1 /* 2 * SH7724 Setup 3 * 4 * Copyright (C) 2009 Renesas Solutions Corp. 5 * 6 * Kuninori Morimoto <morimoto.kuninori@renesas.com> 7 * 8 * Based on SH7723 Setup 9 * Copyright (C) 2008 Paul Mundt 10 * 11 * This file is subject to the terms and conditions of the GNU General Public 12 * License. See the file "COPYING" in the main directory of this archive 13 * for more details. 14 */ 15 #include <linux/platform_device.h> 16 #include <linux/init.h> 17 #include <linux/serial.h> 18 #include <linux/mm.h> 19 #include <linux/serial_sci.h> 20 #include <linux/uio_driver.h> 21 #include <linux/sh_timer.h> 22 #include <linux/io.h> 23 #include <linux/notifier.h> 24 25 #include <asm/suspend.h> 26 #include <asm/clock.h> 27 #include <asm/dmaengine.h> 28 #include <asm/mmzone.h> 29 30 #include <cpu/dma-register.h> 31 #include <cpu/sh7724.h> 32 33 /* DMA */ 34 static struct sh_dmae_channel sh7724_dmae0_channels[] = { 35 { 36 .offset = 0, 37 .dmars = 0, 38 .dmars_bit = 0, 39 }, { 40 .offset = 0x10, 41 .dmars = 0, 42 .dmars_bit = 8, 43 }, { 44 .offset = 0x20, 45 .dmars = 4, 46 .dmars_bit = 0, 47 }, { 48 .offset = 0x30, 49 .dmars = 4, 50 .dmars_bit = 8, 51 }, { 52 .offset = 0x50, 53 .dmars = 8, 54 .dmars_bit = 0, 55 }, { 56 .offset = 0x60, 57 .dmars = 8, 58 .dmars_bit = 8, 59 } 60 }; 61 62 static struct sh_dmae_channel sh7724_dmae1_channels[] = { 63 { 64 .offset = 0, 65 .dmars = 0, 66 .dmars_bit = 0, 67 }, { 68 .offset = 0x10, 69 .dmars = 0, 70 .dmars_bit = 8, 71 }, { 72 .offset = 0x20, 73 .dmars = 4, 74 .dmars_bit = 0, 75 }, { 76 .offset = 0x30, 77 .dmars = 4, 78 .dmars_bit = 8, 79 }, { 80 .offset = 0x50, 81 .dmars = 8, 82 .dmars_bit = 0, 83 }, { 84 .offset = 0x60, 85 .dmars = 8, 86 .dmars_bit = 8, 87 } 88 }; 89 90 static unsigned int ts_shift[] = TS_SHIFT; 91 92 static struct sh_dmae_pdata dma0_platform_data = { 93 .channel = sh7724_dmae0_channels, 94 .channel_num = ARRAY_SIZE(sh7724_dmae0_channels), 95 .ts_low_shift = CHCR_TS_LOW_SHIFT, 96 .ts_low_mask = CHCR_TS_LOW_MASK, 97 .ts_high_shift = CHCR_TS_HIGH_SHIFT, 98 .ts_high_mask = CHCR_TS_HIGH_MASK, 99 .ts_shift = ts_shift, 100 .ts_shift_num = ARRAY_SIZE(ts_shift), 101 .dmaor_init = DMAOR_INIT, 102 }; 103 104 static struct sh_dmae_pdata dma1_platform_data = { 105 .channel = sh7724_dmae1_channels, 106 .channel_num = ARRAY_SIZE(sh7724_dmae1_channels), 107 .ts_low_shift = CHCR_TS_LOW_SHIFT, 108 .ts_low_mask = CHCR_TS_LOW_MASK, 109 .ts_high_shift = CHCR_TS_HIGH_SHIFT, 110 .ts_high_mask = CHCR_TS_HIGH_MASK, 111 .ts_shift = ts_shift, 112 .ts_shift_num = ARRAY_SIZE(ts_shift), 113 .dmaor_init = DMAOR_INIT, 114 }; 115 116 /* Resource order important! */ 117 static struct resource sh7724_dmae0_resources[] = { 118 { 119 /* Channel registers and DMAOR */ 120 .start = 0xfe008020, 121 .end = 0xfe00808f, 122 .flags = IORESOURCE_MEM, 123 }, 124 { 125 /* DMARSx */ 126 .start = 0xfe009000, 127 .end = 0xfe00900b, 128 .flags = IORESOURCE_MEM, 129 }, 130 { 131 /* DMA error IRQ */ 132 .start = 78, 133 .end = 78, 134 .flags = IORESOURCE_IRQ, 135 }, 136 { 137 /* IRQ for channels 0-3 */ 138 .start = 48, 139 .end = 51, 140 .flags = IORESOURCE_IRQ, 141 }, 142 { 143 /* IRQ for channels 4-5 */ 144 .start = 76, 145 .end = 77, 146 .flags = IORESOURCE_IRQ, 147 }, 148 }; 149 150 /* Resource order important! */ 151 static struct resource sh7724_dmae1_resources[] = { 152 { 153 /* Channel registers and DMAOR */ 154 .start = 0xfdc08020, 155 .end = 0xfdc0808f, 156 .flags = IORESOURCE_MEM, 157 }, 158 { 159 /* DMARSx */ 160 .start = 0xfdc09000, 161 .end = 0xfdc0900b, 162 .flags = IORESOURCE_MEM, 163 }, 164 { 165 /* DMA error IRQ */ 166 .start = 74, 167 .end = 74, 168 .flags = IORESOURCE_IRQ, 169 }, 170 { 171 /* IRQ for channels 0-3 */ 172 .start = 40, 173 .end = 43, 174 .flags = IORESOURCE_IRQ, 175 }, 176 { 177 /* IRQ for channels 4-5 */ 178 .start = 72, 179 .end = 73, 180 .flags = IORESOURCE_IRQ, 181 }, 182 }; 183 184 static struct platform_device dma0_device = { 185 .name = "sh-dma-engine", 186 .id = 0, 187 .resource = sh7724_dmae0_resources, 188 .num_resources = ARRAY_SIZE(sh7724_dmae0_resources), 189 .dev = { 190 .platform_data = &dma0_platform_data, 191 }, 192 }; 193 194 static struct platform_device dma1_device = { 195 .name = "sh-dma-engine", 196 .id = 1, 197 .resource = sh7724_dmae1_resources, 198 .num_resources = ARRAY_SIZE(sh7724_dmae1_resources), 199 .dev = { 200 .platform_data = &dma1_platform_data, 201 }, 202 }; 203 204 /* Serial */ 205 static struct plat_sci_port scif0_platform_data = { 206 .mapbase = 0xffe00000, 207 .flags = UPF_BOOT_AUTOCONF, 208 .type = PORT_SCIF, 209 .irqs = { 80, 80, 80, 80 }, 210 .clk = "scif0", 211 }; 212 213 static struct platform_device scif0_device = { 214 .name = "sh-sci", 215 .id = 0, 216 .dev = { 217 .platform_data = &scif0_platform_data, 218 }, 219 }; 220 221 static struct plat_sci_port scif1_platform_data = { 222 .mapbase = 0xffe10000, 223 .flags = UPF_BOOT_AUTOCONF, 224 .type = PORT_SCIF, 225 .irqs = { 81, 81, 81, 81 }, 226 .clk = "scif1", 227 }; 228 229 static struct platform_device scif1_device = { 230 .name = "sh-sci", 231 .id = 1, 232 .dev = { 233 .platform_data = &scif1_platform_data, 234 }, 235 }; 236 237 static struct plat_sci_port scif2_platform_data = { 238 .mapbase = 0xffe20000, 239 .flags = UPF_BOOT_AUTOCONF, 240 .type = PORT_SCIF, 241 .irqs = { 82, 82, 82, 82 }, 242 .clk = "scif2", 243 }; 244 245 static struct platform_device scif2_device = { 246 .name = "sh-sci", 247 .id = 2, 248 .dev = { 249 .platform_data = &scif2_platform_data, 250 }, 251 }; 252 253 static struct plat_sci_port scif3_platform_data = { 254 .mapbase = 0xa4e30000, 255 .flags = UPF_BOOT_AUTOCONF, 256 .type = PORT_SCIFA, 257 .irqs = { 56, 56, 56, 56 }, 258 .clk = "scif3", 259 }; 260 261 static struct platform_device scif3_device = { 262 .name = "sh-sci", 263 .id = 3, 264 .dev = { 265 .platform_data = &scif3_platform_data, 266 }, 267 }; 268 269 static struct plat_sci_port scif4_platform_data = { 270 .mapbase = 0xa4e40000, 271 .flags = UPF_BOOT_AUTOCONF, 272 .type = PORT_SCIFA, 273 .irqs = { 88, 88, 88, 88 }, 274 .clk = "scif4", 275 }; 276 277 static struct platform_device scif4_device = { 278 .name = "sh-sci", 279 .id = 4, 280 .dev = { 281 .platform_data = &scif4_platform_data, 282 }, 283 }; 284 285 static struct plat_sci_port scif5_platform_data = { 286 .mapbase = 0xa4e50000, 287 .flags = UPF_BOOT_AUTOCONF, 288 .type = PORT_SCIFA, 289 .irqs = { 109, 109, 109, 109 }, 290 .clk = "scif5", 291 }; 292 293 static struct platform_device scif5_device = { 294 .name = "sh-sci", 295 .id = 5, 296 .dev = { 297 .platform_data = &scif5_platform_data, 298 }, 299 }; 300 301 /* RTC */ 302 static struct resource rtc_resources[] = { 303 [0] = { 304 .start = 0xa465fec0, 305 .end = 0xa465fec0 + 0x58 - 1, 306 .flags = IORESOURCE_IO, 307 }, 308 [1] = { 309 /* Period IRQ */ 310 .start = 69, 311 .flags = IORESOURCE_IRQ, 312 }, 313 [2] = { 314 /* Carry IRQ */ 315 .start = 70, 316 .flags = IORESOURCE_IRQ, 317 }, 318 [3] = { 319 /* Alarm IRQ */ 320 .start = 68, 321 .flags = IORESOURCE_IRQ, 322 }, 323 }; 324 325 static struct platform_device rtc_device = { 326 .name = "sh-rtc", 327 .id = -1, 328 .num_resources = ARRAY_SIZE(rtc_resources), 329 .resource = rtc_resources, 330 .archdata = { 331 .hwblk_id = HWBLK_RTC, 332 }, 333 }; 334 335 /* I2C0 */ 336 static struct resource iic0_resources[] = { 337 [0] = { 338 .name = "IIC0", 339 .start = 0x04470000, 340 .end = 0x04470018 - 1, 341 .flags = IORESOURCE_MEM, 342 }, 343 [1] = { 344 .start = 96, 345 .end = 99, 346 .flags = IORESOURCE_IRQ, 347 }, 348 }; 349 350 static struct platform_device iic0_device = { 351 .name = "i2c-sh_mobile", 352 .id = 0, /* "i2c0" clock */ 353 .num_resources = ARRAY_SIZE(iic0_resources), 354 .resource = iic0_resources, 355 .archdata = { 356 .hwblk_id = HWBLK_IIC0, 357 }, 358 }; 359 360 /* I2C1 */ 361 static struct resource iic1_resources[] = { 362 [0] = { 363 .name = "IIC1", 364 .start = 0x04750000, 365 .end = 0x04750018 - 1, 366 .flags = IORESOURCE_MEM, 367 }, 368 [1] = { 369 .start = 92, 370 .end = 95, 371 .flags = IORESOURCE_IRQ, 372 }, 373 }; 374 375 static struct platform_device iic1_device = { 376 .name = "i2c-sh_mobile", 377 .id = 1, /* "i2c1" clock */ 378 .num_resources = ARRAY_SIZE(iic1_resources), 379 .resource = iic1_resources, 380 .archdata = { 381 .hwblk_id = HWBLK_IIC1, 382 }, 383 }; 384 385 /* VPU */ 386 static struct uio_info vpu_platform_data = { 387 .name = "VPU5F", 388 .version = "0", 389 .irq = 60, 390 }; 391 392 static struct resource vpu_resources[] = { 393 [0] = { 394 .name = "VPU", 395 .start = 0xfe900000, 396 .end = 0xfe902807, 397 .flags = IORESOURCE_MEM, 398 }, 399 [1] = { 400 /* place holder for contiguous memory */ 401 }, 402 }; 403 404 static struct platform_device vpu_device = { 405 .name = "uio_pdrv_genirq", 406 .id = 0, 407 .dev = { 408 .platform_data = &vpu_platform_data, 409 }, 410 .resource = vpu_resources, 411 .num_resources = ARRAY_SIZE(vpu_resources), 412 .archdata = { 413 .hwblk_id = HWBLK_VPU, 414 }, 415 }; 416 417 /* VEU0 */ 418 static struct uio_info veu0_platform_data = { 419 .name = "VEU3F0", 420 .version = "0", 421 .irq = 83, 422 }; 423 424 static struct resource veu0_resources[] = { 425 [0] = { 426 .name = "VEU3F0", 427 .start = 0xfe920000, 428 .end = 0xfe9200cb, 429 .flags = IORESOURCE_MEM, 430 }, 431 [1] = { 432 /* place holder for contiguous memory */ 433 }, 434 }; 435 436 static struct platform_device veu0_device = { 437 .name = "uio_pdrv_genirq", 438 .id = 1, 439 .dev = { 440 .platform_data = &veu0_platform_data, 441 }, 442 .resource = veu0_resources, 443 .num_resources = ARRAY_SIZE(veu0_resources), 444 .archdata = { 445 .hwblk_id = HWBLK_VEU0, 446 }, 447 }; 448 449 /* VEU1 */ 450 static struct uio_info veu1_platform_data = { 451 .name = "VEU3F1", 452 .version = "0", 453 .irq = 54, 454 }; 455 456 static struct resource veu1_resources[] = { 457 [0] = { 458 .name = "VEU3F1", 459 .start = 0xfe924000, 460 .end = 0xfe9240cb, 461 .flags = IORESOURCE_MEM, 462 }, 463 [1] = { 464 /* place holder for contiguous memory */ 465 }, 466 }; 467 468 static struct platform_device veu1_device = { 469 .name = "uio_pdrv_genirq", 470 .id = 2, 471 .dev = { 472 .platform_data = &veu1_platform_data, 473 }, 474 .resource = veu1_resources, 475 .num_resources = ARRAY_SIZE(veu1_resources), 476 .archdata = { 477 .hwblk_id = HWBLK_VEU1, 478 }, 479 }; 480 481 static struct sh_timer_config cmt_platform_data = { 482 .name = "CMT", 483 .channel_offset = 0x60, 484 .timer_bit = 5, 485 .clk = "cmt0", 486 .clockevent_rating = 125, 487 .clocksource_rating = 200, 488 }; 489 490 static struct resource cmt_resources[] = { 491 [0] = { 492 .name = "CMT", 493 .start = 0x044a0060, 494 .end = 0x044a006b, 495 .flags = IORESOURCE_MEM, 496 }, 497 [1] = { 498 .start = 104, 499 .flags = IORESOURCE_IRQ, 500 }, 501 }; 502 503 static struct platform_device cmt_device = { 504 .name = "sh_cmt", 505 .id = 0, 506 .dev = { 507 .platform_data = &cmt_platform_data, 508 }, 509 .resource = cmt_resources, 510 .num_resources = ARRAY_SIZE(cmt_resources), 511 .archdata = { 512 .hwblk_id = HWBLK_CMT, 513 }, 514 }; 515 516 static struct sh_timer_config tmu0_platform_data = { 517 .name = "TMU0", 518 .channel_offset = 0x04, 519 .timer_bit = 0, 520 .clk = "tmu0", 521 .clockevent_rating = 200, 522 }; 523 524 static struct resource tmu0_resources[] = { 525 [0] = { 526 .name = "TMU0", 527 .start = 0xffd80008, 528 .end = 0xffd80013, 529 .flags = IORESOURCE_MEM, 530 }, 531 [1] = { 532 .start = 16, 533 .flags = IORESOURCE_IRQ, 534 }, 535 }; 536 537 static struct platform_device tmu0_device = { 538 .name = "sh_tmu", 539 .id = 0, 540 .dev = { 541 .platform_data = &tmu0_platform_data, 542 }, 543 .resource = tmu0_resources, 544 .num_resources = ARRAY_SIZE(tmu0_resources), 545 .archdata = { 546 .hwblk_id = HWBLK_TMU0, 547 }, 548 }; 549 550 static struct sh_timer_config tmu1_platform_data = { 551 .name = "TMU1", 552 .channel_offset = 0x10, 553 .timer_bit = 1, 554 .clk = "tmu0", 555 .clocksource_rating = 200, 556 }; 557 558 static struct resource tmu1_resources[] = { 559 [0] = { 560 .name = "TMU1", 561 .start = 0xffd80014, 562 .end = 0xffd8001f, 563 .flags = IORESOURCE_MEM, 564 }, 565 [1] = { 566 .start = 17, 567 .flags = IORESOURCE_IRQ, 568 }, 569 }; 570 571 static struct platform_device tmu1_device = { 572 .name = "sh_tmu", 573 .id = 1, 574 .dev = { 575 .platform_data = &tmu1_platform_data, 576 }, 577 .resource = tmu1_resources, 578 .num_resources = ARRAY_SIZE(tmu1_resources), 579 .archdata = { 580 .hwblk_id = HWBLK_TMU0, 581 }, 582 }; 583 584 static struct sh_timer_config tmu2_platform_data = { 585 .name = "TMU2", 586 .channel_offset = 0x1c, 587 .timer_bit = 2, 588 .clk = "tmu0", 589 }; 590 591 static struct resource tmu2_resources[] = { 592 [0] = { 593 .name = "TMU2", 594 .start = 0xffd80020, 595 .end = 0xffd8002b, 596 .flags = IORESOURCE_MEM, 597 }, 598 [1] = { 599 .start = 18, 600 .flags = IORESOURCE_IRQ, 601 }, 602 }; 603 604 static struct platform_device tmu2_device = { 605 .name = "sh_tmu", 606 .id = 2, 607 .dev = { 608 .platform_data = &tmu2_platform_data, 609 }, 610 .resource = tmu2_resources, 611 .num_resources = ARRAY_SIZE(tmu2_resources), 612 .archdata = { 613 .hwblk_id = HWBLK_TMU0, 614 }, 615 }; 616 617 618 static struct sh_timer_config tmu3_platform_data = { 619 .name = "TMU3", 620 .channel_offset = 0x04, 621 .timer_bit = 0, 622 .clk = "tmu1", 623 }; 624 625 static struct resource tmu3_resources[] = { 626 [0] = { 627 .name = "TMU3", 628 .start = 0xffd90008, 629 .end = 0xffd90013, 630 .flags = IORESOURCE_MEM, 631 }, 632 [1] = { 633 .start = 57, 634 .flags = IORESOURCE_IRQ, 635 }, 636 }; 637 638 static struct platform_device tmu3_device = { 639 .name = "sh_tmu", 640 .id = 3, 641 .dev = { 642 .platform_data = &tmu3_platform_data, 643 }, 644 .resource = tmu3_resources, 645 .num_resources = ARRAY_SIZE(tmu3_resources), 646 .archdata = { 647 .hwblk_id = HWBLK_TMU1, 648 }, 649 }; 650 651 static struct sh_timer_config tmu4_platform_data = { 652 .name = "TMU4", 653 .channel_offset = 0x10, 654 .timer_bit = 1, 655 .clk = "tmu1", 656 }; 657 658 static struct resource tmu4_resources[] = { 659 [0] = { 660 .name = "TMU4", 661 .start = 0xffd90014, 662 .end = 0xffd9001f, 663 .flags = IORESOURCE_MEM, 664 }, 665 [1] = { 666 .start = 58, 667 .flags = IORESOURCE_IRQ, 668 }, 669 }; 670 671 static struct platform_device tmu4_device = { 672 .name = "sh_tmu", 673 .id = 4, 674 .dev = { 675 .platform_data = &tmu4_platform_data, 676 }, 677 .resource = tmu4_resources, 678 .num_resources = ARRAY_SIZE(tmu4_resources), 679 .archdata = { 680 .hwblk_id = HWBLK_TMU1, 681 }, 682 }; 683 684 static struct sh_timer_config tmu5_platform_data = { 685 .name = "TMU5", 686 .channel_offset = 0x1c, 687 .timer_bit = 2, 688 .clk = "tmu1", 689 }; 690 691 static struct resource tmu5_resources[] = { 692 [0] = { 693 .name = "TMU5", 694 .start = 0xffd90020, 695 .end = 0xffd9002b, 696 .flags = IORESOURCE_MEM, 697 }, 698 [1] = { 699 .start = 57, 700 .flags = IORESOURCE_IRQ, 701 }, 702 }; 703 704 static struct platform_device tmu5_device = { 705 .name = "sh_tmu", 706 .id = 5, 707 .dev = { 708 .platform_data = &tmu5_platform_data, 709 }, 710 .resource = tmu5_resources, 711 .num_resources = ARRAY_SIZE(tmu5_resources), 712 .archdata = { 713 .hwblk_id = HWBLK_TMU1, 714 }, 715 }; 716 717 /* JPU */ 718 static struct uio_info jpu_platform_data = { 719 .name = "JPU", 720 .version = "0", 721 .irq = 27, 722 }; 723 724 static struct resource jpu_resources[] = { 725 [0] = { 726 .name = "JPU", 727 .start = 0xfe980000, 728 .end = 0xfe9902d3, 729 .flags = IORESOURCE_MEM, 730 }, 731 [1] = { 732 /* place holder for contiguous memory */ 733 }, 734 }; 735 736 static struct platform_device jpu_device = { 737 .name = "uio_pdrv_genirq", 738 .id = 3, 739 .dev = { 740 .platform_data = &jpu_platform_data, 741 }, 742 .resource = jpu_resources, 743 .num_resources = ARRAY_SIZE(jpu_resources), 744 .archdata = { 745 .hwblk_id = HWBLK_JPU, 746 }, 747 }; 748 749 /* SPU2DSP0 */ 750 static struct uio_info spu0_platform_data = { 751 .name = "SPU2DSP0", 752 .version = "0", 753 .irq = 86, 754 }; 755 756 static struct resource spu0_resources[] = { 757 [0] = { 758 .name = "SPU2DSP0", 759 .start = 0xFE200000, 760 .end = 0xFE2FFFFF, 761 .flags = IORESOURCE_MEM, 762 }, 763 [1] = { 764 /* place holder for contiguous memory */ 765 }, 766 }; 767 768 static struct platform_device spu0_device = { 769 .name = "uio_pdrv_genirq", 770 .id = 4, 771 .dev = { 772 .platform_data = &spu0_platform_data, 773 }, 774 .resource = spu0_resources, 775 .num_resources = ARRAY_SIZE(spu0_resources), 776 .archdata = { 777 .hwblk_id = HWBLK_SPU, 778 }, 779 }; 780 781 /* SPU2DSP1 */ 782 static struct uio_info spu1_platform_data = { 783 .name = "SPU2DSP1", 784 .version = "0", 785 .irq = 87, 786 }; 787 788 static struct resource spu1_resources[] = { 789 [0] = { 790 .name = "SPU2DSP1", 791 .start = 0xFE300000, 792 .end = 0xFE3FFFFF, 793 .flags = IORESOURCE_MEM, 794 }, 795 [1] = { 796 /* place holder for contiguous memory */ 797 }, 798 }; 799 800 static struct platform_device spu1_device = { 801 .name = "uio_pdrv_genirq", 802 .id = 5, 803 .dev = { 804 .platform_data = &spu1_platform_data, 805 }, 806 .resource = spu1_resources, 807 .num_resources = ARRAY_SIZE(spu1_resources), 808 .archdata = { 809 .hwblk_id = HWBLK_SPU, 810 }, 811 }; 812 813 static struct platform_device *sh7724_devices[] __initdata = { 814 &scif0_device, 815 &scif1_device, 816 &scif2_device, 817 &scif3_device, 818 &scif4_device, 819 &scif5_device, 820 &cmt_device, 821 &tmu0_device, 822 &tmu1_device, 823 &tmu2_device, 824 &tmu3_device, 825 &tmu4_device, 826 &tmu5_device, 827 &dma0_device, 828 &dma1_device, 829 &rtc_device, 830 &iic0_device, 831 &iic1_device, 832 &vpu_device, 833 &veu0_device, 834 &veu1_device, 835 &jpu_device, 836 &spu0_device, 837 &spu1_device, 838 }; 839 840 static int __init sh7724_devices_setup(void) 841 { 842 platform_resource_setup_memory(&vpu_device, "vpu", 2 << 20); 843 platform_resource_setup_memory(&veu0_device, "veu0", 2 << 20); 844 platform_resource_setup_memory(&veu1_device, "veu1", 2 << 20); 845 platform_resource_setup_memory(&jpu_device, "jpu", 2 << 20); 846 platform_resource_setup_memory(&spu0_device, "spu0", 2 << 20); 847 platform_resource_setup_memory(&spu1_device, "spu1", 2 << 20); 848 849 return platform_add_devices(sh7724_devices, 850 ARRAY_SIZE(sh7724_devices)); 851 } 852 arch_initcall(sh7724_devices_setup); 853 854 static struct platform_device *sh7724_early_devices[] __initdata = { 855 &scif0_device, 856 &scif1_device, 857 &scif2_device, 858 &scif3_device, 859 &scif4_device, 860 &scif5_device, 861 &cmt_device, 862 &tmu0_device, 863 &tmu1_device, 864 &tmu2_device, 865 &tmu3_device, 866 &tmu4_device, 867 &tmu5_device, 868 }; 869 870 void __init plat_early_device_setup(void) 871 { 872 early_platform_add_devices(sh7724_early_devices, 873 ARRAY_SIZE(sh7724_early_devices)); 874 } 875 876 #define RAMCR_CACHE_L2FC 0x0002 877 #define RAMCR_CACHE_L2E 0x0001 878 #define L2_CACHE_ENABLE (RAMCR_CACHE_L2E|RAMCR_CACHE_L2FC) 879 880 void l2_cache_init(void) 881 { 882 /* Enable L2 cache */ 883 __raw_writel(L2_CACHE_ENABLE, RAMCR); 884 } 885 886 enum { 887 UNUSED = 0, 888 ENABLED, 889 DISABLED, 890 891 /* interrupt sources */ 892 IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7, 893 HUDI, 894 DMAC1A_DEI0, DMAC1A_DEI1, DMAC1A_DEI2, DMAC1A_DEI3, 895 _2DG_TRI, _2DG_INI, _2DG_CEI, 896 DMAC0A_DEI0, DMAC0A_DEI1, DMAC0A_DEI2, DMAC0A_DEI3, 897 VIO_CEU0, VIO_BEU0, VIO_VEU1, VIO_VOU, 898 SCIFA3, 899 VPU, 900 TPU, 901 CEU1, 902 BEU1, 903 USB0, USB1, 904 ATAPI, 905 RTC_ATI, RTC_PRI, RTC_CUI, 906 DMAC1B_DEI4, DMAC1B_DEI5, DMAC1B_DADERR, 907 DMAC0B_DEI4, DMAC0B_DEI5, DMAC0B_DADERR, 908 KEYSC, 909 SCIF_SCIF0, SCIF_SCIF1, SCIF_SCIF2, 910 VEU0, 911 MSIOF_MSIOFI0, MSIOF_MSIOFI1, 912 SPU_SPUI0, SPU_SPUI1, 913 SCIFA4, 914 ICB, 915 ETHI, 916 I2C1_ALI, I2C1_TACKI, I2C1_WAITI, I2C1_DTEI, 917 I2C0_ALI, I2C0_TACKI, I2C0_WAITI, I2C0_DTEI, 918 CMT, 919 TSIF, 920 FSI, 921 SCIFA5, 922 TMU0_TUNI0, TMU0_TUNI1, TMU0_TUNI2, 923 IRDA, 924 JPU, 925 _2DDMAC, 926 MMC_MMC2I, MMC_MMC3I, 927 LCDC, 928 TMU1_TUNI0, TMU1_TUNI1, TMU1_TUNI2, 929 930 /* interrupt groups */ 931 DMAC1A, _2DG, DMAC0A, VIO, USB, RTC, 932 DMAC1B, DMAC0B, I2C0, I2C1, SDHI0, SDHI1, SPU, MMCIF, 933 }; 934 935 static struct intc_vect vectors[] __initdata = { 936 INTC_VECT(IRQ0, 0x600), INTC_VECT(IRQ1, 0x620), 937 INTC_VECT(IRQ2, 0x640), INTC_VECT(IRQ3, 0x660), 938 INTC_VECT(IRQ4, 0x680), INTC_VECT(IRQ5, 0x6a0), 939 INTC_VECT(IRQ6, 0x6c0), INTC_VECT(IRQ7, 0x6e0), 940 941 INTC_VECT(DMAC1A_DEI0, 0x700), 942 INTC_VECT(DMAC1A_DEI1, 0x720), 943 INTC_VECT(DMAC1A_DEI2, 0x740), 944 INTC_VECT(DMAC1A_DEI3, 0x760), 945 946 INTC_VECT(_2DG_TRI, 0x780), 947 INTC_VECT(_2DG_INI, 0x7A0), 948 INTC_VECT(_2DG_CEI, 0x7C0), 949 950 INTC_VECT(DMAC0A_DEI0, 0x800), 951 INTC_VECT(DMAC0A_DEI1, 0x820), 952 INTC_VECT(DMAC0A_DEI2, 0x840), 953 INTC_VECT(DMAC0A_DEI3, 0x860), 954 955 INTC_VECT(VIO_CEU0, 0x880), 956 INTC_VECT(VIO_BEU0, 0x8A0), 957 INTC_VECT(VIO_VEU1, 0x8C0), 958 INTC_VECT(VIO_VOU, 0x8E0), 959 960 INTC_VECT(SCIFA3, 0x900), 961 INTC_VECT(VPU, 0x980), 962 INTC_VECT(TPU, 0x9A0), 963 INTC_VECT(CEU1, 0x9E0), 964 INTC_VECT(BEU1, 0xA00), 965 INTC_VECT(USB0, 0xA20), 966 INTC_VECT(USB1, 0xA40), 967 INTC_VECT(ATAPI, 0xA60), 968 969 INTC_VECT(RTC_ATI, 0xA80), 970 INTC_VECT(RTC_PRI, 0xAA0), 971 INTC_VECT(RTC_CUI, 0xAC0), 972 973 INTC_VECT(DMAC1B_DEI4, 0xB00), 974 INTC_VECT(DMAC1B_DEI5, 0xB20), 975 INTC_VECT(DMAC1B_DADERR, 0xB40), 976 977 INTC_VECT(DMAC0B_DEI4, 0xB80), 978 INTC_VECT(DMAC0B_DEI5, 0xBA0), 979 INTC_VECT(DMAC0B_DADERR, 0xBC0), 980 981 INTC_VECT(KEYSC, 0xBE0), 982 INTC_VECT(SCIF_SCIF0, 0xC00), 983 INTC_VECT(SCIF_SCIF1, 0xC20), 984 INTC_VECT(SCIF_SCIF2, 0xC40), 985 INTC_VECT(VEU0, 0xC60), 986 INTC_VECT(MSIOF_MSIOFI0, 0xC80), 987 INTC_VECT(MSIOF_MSIOFI1, 0xCA0), 988 INTC_VECT(SPU_SPUI0, 0xCC0), 989 INTC_VECT(SPU_SPUI1, 0xCE0), 990 INTC_VECT(SCIFA4, 0xD00), 991 992 INTC_VECT(ICB, 0xD20), 993 INTC_VECT(ETHI, 0xD60), 994 995 INTC_VECT(I2C1_ALI, 0xD80), 996 INTC_VECT(I2C1_TACKI, 0xDA0), 997 INTC_VECT(I2C1_WAITI, 0xDC0), 998 INTC_VECT(I2C1_DTEI, 0xDE0), 999 1000 INTC_VECT(I2C0_ALI, 0xE00), 1001 INTC_VECT(I2C0_TACKI, 0xE20), 1002 INTC_VECT(I2C0_WAITI, 0xE40), 1003 INTC_VECT(I2C0_DTEI, 0xE60), 1004 1005 INTC_VECT(SDHI0, 0xE80), 1006 INTC_VECT(SDHI0, 0xEA0), 1007 INTC_VECT(SDHI0, 0xEC0), 1008 INTC_VECT(SDHI0, 0xEE0), 1009 1010 INTC_VECT(CMT, 0xF00), 1011 INTC_VECT(TSIF, 0xF20), 1012 INTC_VECT(FSI, 0xF80), 1013 INTC_VECT(SCIFA5, 0xFA0), 1014 1015 INTC_VECT(TMU0_TUNI0, 0x400), 1016 INTC_VECT(TMU0_TUNI1, 0x420), 1017 INTC_VECT(TMU0_TUNI2, 0x440), 1018 1019 INTC_VECT(IRDA, 0x480), 1020 1021 INTC_VECT(SDHI1, 0x4E0), 1022 INTC_VECT(SDHI1, 0x500), 1023 INTC_VECT(SDHI1, 0x520), 1024 1025 INTC_VECT(JPU, 0x560), 1026 INTC_VECT(_2DDMAC, 0x4A0), 1027 1028 INTC_VECT(MMC_MMC2I, 0x5A0), 1029 INTC_VECT(MMC_MMC3I, 0x5C0), 1030 1031 INTC_VECT(LCDC, 0xF40), 1032 1033 INTC_VECT(TMU1_TUNI0, 0x920), 1034 INTC_VECT(TMU1_TUNI1, 0x940), 1035 INTC_VECT(TMU1_TUNI2, 0x960), 1036 }; 1037 1038 static struct intc_group groups[] __initdata = { 1039 INTC_GROUP(DMAC1A, DMAC1A_DEI0, DMAC1A_DEI1, DMAC1A_DEI2, DMAC1A_DEI3), 1040 INTC_GROUP(_2DG, _2DG_TRI, _2DG_INI, _2DG_CEI), 1041 INTC_GROUP(DMAC0A, DMAC0A_DEI0, DMAC0A_DEI1, DMAC0A_DEI2, DMAC0A_DEI3), 1042 INTC_GROUP(VIO, VIO_CEU0, VIO_BEU0, VIO_VEU1, VIO_VOU), 1043 INTC_GROUP(USB, USB0, USB1), 1044 INTC_GROUP(RTC, RTC_ATI, RTC_PRI, RTC_CUI), 1045 INTC_GROUP(DMAC1B, DMAC1B_DEI4, DMAC1B_DEI5, DMAC1B_DADERR), 1046 INTC_GROUP(DMAC0B, DMAC0B_DEI4, DMAC0B_DEI5, DMAC0B_DADERR), 1047 INTC_GROUP(I2C0, I2C0_ALI, I2C0_TACKI, I2C0_WAITI, I2C0_DTEI), 1048 INTC_GROUP(I2C1, I2C1_ALI, I2C1_TACKI, I2C1_WAITI, I2C1_DTEI), 1049 INTC_GROUP(SPU, SPU_SPUI0, SPU_SPUI1), 1050 INTC_GROUP(MMCIF, MMC_MMC2I, MMC_MMC3I), 1051 }; 1052 1053 static struct intc_mask_reg mask_registers[] __initdata = { 1054 { 0xa4080080, 0xa40800c0, 8, /* IMR0 / IMCR0 */ 1055 { 0, TMU1_TUNI2, TMU1_TUNI1, TMU1_TUNI0, 1056 0, DISABLED, ENABLED, ENABLED } }, 1057 { 0xa4080084, 0xa40800c4, 8, /* IMR1 / IMCR1 */ 1058 { VIO_VOU, VIO_VEU1, VIO_BEU0, VIO_CEU0, 1059 DMAC0A_DEI3, DMAC0A_DEI2, DMAC0A_DEI1, DMAC0A_DEI0 } }, 1060 { 0xa4080088, 0xa40800c8, 8, /* IMR2 / IMCR2 */ 1061 { 0, 0, 0, VPU, ATAPI, ETHI, 0, SCIFA3 } }, 1062 { 0xa408008c, 0xa40800cc, 8, /* IMR3 / IMCR3 */ 1063 { DMAC1A_DEI3, DMAC1A_DEI2, DMAC1A_DEI1, DMAC1A_DEI0, 1064 SPU_SPUI1, SPU_SPUI0, BEU1, IRDA } }, 1065 { 0xa4080090, 0xa40800d0, 8, /* IMR4 / IMCR4 */ 1066 { 0, TMU0_TUNI2, TMU0_TUNI1, TMU0_TUNI0, 1067 JPU, 0, 0, LCDC } }, 1068 { 0xa4080094, 0xa40800d4, 8, /* IMR5 / IMCR5 */ 1069 { KEYSC, DMAC0B_DADERR, DMAC0B_DEI5, DMAC0B_DEI4, 1070 VEU0, SCIF_SCIF2, SCIF_SCIF1, SCIF_SCIF0 } }, 1071 { 0xa4080098, 0xa40800d8, 8, /* IMR6 / IMCR6 */ 1072 { 0, 0, ICB, SCIFA4, 1073 CEU1, 0, MSIOF_MSIOFI1, MSIOF_MSIOFI0 } }, 1074 { 0xa408009c, 0xa40800dc, 8, /* IMR7 / IMCR7 */ 1075 { I2C0_DTEI, I2C0_WAITI, I2C0_TACKI, I2C0_ALI, 1076 I2C1_DTEI, I2C1_WAITI, I2C1_TACKI, I2C1_ALI } }, 1077 { 0xa40800a0, 0xa40800e0, 8, /* IMR8 / IMCR8 */ 1078 { DISABLED, DISABLED, ENABLED, ENABLED, 1079 0, 0, SCIFA5, FSI } }, 1080 { 0xa40800a4, 0xa40800e4, 8, /* IMR9 / IMCR9 */ 1081 { 0, 0, 0, CMT, 0, USB1, USB0, 0 } }, 1082 { 0xa40800a8, 0xa40800e8, 8, /* IMR10 / IMCR10 */ 1083 { 0, DMAC1B_DADERR, DMAC1B_DEI5, DMAC1B_DEI4, 1084 0, RTC_CUI, RTC_PRI, RTC_ATI } }, 1085 { 0xa40800ac, 0xa40800ec, 8, /* IMR11 / IMCR11 */ 1086 { 0, _2DG_CEI, _2DG_INI, _2DG_TRI, 1087 0, TPU, 0, TSIF } }, 1088 { 0xa40800b0, 0xa40800f0, 8, /* IMR12 / IMCR12 */ 1089 { 0, 0, MMC_MMC3I, MMC_MMC2I, 0, 0, 0, _2DDMAC } }, 1090 { 0xa4140044, 0xa4140064, 8, /* INTMSK00 / INTMSKCLR00 */ 1091 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } }, 1092 }; 1093 1094 static struct intc_prio_reg prio_registers[] __initdata = { 1095 { 0xa4080000, 0, 16, 4, /* IPRA */ { TMU0_TUNI0, TMU0_TUNI1, 1096 TMU0_TUNI2, IRDA } }, 1097 { 0xa4080004, 0, 16, 4, /* IPRB */ { JPU, LCDC, DMAC1A, BEU1 } }, 1098 { 0xa4080008, 0, 16, 4, /* IPRC */ { TMU1_TUNI0, TMU1_TUNI1, 1099 TMU1_TUNI2, SPU } }, 1100 { 0xa408000c, 0, 16, 4, /* IPRD */ { 0, MMCIF, 0, ATAPI } }, 1101 { 0xa4080010, 0, 16, 4, /* IPRE */ { DMAC0A, VIO, SCIFA3, VPU } }, 1102 { 0xa4080014, 0, 16, 4, /* IPRF */ { KEYSC, DMAC0B, USB, CMT } }, 1103 { 0xa4080018, 0, 16, 4, /* IPRG */ { SCIF_SCIF0, SCIF_SCIF1, 1104 SCIF_SCIF2, VEU0 } }, 1105 { 0xa408001c, 0, 16, 4, /* IPRH */ { MSIOF_MSIOFI0, MSIOF_MSIOFI1, 1106 I2C1, I2C0 } }, 1107 { 0xa4080020, 0, 16, 4, /* IPRI */ { SCIFA4, ICB, TSIF, _2DG } }, 1108 { 0xa4080024, 0, 16, 4, /* IPRJ */ { CEU1, ETHI, FSI, SDHI1 } }, 1109 { 0xa4080028, 0, 16, 4, /* IPRK */ { RTC, DMAC1B, 0, SDHI0 } }, 1110 { 0xa408002c, 0, 16, 4, /* IPRL */ { SCIFA5, 0, TPU, _2DDMAC } }, 1111 { 0xa4140010, 0, 32, 4, /* INTPRI00 */ 1112 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } }, 1113 }; 1114 1115 static struct intc_sense_reg sense_registers[] __initdata = { 1116 { 0xa414001c, 16, 2, /* ICR1 */ 1117 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } }, 1118 }; 1119 1120 static struct intc_mask_reg ack_registers[] __initdata = { 1121 { 0xa4140024, 0, 8, /* INTREQ00 */ 1122 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } }, 1123 }; 1124 1125 static struct intc_desc intc_desc __initdata = { 1126 .name = "sh7724", 1127 .force_enable = ENABLED, 1128 .force_disable = DISABLED, 1129 .hw = INTC_HW_DESC(vectors, groups, mask_registers, 1130 prio_registers, sense_registers, ack_registers), 1131 }; 1132 1133 void __init plat_irq_setup(void) 1134 { 1135 register_intc_controller(&intc_desc); 1136 } 1137 1138 static struct { 1139 /* BSC */ 1140 unsigned long mmselr; 1141 unsigned long cs0bcr; 1142 unsigned long cs4bcr; 1143 unsigned long cs5abcr; 1144 unsigned long cs5bbcr; 1145 unsigned long cs6abcr; 1146 unsigned long cs6bbcr; 1147 unsigned long cs4wcr; 1148 unsigned long cs5awcr; 1149 unsigned long cs5bwcr; 1150 unsigned long cs6awcr; 1151 unsigned long cs6bwcr; 1152 /* INTC */ 1153 unsigned short ipra; 1154 unsigned short iprb; 1155 unsigned short iprc; 1156 unsigned short iprd; 1157 unsigned short ipre; 1158 unsigned short iprf; 1159 unsigned short iprg; 1160 unsigned short iprh; 1161 unsigned short ipri; 1162 unsigned short iprj; 1163 unsigned short iprk; 1164 unsigned short iprl; 1165 unsigned char imr0; 1166 unsigned char imr1; 1167 unsigned char imr2; 1168 unsigned char imr3; 1169 unsigned char imr4; 1170 unsigned char imr5; 1171 unsigned char imr6; 1172 unsigned char imr7; 1173 unsigned char imr8; 1174 unsigned char imr9; 1175 unsigned char imr10; 1176 unsigned char imr11; 1177 unsigned char imr12; 1178 /* RWDT */ 1179 unsigned short rwtcnt; 1180 unsigned short rwtcsr; 1181 /* CPG */ 1182 unsigned long irdaclk; 1183 unsigned long spuclk; 1184 } sh7724_rstandby_state; 1185 1186 static int sh7724_pre_sleep_notifier_call(struct notifier_block *nb, 1187 unsigned long flags, void *unused) 1188 { 1189 if (!(flags & SUSP_SH_RSTANDBY)) 1190 return NOTIFY_DONE; 1191 1192 /* BCR */ 1193 sh7724_rstandby_state.mmselr = __raw_readl(0xff800020); /* MMSELR */ 1194 sh7724_rstandby_state.mmselr |= 0xa5a50000; 1195 sh7724_rstandby_state.cs0bcr = __raw_readl(0xfec10004); /* CS0BCR */ 1196 sh7724_rstandby_state.cs4bcr = __raw_readl(0xfec10010); /* CS4BCR */ 1197 sh7724_rstandby_state.cs5abcr = __raw_readl(0xfec10014); /* CS5ABCR */ 1198 sh7724_rstandby_state.cs5bbcr = __raw_readl(0xfec10018); /* CS5BBCR */ 1199 sh7724_rstandby_state.cs6abcr = __raw_readl(0xfec1001c); /* CS6ABCR */ 1200 sh7724_rstandby_state.cs6bbcr = __raw_readl(0xfec10020); /* CS6BBCR */ 1201 sh7724_rstandby_state.cs4wcr = __raw_readl(0xfec10030); /* CS4WCR */ 1202 sh7724_rstandby_state.cs5awcr = __raw_readl(0xfec10034); /* CS5AWCR */ 1203 sh7724_rstandby_state.cs5bwcr = __raw_readl(0xfec10038); /* CS5BWCR */ 1204 sh7724_rstandby_state.cs6awcr = __raw_readl(0xfec1003c); /* CS6AWCR */ 1205 sh7724_rstandby_state.cs6bwcr = __raw_readl(0xfec10040); /* CS6BWCR */ 1206 1207 /* INTC */ 1208 sh7724_rstandby_state.ipra = __raw_readw(0xa4080000); /* IPRA */ 1209 sh7724_rstandby_state.iprb = __raw_readw(0xa4080004); /* IPRB */ 1210 sh7724_rstandby_state.iprc = __raw_readw(0xa4080008); /* IPRC */ 1211 sh7724_rstandby_state.iprd = __raw_readw(0xa408000c); /* IPRD */ 1212 sh7724_rstandby_state.ipre = __raw_readw(0xa4080010); /* IPRE */ 1213 sh7724_rstandby_state.iprf = __raw_readw(0xa4080014); /* IPRF */ 1214 sh7724_rstandby_state.iprg = __raw_readw(0xa4080018); /* IPRG */ 1215 sh7724_rstandby_state.iprh = __raw_readw(0xa408001c); /* IPRH */ 1216 sh7724_rstandby_state.ipri = __raw_readw(0xa4080020); /* IPRI */ 1217 sh7724_rstandby_state.iprj = __raw_readw(0xa4080024); /* IPRJ */ 1218 sh7724_rstandby_state.iprk = __raw_readw(0xa4080028); /* IPRK */ 1219 sh7724_rstandby_state.iprl = __raw_readw(0xa408002c); /* IPRL */ 1220 sh7724_rstandby_state.imr0 = __raw_readb(0xa4080080); /* IMR0 */ 1221 sh7724_rstandby_state.imr1 = __raw_readb(0xa4080084); /* IMR1 */ 1222 sh7724_rstandby_state.imr2 = __raw_readb(0xa4080088); /* IMR2 */ 1223 sh7724_rstandby_state.imr3 = __raw_readb(0xa408008c); /* IMR3 */ 1224 sh7724_rstandby_state.imr4 = __raw_readb(0xa4080090); /* IMR4 */ 1225 sh7724_rstandby_state.imr5 = __raw_readb(0xa4080094); /* IMR5 */ 1226 sh7724_rstandby_state.imr6 = __raw_readb(0xa4080098); /* IMR6 */ 1227 sh7724_rstandby_state.imr7 = __raw_readb(0xa408009c); /* IMR7 */ 1228 sh7724_rstandby_state.imr8 = __raw_readb(0xa40800a0); /* IMR8 */ 1229 sh7724_rstandby_state.imr9 = __raw_readb(0xa40800a4); /* IMR9 */ 1230 sh7724_rstandby_state.imr10 = __raw_readb(0xa40800a8); /* IMR10 */ 1231 sh7724_rstandby_state.imr11 = __raw_readb(0xa40800ac); /* IMR11 */ 1232 sh7724_rstandby_state.imr12 = __raw_readb(0xa40800b0); /* IMR12 */ 1233 1234 /* RWDT */ 1235 sh7724_rstandby_state.rwtcnt = __raw_readb(0xa4520000); /* RWTCNT */ 1236 sh7724_rstandby_state.rwtcnt |= 0x5a00; 1237 sh7724_rstandby_state.rwtcsr = __raw_readb(0xa4520004); /* RWTCSR */ 1238 sh7724_rstandby_state.rwtcsr |= 0xa500; 1239 __raw_writew(sh7724_rstandby_state.rwtcsr & 0x07, 0xa4520004); 1240 1241 /* CPG */ 1242 sh7724_rstandby_state.irdaclk = __raw_readl(0xa4150018); /* IRDACLKCR */ 1243 sh7724_rstandby_state.spuclk = __raw_readl(0xa415003c); /* SPUCLKCR */ 1244 1245 return NOTIFY_DONE; 1246 } 1247 1248 static int sh7724_post_sleep_notifier_call(struct notifier_block *nb, 1249 unsigned long flags, void *unused) 1250 { 1251 if (!(flags & SUSP_SH_RSTANDBY)) 1252 return NOTIFY_DONE; 1253 1254 /* BCR */ 1255 __raw_writel(sh7724_rstandby_state.mmselr, 0xff800020); /* MMSELR */ 1256 __raw_writel(sh7724_rstandby_state.cs0bcr, 0xfec10004); /* CS0BCR */ 1257 __raw_writel(sh7724_rstandby_state.cs4bcr, 0xfec10010); /* CS4BCR */ 1258 __raw_writel(sh7724_rstandby_state.cs5abcr, 0xfec10014); /* CS5ABCR */ 1259 __raw_writel(sh7724_rstandby_state.cs5bbcr, 0xfec10018); /* CS5BBCR */ 1260 __raw_writel(sh7724_rstandby_state.cs6abcr, 0xfec1001c); /* CS6ABCR */ 1261 __raw_writel(sh7724_rstandby_state.cs6bbcr, 0xfec10020); /* CS6BBCR */ 1262 __raw_writel(sh7724_rstandby_state.cs4wcr, 0xfec10030); /* CS4WCR */ 1263 __raw_writel(sh7724_rstandby_state.cs5awcr, 0xfec10034); /* CS5AWCR */ 1264 __raw_writel(sh7724_rstandby_state.cs5bwcr, 0xfec10038); /* CS5BWCR */ 1265 __raw_writel(sh7724_rstandby_state.cs6awcr, 0xfec1003c); /* CS6AWCR */ 1266 __raw_writel(sh7724_rstandby_state.cs6bwcr, 0xfec10040); /* CS6BWCR */ 1267 1268 /* INTC */ 1269 __raw_writew(sh7724_rstandby_state.ipra, 0xa4080000); /* IPRA */ 1270 __raw_writew(sh7724_rstandby_state.iprb, 0xa4080004); /* IPRB */ 1271 __raw_writew(sh7724_rstandby_state.iprc, 0xa4080008); /* IPRC */ 1272 __raw_writew(sh7724_rstandby_state.iprd, 0xa408000c); /* IPRD */ 1273 __raw_writew(sh7724_rstandby_state.ipre, 0xa4080010); /* IPRE */ 1274 __raw_writew(sh7724_rstandby_state.iprf, 0xa4080014); /* IPRF */ 1275 __raw_writew(sh7724_rstandby_state.iprg, 0xa4080018); /* IPRG */ 1276 __raw_writew(sh7724_rstandby_state.iprh, 0xa408001c); /* IPRH */ 1277 __raw_writew(sh7724_rstandby_state.ipri, 0xa4080020); /* IPRI */ 1278 __raw_writew(sh7724_rstandby_state.iprj, 0xa4080024); /* IPRJ */ 1279 __raw_writew(sh7724_rstandby_state.iprk, 0xa4080028); /* IPRK */ 1280 __raw_writew(sh7724_rstandby_state.iprl, 0xa408002c); /* IPRL */ 1281 __raw_writeb(sh7724_rstandby_state.imr0, 0xa4080080); /* IMR0 */ 1282 __raw_writeb(sh7724_rstandby_state.imr1, 0xa4080084); /* IMR1 */ 1283 __raw_writeb(sh7724_rstandby_state.imr2, 0xa4080088); /* IMR2 */ 1284 __raw_writeb(sh7724_rstandby_state.imr3, 0xa408008c); /* IMR3 */ 1285 __raw_writeb(sh7724_rstandby_state.imr4, 0xa4080090); /* IMR4 */ 1286 __raw_writeb(sh7724_rstandby_state.imr5, 0xa4080094); /* IMR5 */ 1287 __raw_writeb(sh7724_rstandby_state.imr6, 0xa4080098); /* IMR6 */ 1288 __raw_writeb(sh7724_rstandby_state.imr7, 0xa408009c); /* IMR7 */ 1289 __raw_writeb(sh7724_rstandby_state.imr8, 0xa40800a0); /* IMR8 */ 1290 __raw_writeb(sh7724_rstandby_state.imr9, 0xa40800a4); /* IMR9 */ 1291 __raw_writeb(sh7724_rstandby_state.imr10, 0xa40800a8); /* IMR10 */ 1292 __raw_writeb(sh7724_rstandby_state.imr11, 0xa40800ac); /* IMR11 */ 1293 __raw_writeb(sh7724_rstandby_state.imr12, 0xa40800b0); /* IMR12 */ 1294 1295 /* RWDT */ 1296 __raw_writew(sh7724_rstandby_state.rwtcnt, 0xa4520000); /* RWTCNT */ 1297 __raw_writew(sh7724_rstandby_state.rwtcsr, 0xa4520004); /* RWTCSR */ 1298 1299 /* CPG */ 1300 __raw_writel(sh7724_rstandby_state.irdaclk, 0xa4150018); /* IRDACLKCR */ 1301 __raw_writel(sh7724_rstandby_state.spuclk, 0xa415003c); /* SPUCLKCR */ 1302 1303 return NOTIFY_DONE; 1304 } 1305 1306 static struct notifier_block sh7724_pre_sleep_notifier = { 1307 .notifier_call = sh7724_pre_sleep_notifier_call, 1308 .priority = SH_MOBILE_PRE(SH_MOBILE_SLEEP_CPU), 1309 }; 1310 1311 static struct notifier_block sh7724_post_sleep_notifier = { 1312 .notifier_call = sh7724_post_sleep_notifier_call, 1313 .priority = SH_MOBILE_POST(SH_MOBILE_SLEEP_CPU), 1314 }; 1315 1316 static int __init sh7724_sleep_setup(void) 1317 { 1318 atomic_notifier_chain_register(&sh_mobile_pre_sleep_notifier_list, 1319 &sh7724_pre_sleep_notifier); 1320 1321 atomic_notifier_chain_register(&sh_mobile_post_sleep_notifier_list, 1322 &sh7724_post_sleep_notifier); 1323 return 0; 1324 } 1325 arch_initcall(sh7724_sleep_setup); 1326 1327