1 /* 2 * SH7724 Setup 3 * 4 * Copyright (C) 2009 Renesas Solutions Corp. 5 * 6 * Kuninori Morimoto <morimoto.kuninori@renesas.com> 7 * 8 * Based on SH7723 Setup 9 * Copyright (C) 2008 Paul Mundt 10 * 11 * This file is subject to the terms and conditions of the GNU General Public 12 * License. See the file "COPYING" in the main directory of this archive 13 * for more details. 14 */ 15 #include <linux/platform_device.h> 16 #include <linux/init.h> 17 #include <linux/serial.h> 18 #include <linux/mm.h> 19 #include <linux/serial_sci.h> 20 #include <linux/uio_driver.h> 21 #include <linux/sh_timer.h> 22 #include <linux/io.h> 23 #include <asm/clock.h> 24 #include <asm/mmzone.h> 25 #include <cpu/sh7724.h> 26 27 /* Serial */ 28 static struct plat_sci_port sci_platform_data[] = { 29 { 30 .mapbase = 0xffe00000, 31 .flags = UPF_BOOT_AUTOCONF, 32 .type = PORT_SCIF, 33 .irqs = { 80, 80, 80, 80 }, 34 .clk = "scif0", 35 }, { 36 .mapbase = 0xffe10000, 37 .flags = UPF_BOOT_AUTOCONF, 38 .type = PORT_SCIF, 39 .irqs = { 81, 81, 81, 81 }, 40 .clk = "scif1", 41 }, { 42 .mapbase = 0xffe20000, 43 .flags = UPF_BOOT_AUTOCONF, 44 .type = PORT_SCIF, 45 .irqs = { 82, 82, 82, 82 }, 46 .clk = "scif2", 47 }, { 48 .mapbase = 0xa4e30000, 49 .flags = UPF_BOOT_AUTOCONF, 50 .type = PORT_SCIFA, 51 .irqs = { 56, 56, 56, 56 }, 52 .clk = "scif3", 53 }, { 54 .mapbase = 0xa4e40000, 55 .flags = UPF_BOOT_AUTOCONF, 56 .type = PORT_SCIFA, 57 .irqs = { 88, 88, 88, 88 }, 58 .clk = "scif4", 59 }, { 60 .mapbase = 0xa4e50000, 61 .flags = UPF_BOOT_AUTOCONF, 62 .type = PORT_SCIFA, 63 .irqs = { 109, 109, 109, 109 }, 64 .clk = "scif5", 65 }, { 66 .flags = 0, 67 } 68 }; 69 70 static struct platform_device sci_device = { 71 .name = "sh-sci", 72 .id = -1, 73 .dev = { 74 .platform_data = sci_platform_data, 75 }, 76 }; 77 78 /* RTC */ 79 static struct resource rtc_resources[] = { 80 [0] = { 81 .start = 0xa465fec0, 82 .end = 0xa465fec0 + 0x58 - 1, 83 .flags = IORESOURCE_IO, 84 }, 85 [1] = { 86 /* Period IRQ */ 87 .start = 69, 88 .flags = IORESOURCE_IRQ, 89 }, 90 [2] = { 91 /* Carry IRQ */ 92 .start = 70, 93 .flags = IORESOURCE_IRQ, 94 }, 95 [3] = { 96 /* Alarm IRQ */ 97 .start = 68, 98 .flags = IORESOURCE_IRQ, 99 }, 100 }; 101 102 static struct platform_device rtc_device = { 103 .name = "sh-rtc", 104 .id = -1, 105 .num_resources = ARRAY_SIZE(rtc_resources), 106 .resource = rtc_resources, 107 .archdata = { 108 .hwblk_id = HWBLK_RTC, 109 }, 110 }; 111 112 /* I2C0 */ 113 static struct resource iic0_resources[] = { 114 [0] = { 115 .name = "IIC0", 116 .start = 0x04470000, 117 .end = 0x04470018 - 1, 118 .flags = IORESOURCE_MEM, 119 }, 120 [1] = { 121 .start = 96, 122 .end = 99, 123 .flags = IORESOURCE_IRQ, 124 }, 125 }; 126 127 static struct platform_device iic0_device = { 128 .name = "i2c-sh_mobile", 129 .id = 0, /* "i2c0" clock */ 130 .num_resources = ARRAY_SIZE(iic0_resources), 131 .resource = iic0_resources, 132 .archdata = { 133 .hwblk_id = HWBLK_IIC0, 134 }, 135 }; 136 137 /* I2C1 */ 138 static struct resource iic1_resources[] = { 139 [0] = { 140 .name = "IIC1", 141 .start = 0x04750000, 142 .end = 0x04750018 - 1, 143 .flags = IORESOURCE_MEM, 144 }, 145 [1] = { 146 .start = 92, 147 .end = 95, 148 .flags = IORESOURCE_IRQ, 149 }, 150 }; 151 152 static struct platform_device iic1_device = { 153 .name = "i2c-sh_mobile", 154 .id = 1, /* "i2c1" clock */ 155 .num_resources = ARRAY_SIZE(iic1_resources), 156 .resource = iic1_resources, 157 .archdata = { 158 .hwblk_id = HWBLK_IIC1, 159 }, 160 }; 161 162 /* VPU */ 163 static struct uio_info vpu_platform_data = { 164 .name = "VPU5F", 165 .version = "0", 166 .irq = 60, 167 }; 168 169 static struct resource vpu_resources[] = { 170 [0] = { 171 .name = "VPU", 172 .start = 0xfe900000, 173 .end = 0xfe902807, 174 .flags = IORESOURCE_MEM, 175 }, 176 [1] = { 177 /* place holder for contiguous memory */ 178 }, 179 }; 180 181 static struct platform_device vpu_device = { 182 .name = "uio_pdrv_genirq", 183 .id = 0, 184 .dev = { 185 .platform_data = &vpu_platform_data, 186 }, 187 .resource = vpu_resources, 188 .num_resources = ARRAY_SIZE(vpu_resources), 189 .archdata = { 190 .hwblk_id = HWBLK_VPU, 191 }, 192 }; 193 194 /* VEU0 */ 195 static struct uio_info veu0_platform_data = { 196 .name = "VEU3F0", 197 .version = "0", 198 .irq = 83, 199 }; 200 201 static struct resource veu0_resources[] = { 202 [0] = { 203 .name = "VEU3F0", 204 .start = 0xfe920000, 205 .end = 0xfe9200cb - 1, 206 .flags = IORESOURCE_MEM, 207 }, 208 [1] = { 209 /* place holder for contiguous memory */ 210 }, 211 }; 212 213 static struct platform_device veu0_device = { 214 .name = "uio_pdrv_genirq", 215 .id = 1, 216 .dev = { 217 .platform_data = &veu0_platform_data, 218 }, 219 .resource = veu0_resources, 220 .num_resources = ARRAY_SIZE(veu0_resources), 221 .archdata = { 222 .hwblk_id = HWBLK_VEU0, 223 }, 224 }; 225 226 /* VEU1 */ 227 static struct uio_info veu1_platform_data = { 228 .name = "VEU3F1", 229 .version = "0", 230 .irq = 54, 231 }; 232 233 static struct resource veu1_resources[] = { 234 [0] = { 235 .name = "VEU3F1", 236 .start = 0xfe924000, 237 .end = 0xfe9240cb - 1, 238 .flags = IORESOURCE_MEM, 239 }, 240 [1] = { 241 /* place holder for contiguous memory */ 242 }, 243 }; 244 245 static struct platform_device veu1_device = { 246 .name = "uio_pdrv_genirq", 247 .id = 2, 248 .dev = { 249 .platform_data = &veu1_platform_data, 250 }, 251 .resource = veu1_resources, 252 .num_resources = ARRAY_SIZE(veu1_resources), 253 .archdata = { 254 .hwblk_id = HWBLK_VEU1, 255 }, 256 }; 257 258 static struct sh_timer_config cmt_platform_data = { 259 .name = "CMT", 260 .channel_offset = 0x60, 261 .timer_bit = 5, 262 .clk = "cmt0", 263 .clockevent_rating = 125, 264 .clocksource_rating = 200, 265 }; 266 267 static struct resource cmt_resources[] = { 268 [0] = { 269 .name = "CMT", 270 .start = 0x044a0060, 271 .end = 0x044a006b, 272 .flags = IORESOURCE_MEM, 273 }, 274 [1] = { 275 .start = 104, 276 .flags = IORESOURCE_IRQ, 277 }, 278 }; 279 280 static struct platform_device cmt_device = { 281 .name = "sh_cmt", 282 .id = 0, 283 .dev = { 284 .platform_data = &cmt_platform_data, 285 }, 286 .resource = cmt_resources, 287 .num_resources = ARRAY_SIZE(cmt_resources), 288 .archdata = { 289 .hwblk_id = HWBLK_CMT, 290 }, 291 }; 292 293 static struct sh_timer_config tmu0_platform_data = { 294 .name = "TMU0", 295 .channel_offset = 0x04, 296 .timer_bit = 0, 297 .clk = "tmu0", 298 .clockevent_rating = 200, 299 }; 300 301 static struct resource tmu0_resources[] = { 302 [0] = { 303 .name = "TMU0", 304 .start = 0xffd80008, 305 .end = 0xffd80013, 306 .flags = IORESOURCE_MEM, 307 }, 308 [1] = { 309 .start = 16, 310 .flags = IORESOURCE_IRQ, 311 }, 312 }; 313 314 static struct platform_device tmu0_device = { 315 .name = "sh_tmu", 316 .id = 0, 317 .dev = { 318 .platform_data = &tmu0_platform_data, 319 }, 320 .resource = tmu0_resources, 321 .num_resources = ARRAY_SIZE(tmu0_resources), 322 .archdata = { 323 .hwblk_id = HWBLK_TMU0, 324 }, 325 }; 326 327 static struct sh_timer_config tmu1_platform_data = { 328 .name = "TMU1", 329 .channel_offset = 0x10, 330 .timer_bit = 1, 331 .clk = "tmu0", 332 .clocksource_rating = 200, 333 }; 334 335 static struct resource tmu1_resources[] = { 336 [0] = { 337 .name = "TMU1", 338 .start = 0xffd80014, 339 .end = 0xffd8001f, 340 .flags = IORESOURCE_MEM, 341 }, 342 [1] = { 343 .start = 17, 344 .flags = IORESOURCE_IRQ, 345 }, 346 }; 347 348 static struct platform_device tmu1_device = { 349 .name = "sh_tmu", 350 .id = 1, 351 .dev = { 352 .platform_data = &tmu1_platform_data, 353 }, 354 .resource = tmu1_resources, 355 .num_resources = ARRAY_SIZE(tmu1_resources), 356 .archdata = { 357 .hwblk_id = HWBLK_TMU0, 358 }, 359 }; 360 361 static struct sh_timer_config tmu2_platform_data = { 362 .name = "TMU2", 363 .channel_offset = 0x1c, 364 .timer_bit = 2, 365 .clk = "tmu0", 366 }; 367 368 static struct resource tmu2_resources[] = { 369 [0] = { 370 .name = "TMU2", 371 .start = 0xffd80020, 372 .end = 0xffd8002b, 373 .flags = IORESOURCE_MEM, 374 }, 375 [1] = { 376 .start = 18, 377 .flags = IORESOURCE_IRQ, 378 }, 379 }; 380 381 static struct platform_device tmu2_device = { 382 .name = "sh_tmu", 383 .id = 2, 384 .dev = { 385 .platform_data = &tmu2_platform_data, 386 }, 387 .resource = tmu2_resources, 388 .num_resources = ARRAY_SIZE(tmu2_resources), 389 .archdata = { 390 .hwblk_id = HWBLK_TMU0, 391 }, 392 }; 393 394 395 static struct sh_timer_config tmu3_platform_data = { 396 .name = "TMU3", 397 .channel_offset = 0x04, 398 .timer_bit = 0, 399 .clk = "tmu1", 400 }; 401 402 static struct resource tmu3_resources[] = { 403 [0] = { 404 .name = "TMU3", 405 .start = 0xffd90008, 406 .end = 0xffd90013, 407 .flags = IORESOURCE_MEM, 408 }, 409 [1] = { 410 .start = 57, 411 .flags = IORESOURCE_IRQ, 412 }, 413 }; 414 415 static struct platform_device tmu3_device = { 416 .name = "sh_tmu", 417 .id = 3, 418 .dev = { 419 .platform_data = &tmu3_platform_data, 420 }, 421 .resource = tmu3_resources, 422 .num_resources = ARRAY_SIZE(tmu3_resources), 423 .archdata = { 424 .hwblk_id = HWBLK_TMU1, 425 }, 426 }; 427 428 static struct sh_timer_config tmu4_platform_data = { 429 .name = "TMU4", 430 .channel_offset = 0x10, 431 .timer_bit = 1, 432 .clk = "tmu1", 433 }; 434 435 static struct resource tmu4_resources[] = { 436 [0] = { 437 .name = "TMU4", 438 .start = 0xffd90014, 439 .end = 0xffd9001f, 440 .flags = IORESOURCE_MEM, 441 }, 442 [1] = { 443 .start = 58, 444 .flags = IORESOURCE_IRQ, 445 }, 446 }; 447 448 static struct platform_device tmu4_device = { 449 .name = "sh_tmu", 450 .id = 4, 451 .dev = { 452 .platform_data = &tmu4_platform_data, 453 }, 454 .resource = tmu4_resources, 455 .num_resources = ARRAY_SIZE(tmu4_resources), 456 .archdata = { 457 .hwblk_id = HWBLK_TMU1, 458 }, 459 }; 460 461 static struct sh_timer_config tmu5_platform_data = { 462 .name = "TMU5", 463 .channel_offset = 0x1c, 464 .timer_bit = 2, 465 .clk = "tmu1", 466 }; 467 468 static struct resource tmu5_resources[] = { 469 [0] = { 470 .name = "TMU5", 471 .start = 0xffd90020, 472 .end = 0xffd9002b, 473 .flags = IORESOURCE_MEM, 474 }, 475 [1] = { 476 .start = 57, 477 .flags = IORESOURCE_IRQ, 478 }, 479 }; 480 481 static struct platform_device tmu5_device = { 482 .name = "sh_tmu", 483 .id = 5, 484 .dev = { 485 .platform_data = &tmu5_platform_data, 486 }, 487 .resource = tmu5_resources, 488 .num_resources = ARRAY_SIZE(tmu5_resources), 489 .archdata = { 490 .hwblk_id = HWBLK_TMU1, 491 }, 492 }; 493 494 /* JPU */ 495 static struct uio_info jpu_platform_data = { 496 .name = "JPU", 497 .version = "0", 498 .irq = 27, 499 }; 500 501 static struct resource jpu_resources[] = { 502 [0] = { 503 .name = "JPU", 504 .start = 0xfe980000, 505 .end = 0xfe9902d3, 506 .flags = IORESOURCE_MEM, 507 }, 508 [1] = { 509 /* place holder for contiguous memory */ 510 }, 511 }; 512 513 static struct platform_device jpu_device = { 514 .name = "uio_pdrv_genirq", 515 .id = 3, 516 .dev = { 517 .platform_data = &jpu_platform_data, 518 }, 519 .resource = jpu_resources, 520 .num_resources = ARRAY_SIZE(jpu_resources), 521 .archdata = { 522 .hwblk_id = HWBLK_JPU, 523 }, 524 }; 525 526 static struct platform_device *sh7724_devices[] __initdata = { 527 &cmt_device, 528 &tmu0_device, 529 &tmu1_device, 530 &tmu2_device, 531 &tmu3_device, 532 &tmu4_device, 533 &tmu5_device, 534 &sci_device, 535 &rtc_device, 536 &iic0_device, 537 &iic1_device, 538 &vpu_device, 539 &veu0_device, 540 &veu1_device, 541 &jpu_device, 542 }; 543 544 static int __init sh7724_devices_setup(void) 545 { 546 platform_resource_setup_memory(&vpu_device, "vpu", 2 << 20); 547 platform_resource_setup_memory(&veu0_device, "veu0", 2 << 20); 548 platform_resource_setup_memory(&veu1_device, "veu1", 2 << 20); 549 platform_resource_setup_memory(&jpu_device, "jpu", 2 << 20); 550 551 return platform_add_devices(sh7724_devices, 552 ARRAY_SIZE(sh7724_devices)); 553 } 554 arch_initcall(sh7724_devices_setup); 555 556 static struct platform_device *sh7724_early_devices[] __initdata = { 557 &cmt_device, 558 &tmu0_device, 559 &tmu1_device, 560 &tmu2_device, 561 &tmu3_device, 562 &tmu4_device, 563 &tmu5_device, 564 }; 565 566 void __init plat_early_device_setup(void) 567 { 568 early_platform_add_devices(sh7724_early_devices, 569 ARRAY_SIZE(sh7724_early_devices)); 570 } 571 572 #define RAMCR_CACHE_L2FC 0x0002 573 #define RAMCR_CACHE_L2E 0x0001 574 #define L2_CACHE_ENABLE (RAMCR_CACHE_L2E|RAMCR_CACHE_L2FC) 575 void __uses_jump_to_uncached l2_cache_init(void) 576 { 577 /* Enable L2 cache */ 578 ctrl_outl(L2_CACHE_ENABLE, RAMCR); 579 } 580 581 enum { 582 UNUSED = 0, 583 584 /* interrupt sources */ 585 IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7, 586 HUDI, 587 DMAC1A_DEI0, DMAC1A_DEI1, DMAC1A_DEI2, DMAC1A_DEI3, 588 _2DG_TRI, _2DG_INI, _2DG_CEI, 589 DMAC0A_DEI0, DMAC0A_DEI1, DMAC0A_DEI2, DMAC0A_DEI3, 590 VIO_CEU0, VIO_BEU0, VIO_VEU1, VIO_VOU, 591 SCIFA3, 592 VPU, 593 TPU, 594 CEU1, 595 BEU1, 596 USB0, USB1, 597 ATAPI, 598 RTC_ATI, RTC_PRI, RTC_CUI, 599 DMAC1B_DEI4, DMAC1B_DEI5, DMAC1B_DADERR, 600 DMAC0B_DEI4, DMAC0B_DEI5, DMAC0B_DADERR, 601 KEYSC, 602 SCIF_SCIF0, SCIF_SCIF1, SCIF_SCIF2, 603 VEU0, 604 MSIOF_MSIOFI0, MSIOF_MSIOFI1, 605 SPU_SPUI0, SPU_SPUI1, 606 SCIFA4, 607 ICB, 608 ETHI, 609 I2C1_ALI, I2C1_TACKI, I2C1_WAITI, I2C1_DTEI, 610 I2C0_ALI, I2C0_TACKI, I2C0_WAITI, I2C0_DTEI, 611 SDHI0_SDHII0, SDHI0_SDHII1, SDHI0_SDHII2, SDHI0_SDHII3, 612 CMT, 613 TSIF, 614 FSI, 615 SCIFA5, 616 TMU0_TUNI0, TMU0_TUNI1, TMU0_TUNI2, 617 IRDA, 618 SDHI1_SDHII0, SDHI1_SDHII1, SDHI1_SDHII2, 619 JPU, 620 _2DDMAC, 621 MMC_MMC2I, MMC_MMC3I, 622 LCDC, 623 TMU1_TUNI0, TMU1_TUNI1, TMU1_TUNI2, 624 625 /* interrupt groups */ 626 DMAC1A, _2DG, DMAC0A, VIO, USB, RTC, 627 DMAC1B, DMAC0B, I2C0, I2C1, SDHI0, SDHI1, SPU, MMCIF, 628 }; 629 630 static struct intc_vect vectors[] __initdata = { 631 INTC_VECT(IRQ0, 0x600), INTC_VECT(IRQ1, 0x620), 632 INTC_VECT(IRQ2, 0x640), INTC_VECT(IRQ3, 0x660), 633 INTC_VECT(IRQ4, 0x680), INTC_VECT(IRQ5, 0x6a0), 634 INTC_VECT(IRQ6, 0x6c0), INTC_VECT(IRQ7, 0x6e0), 635 636 INTC_VECT(DMAC1A_DEI0, 0x700), 637 INTC_VECT(DMAC1A_DEI1, 0x720), 638 INTC_VECT(DMAC1A_DEI2, 0x740), 639 INTC_VECT(DMAC1A_DEI3, 0x760), 640 641 INTC_VECT(_2DG_TRI, 0x780), 642 INTC_VECT(_2DG_INI, 0x7A0), 643 INTC_VECT(_2DG_CEI, 0x7C0), 644 645 INTC_VECT(DMAC0A_DEI0, 0x800), 646 INTC_VECT(DMAC0A_DEI1, 0x820), 647 INTC_VECT(DMAC0A_DEI2, 0x840), 648 INTC_VECT(DMAC0A_DEI3, 0x860), 649 650 INTC_VECT(VIO_CEU0, 0x880), 651 INTC_VECT(VIO_BEU0, 0x8A0), 652 INTC_VECT(VIO_VEU1, 0x8C0), 653 INTC_VECT(VIO_VOU, 0x8E0), 654 655 INTC_VECT(SCIFA3, 0x900), 656 INTC_VECT(VPU, 0x980), 657 INTC_VECT(TPU, 0x9A0), 658 INTC_VECT(CEU1, 0x9E0), 659 INTC_VECT(BEU1, 0xA00), 660 INTC_VECT(USB0, 0xA20), 661 INTC_VECT(USB1, 0xA40), 662 INTC_VECT(ATAPI, 0xA60), 663 664 INTC_VECT(RTC_ATI, 0xA80), 665 INTC_VECT(RTC_PRI, 0xAA0), 666 INTC_VECT(RTC_CUI, 0xAC0), 667 668 INTC_VECT(DMAC1B_DEI4, 0xB00), 669 INTC_VECT(DMAC1B_DEI5, 0xB20), 670 INTC_VECT(DMAC1B_DADERR, 0xB40), 671 672 INTC_VECT(DMAC0B_DEI4, 0xB80), 673 INTC_VECT(DMAC0B_DEI5, 0xBA0), 674 INTC_VECT(DMAC0B_DADERR, 0xBC0), 675 676 INTC_VECT(KEYSC, 0xBE0), 677 INTC_VECT(SCIF_SCIF0, 0xC00), 678 INTC_VECT(SCIF_SCIF1, 0xC20), 679 INTC_VECT(SCIF_SCIF2, 0xC40), 680 INTC_VECT(VEU0, 0xC60), 681 INTC_VECT(MSIOF_MSIOFI0, 0xC80), 682 INTC_VECT(MSIOF_MSIOFI1, 0xCA0), 683 INTC_VECT(SPU_SPUI0, 0xCC0), 684 INTC_VECT(SPU_SPUI1, 0xCE0), 685 INTC_VECT(SCIFA4, 0xD00), 686 687 INTC_VECT(ICB, 0xD20), 688 INTC_VECT(ETHI, 0xD60), 689 690 INTC_VECT(I2C1_ALI, 0xD80), 691 INTC_VECT(I2C1_TACKI, 0xDA0), 692 INTC_VECT(I2C1_WAITI, 0xDC0), 693 INTC_VECT(I2C1_DTEI, 0xDE0), 694 695 INTC_VECT(I2C0_ALI, 0xE00), 696 INTC_VECT(I2C0_TACKI, 0xE20), 697 INTC_VECT(I2C0_WAITI, 0xE40), 698 INTC_VECT(I2C0_DTEI, 0xE60), 699 700 INTC_VECT(SDHI0_SDHII0, 0xE80), 701 INTC_VECT(SDHI0_SDHII1, 0xEA0), 702 INTC_VECT(SDHI0_SDHII2, 0xEC0), 703 INTC_VECT(SDHI0_SDHII3, 0xEE0), 704 705 INTC_VECT(CMT, 0xF00), 706 INTC_VECT(TSIF, 0xF20), 707 INTC_VECT(FSI, 0xF80), 708 INTC_VECT(SCIFA5, 0xFA0), 709 710 INTC_VECT(TMU0_TUNI0, 0x400), 711 INTC_VECT(TMU0_TUNI1, 0x420), 712 INTC_VECT(TMU0_TUNI2, 0x440), 713 714 INTC_VECT(IRDA, 0x480), 715 716 INTC_VECT(SDHI1_SDHII0, 0x4E0), 717 INTC_VECT(SDHI1_SDHII1, 0x500), 718 INTC_VECT(SDHI1_SDHII2, 0x520), 719 720 INTC_VECT(JPU, 0x560), 721 INTC_VECT(_2DDMAC, 0x4A0), 722 723 INTC_VECT(MMC_MMC2I, 0x5A0), 724 INTC_VECT(MMC_MMC3I, 0x5C0), 725 726 INTC_VECT(LCDC, 0xF40), 727 728 INTC_VECT(TMU1_TUNI0, 0x920), 729 INTC_VECT(TMU1_TUNI1, 0x940), 730 INTC_VECT(TMU1_TUNI2, 0x960), 731 }; 732 733 static struct intc_group groups[] __initdata = { 734 INTC_GROUP(DMAC1A, DMAC1A_DEI0, DMAC1A_DEI1, DMAC1A_DEI2, DMAC1A_DEI3), 735 INTC_GROUP(_2DG, _2DG_TRI, _2DG_INI, _2DG_CEI), 736 INTC_GROUP(DMAC0A, DMAC0A_DEI0, DMAC0A_DEI1, DMAC0A_DEI2, DMAC0A_DEI3), 737 INTC_GROUP(VIO, VIO_CEU0, VIO_BEU0, VIO_VEU1, VIO_VOU), 738 INTC_GROUP(USB, USB0, USB1), 739 INTC_GROUP(RTC, RTC_ATI, RTC_PRI, RTC_CUI), 740 INTC_GROUP(DMAC1B, DMAC1B_DEI4, DMAC1B_DEI5, DMAC1B_DADERR), 741 INTC_GROUP(DMAC0B, DMAC0B_DEI4, DMAC0B_DEI5, DMAC0B_DADERR), 742 INTC_GROUP(I2C0, I2C0_ALI, I2C0_TACKI, I2C0_WAITI, I2C0_DTEI), 743 INTC_GROUP(I2C1, I2C1_ALI, I2C1_TACKI, I2C1_WAITI, I2C1_DTEI), 744 INTC_GROUP(SDHI0, SDHI0_SDHII0, SDHI0_SDHII1, SDHI0_SDHII2, SDHI0_SDHII3), 745 INTC_GROUP(SDHI1, SDHI1_SDHII0, SDHI1_SDHII1, SDHI1_SDHII2), 746 INTC_GROUP(SPU, SPU_SPUI0, SPU_SPUI1), 747 INTC_GROUP(MMCIF, MMC_MMC2I, MMC_MMC3I), 748 }; 749 750 static struct intc_mask_reg mask_registers[] __initdata = { 751 { 0xa4080080, 0xa40800c0, 8, /* IMR0 / IMCR0 */ 752 { 0, TMU1_TUNI2, TMU1_TUNI1, TMU1_TUNI0, 753 0, SDHI1_SDHII2, SDHI1_SDHII1, SDHI1_SDHII0 } }, 754 { 0xa4080084, 0xa40800c4, 8, /* IMR1 / IMCR1 */ 755 { VIO_VOU, VIO_VEU1, VIO_BEU0, VIO_CEU0, 756 DMAC0A_DEI3, DMAC0A_DEI2, DMAC0A_DEI1, DMAC0A_DEI0 } }, 757 { 0xa4080088, 0xa40800c8, 8, /* IMR2 / IMCR2 */ 758 { 0, 0, 0, VPU, ATAPI, ETHI, 0, SCIFA3 } }, 759 { 0xa408008c, 0xa40800cc, 8, /* IMR3 / IMCR3 */ 760 { DMAC1A_DEI3, DMAC1A_DEI2, DMAC1A_DEI1, DMAC1A_DEI0, 761 SPU_SPUI1, SPU_SPUI0, BEU1, IRDA } }, 762 { 0xa4080090, 0xa40800d0, 8, /* IMR4 / IMCR4 */ 763 { 0, TMU0_TUNI2, TMU0_TUNI1, TMU0_TUNI0, 764 JPU, 0, 0, LCDC } }, 765 { 0xa4080094, 0xa40800d4, 8, /* IMR5 / IMCR5 */ 766 { KEYSC, DMAC0B_DADERR, DMAC0B_DEI5, DMAC0B_DEI4, 767 VEU0, SCIF_SCIF2, SCIF_SCIF1, SCIF_SCIF0 } }, 768 { 0xa4080098, 0xa40800d8, 8, /* IMR6 / IMCR6 */ 769 { 0, 0, ICB, SCIFA4, 770 CEU1, 0, MSIOF_MSIOFI1, MSIOF_MSIOFI0 } }, 771 { 0xa408009c, 0xa40800dc, 8, /* IMR7 / IMCR7 */ 772 { I2C0_DTEI, I2C0_WAITI, I2C0_TACKI, I2C0_ALI, 773 I2C1_DTEI, I2C1_WAITI, I2C1_TACKI, I2C1_ALI } }, 774 { 0xa40800a0, 0xa40800e0, 8, /* IMR8 / IMCR8 */ 775 { SDHI0_SDHII3, SDHI0_SDHII2, SDHI0_SDHII1, SDHI0_SDHII0, 776 0, 0, SCIFA5, FSI } }, 777 { 0xa40800a4, 0xa40800e4, 8, /* IMR9 / IMCR9 */ 778 { 0, 0, 0, CMT, 0, USB1, USB0, 0 } }, 779 { 0xa40800a8, 0xa40800e8, 8, /* IMR10 / IMCR10 */ 780 { 0, DMAC1B_DADERR, DMAC1B_DEI5, DMAC1B_DEI4, 781 0, RTC_CUI, RTC_PRI, RTC_ATI } }, 782 { 0xa40800ac, 0xa40800ec, 8, /* IMR11 / IMCR11 */ 783 { 0, _2DG_CEI, _2DG_INI, _2DG_TRI, 784 0, TPU, 0, TSIF } }, 785 { 0xa40800b0, 0xa40800f0, 8, /* IMR12 / IMCR12 */ 786 { 0, 0, MMC_MMC3I, MMC_MMC2I, 0, 0, 0, _2DDMAC } }, 787 { 0xa4140044, 0xa4140064, 8, /* INTMSK00 / INTMSKCLR00 */ 788 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } }, 789 }; 790 791 static struct intc_prio_reg prio_registers[] __initdata = { 792 { 0xa4080000, 0, 16, 4, /* IPRA */ { TMU0_TUNI0, TMU0_TUNI1, 793 TMU0_TUNI2, IRDA } }, 794 { 0xa4080004, 0, 16, 4, /* IPRB */ { JPU, LCDC, DMAC1A, BEU1 } }, 795 { 0xa4080008, 0, 16, 4, /* IPRC */ { TMU1_TUNI0, TMU1_TUNI1, 796 TMU1_TUNI2, SPU } }, 797 { 0xa408000c, 0, 16, 4, /* IPRD */ { 0, MMCIF, 0, ATAPI } }, 798 { 0xa4080010, 0, 16, 4, /* IPRE */ { DMAC0A, VIO, SCIFA3, VPU } }, 799 { 0xa4080014, 0, 16, 4, /* IPRF */ { KEYSC, DMAC0B, USB, CMT } }, 800 { 0xa4080018, 0, 16, 4, /* IPRG */ { SCIF_SCIF0, SCIF_SCIF1, 801 SCIF_SCIF2, VEU0 } }, 802 { 0xa408001c, 0, 16, 4, /* IPRH */ { MSIOF_MSIOFI0, MSIOF_MSIOFI1, 803 I2C1, I2C0 } }, 804 { 0xa4080020, 0, 16, 4, /* IPRI */ { SCIFA4, ICB, TSIF, _2DG } }, 805 { 0xa4080024, 0, 16, 4, /* IPRJ */ { CEU1, ETHI, FSI, SDHI1 } }, 806 { 0xa4080028, 0, 16, 4, /* IPRK */ { RTC, DMAC1B, 0, SDHI0 } }, 807 { 0xa408002c, 0, 16, 4, /* IPRL */ { SCIFA5, 0, TPU, _2DDMAC } }, 808 { 0xa4140010, 0, 32, 4, /* INTPRI00 */ 809 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } }, 810 }; 811 812 static struct intc_sense_reg sense_registers[] __initdata = { 813 { 0xa414001c, 16, 2, /* ICR1 */ 814 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } }, 815 }; 816 817 static struct intc_mask_reg ack_registers[] __initdata = { 818 { 0xa4140024, 0, 8, /* INTREQ00 */ 819 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } }, 820 }; 821 822 static DECLARE_INTC_DESC_ACK(intc_desc, "sh7724", vectors, groups, 823 mask_registers, prio_registers, sense_registers, 824 ack_registers); 825 826 void __init plat_irq_setup(void) 827 { 828 register_intc_controller(&intc_desc); 829 } 830