1 /* 2 * SH7723 Setup 3 * 4 * Copyright (C) 2008 Paul Mundt 5 * 6 * This file is subject to the terms and conditions of the GNU General Public 7 * License. See the file "COPYING" in the main directory of this archive 8 * for more details. 9 */ 10 #include <linux/platform_device.h> 11 #include <linux/init.h> 12 #include <linux/serial.h> 13 #include <linux/mm.h> 14 #include <linux/serial_sci.h> 15 #include <linux/uio_driver.h> 16 #include <linux/usb/r8a66597.h> 17 #include <linux/sh_timer.h> 18 #include <linux/io.h> 19 #include <asm/clock.h> 20 #include <asm/mmzone.h> 21 22 static struct uio_info vpu_platform_data = { 23 .name = "VPU5", 24 .version = "0", 25 .irq = 60, 26 }; 27 28 static struct resource vpu_resources[] = { 29 [0] = { 30 .name = "VPU", 31 .start = 0xfe900000, 32 .end = 0xfe902807, 33 .flags = IORESOURCE_MEM, 34 }, 35 [1] = { 36 /* place holder for contiguous memory */ 37 }, 38 }; 39 40 static struct platform_device vpu_device = { 41 .name = "uio_pdrv_genirq", 42 .id = 0, 43 .dev = { 44 .platform_data = &vpu_platform_data, 45 }, 46 .resource = vpu_resources, 47 .num_resources = ARRAY_SIZE(vpu_resources), 48 }; 49 50 static struct uio_info veu0_platform_data = { 51 .name = "VEU2H", 52 .version = "0", 53 .irq = 54, 54 }; 55 56 static struct resource veu0_resources[] = { 57 [0] = { 58 .name = "VEU2H0", 59 .start = 0xfe920000, 60 .end = 0xfe92027b, 61 .flags = IORESOURCE_MEM, 62 }, 63 [1] = { 64 /* place holder for contiguous memory */ 65 }, 66 }; 67 68 static struct platform_device veu0_device = { 69 .name = "uio_pdrv_genirq", 70 .id = 1, 71 .dev = { 72 .platform_data = &veu0_platform_data, 73 }, 74 .resource = veu0_resources, 75 .num_resources = ARRAY_SIZE(veu0_resources), 76 }; 77 78 static struct uio_info veu1_platform_data = { 79 .name = "VEU2H", 80 .version = "0", 81 .irq = 27, 82 }; 83 84 static struct resource veu1_resources[] = { 85 [0] = { 86 .name = "VEU2H1", 87 .start = 0xfe924000, 88 .end = 0xfe92427b, 89 .flags = IORESOURCE_MEM, 90 }, 91 [1] = { 92 /* place holder for contiguous memory */ 93 }, 94 }; 95 96 static struct platform_device veu1_device = { 97 .name = "uio_pdrv_genirq", 98 .id = 2, 99 .dev = { 100 .platform_data = &veu1_platform_data, 101 }, 102 .resource = veu1_resources, 103 .num_resources = ARRAY_SIZE(veu1_resources), 104 }; 105 106 static struct sh_timer_config cmt_platform_data = { 107 .name = "CMT", 108 .channel_offset = 0x60, 109 .timer_bit = 5, 110 .clk = "cmt0", 111 .clockevent_rating = 125, 112 .clocksource_rating = 125, 113 }; 114 115 static struct resource cmt_resources[] = { 116 [0] = { 117 .name = "CMT", 118 .start = 0x044a0060, 119 .end = 0x044a006b, 120 .flags = IORESOURCE_MEM, 121 }, 122 [1] = { 123 .start = 104, 124 .flags = IORESOURCE_IRQ, 125 }, 126 }; 127 128 static struct platform_device cmt_device = { 129 .name = "sh_cmt", 130 .id = 0, 131 .dev = { 132 .platform_data = &cmt_platform_data, 133 }, 134 .resource = cmt_resources, 135 .num_resources = ARRAY_SIZE(cmt_resources), 136 }; 137 138 static struct sh_timer_config tmu0_platform_data = { 139 .name = "TMU0", 140 .channel_offset = 0x04, 141 .timer_bit = 0, 142 .clk = "tmu0", 143 .clockevent_rating = 200, 144 }; 145 146 static struct resource tmu0_resources[] = { 147 [0] = { 148 .name = "TMU0", 149 .start = 0xffd80008, 150 .end = 0xffd80013, 151 .flags = IORESOURCE_MEM, 152 }, 153 [1] = { 154 .start = 16, 155 .flags = IORESOURCE_IRQ, 156 }, 157 }; 158 159 static struct platform_device tmu0_device = { 160 .name = "sh_tmu", 161 .id = 0, 162 .dev = { 163 .platform_data = &tmu0_platform_data, 164 }, 165 .resource = tmu0_resources, 166 .num_resources = ARRAY_SIZE(tmu0_resources), 167 }; 168 169 static struct sh_timer_config tmu1_platform_data = { 170 .name = "TMU1", 171 .channel_offset = 0x10, 172 .timer_bit = 1, 173 .clk = "tmu0", 174 .clocksource_rating = 200, 175 }; 176 177 static struct resource tmu1_resources[] = { 178 [0] = { 179 .name = "TMU1", 180 .start = 0xffd80014, 181 .end = 0xffd8001f, 182 .flags = IORESOURCE_MEM, 183 }, 184 [1] = { 185 .start = 17, 186 .flags = IORESOURCE_IRQ, 187 }, 188 }; 189 190 static struct platform_device tmu1_device = { 191 .name = "sh_tmu", 192 .id = 1, 193 .dev = { 194 .platform_data = &tmu1_platform_data, 195 }, 196 .resource = tmu1_resources, 197 .num_resources = ARRAY_SIZE(tmu1_resources), 198 }; 199 200 static struct sh_timer_config tmu2_platform_data = { 201 .name = "TMU2", 202 .channel_offset = 0x1c, 203 .timer_bit = 2, 204 .clk = "tmu0", 205 }; 206 207 static struct resource tmu2_resources[] = { 208 [0] = { 209 .name = "TMU2", 210 .start = 0xffd80020, 211 .end = 0xffd8002b, 212 .flags = IORESOURCE_MEM, 213 }, 214 [1] = { 215 .start = 18, 216 .flags = IORESOURCE_IRQ, 217 }, 218 }; 219 220 static struct platform_device tmu2_device = { 221 .name = "sh_tmu", 222 .id = 2, 223 .dev = { 224 .platform_data = &tmu2_platform_data, 225 }, 226 .resource = tmu2_resources, 227 .num_resources = ARRAY_SIZE(tmu2_resources), 228 }; 229 230 static struct sh_timer_config tmu3_platform_data = { 231 .name = "TMU3", 232 .channel_offset = 0x04, 233 .timer_bit = 0, 234 .clk = "tmu1", 235 }; 236 237 static struct resource tmu3_resources[] = { 238 [0] = { 239 .name = "TMU3", 240 .start = 0xffd90008, 241 .end = 0xffd90013, 242 .flags = IORESOURCE_MEM, 243 }, 244 [1] = { 245 .start = 57, 246 .flags = IORESOURCE_IRQ, 247 }, 248 }; 249 250 static struct platform_device tmu3_device = { 251 .name = "sh_tmu", 252 .id = 3, 253 .dev = { 254 .platform_data = &tmu3_platform_data, 255 }, 256 .resource = tmu3_resources, 257 .num_resources = ARRAY_SIZE(tmu3_resources), 258 }; 259 260 static struct sh_timer_config tmu4_platform_data = { 261 .name = "TMU4", 262 .channel_offset = 0x10, 263 .timer_bit = 1, 264 .clk = "tmu1", 265 }; 266 267 static struct resource tmu4_resources[] = { 268 [0] = { 269 .name = "TMU4", 270 .start = 0xffd90014, 271 .end = 0xffd9001f, 272 .flags = IORESOURCE_MEM, 273 }, 274 [1] = { 275 .start = 58, 276 .flags = IORESOURCE_IRQ, 277 }, 278 }; 279 280 static struct platform_device tmu4_device = { 281 .name = "sh_tmu", 282 .id = 4, 283 .dev = { 284 .platform_data = &tmu4_platform_data, 285 }, 286 .resource = tmu4_resources, 287 .num_resources = ARRAY_SIZE(tmu4_resources), 288 }; 289 290 static struct sh_timer_config tmu5_platform_data = { 291 .name = "TMU5", 292 .channel_offset = 0x1c, 293 .timer_bit = 2, 294 .clk = "tmu1", 295 }; 296 297 static struct resource tmu5_resources[] = { 298 [0] = { 299 .name = "TMU5", 300 .start = 0xffd90020, 301 .end = 0xffd9002b, 302 .flags = IORESOURCE_MEM, 303 }, 304 [1] = { 305 .start = 57, 306 .flags = IORESOURCE_IRQ, 307 }, 308 }; 309 310 static struct platform_device tmu5_device = { 311 .name = "sh_tmu", 312 .id = 5, 313 .dev = { 314 .platform_data = &tmu5_platform_data, 315 }, 316 .resource = tmu5_resources, 317 .num_resources = ARRAY_SIZE(tmu5_resources), 318 }; 319 320 static struct plat_sci_port sci_platform_data[] = { 321 { 322 .mapbase = 0xffe00000, 323 .flags = UPF_BOOT_AUTOCONF, 324 .type = PORT_SCIF, 325 .irqs = { 80, 80, 80, 80 }, 326 .clk = "scif0", 327 },{ 328 .mapbase = 0xffe10000, 329 .flags = UPF_BOOT_AUTOCONF, 330 .type = PORT_SCIF, 331 .irqs = { 81, 81, 81, 81 }, 332 .clk = "scif1", 333 },{ 334 .mapbase = 0xffe20000, 335 .flags = UPF_BOOT_AUTOCONF, 336 .type = PORT_SCIF, 337 .irqs = { 82, 82, 82, 82 }, 338 .clk = "scif2", 339 },{ 340 .mapbase = 0xa4e30000, 341 .flags = UPF_BOOT_AUTOCONF, 342 .type = PORT_SCIFA, 343 .irqs = { 56, 56, 56, 56 }, 344 .clk = "scif3", 345 },{ 346 .mapbase = 0xa4e40000, 347 .flags = UPF_BOOT_AUTOCONF, 348 .type = PORT_SCIFA, 349 .irqs = { 88, 88, 88, 88 }, 350 .clk = "scif4", 351 },{ 352 .mapbase = 0xa4e50000, 353 .flags = UPF_BOOT_AUTOCONF, 354 .type = PORT_SCIFA, 355 .irqs = { 109, 109, 109, 109 }, 356 .clk = "scif5", 357 }, { 358 .flags = 0, 359 } 360 }; 361 362 static struct platform_device sci_device = { 363 .name = "sh-sci", 364 .id = -1, 365 .dev = { 366 .platform_data = sci_platform_data, 367 }, 368 }; 369 370 static struct resource rtc_resources[] = { 371 [0] = { 372 .start = 0xa465fec0, 373 .end = 0xa465fec0 + 0x58 - 1, 374 .flags = IORESOURCE_IO, 375 }, 376 [1] = { 377 /* Period IRQ */ 378 .start = 69, 379 .flags = IORESOURCE_IRQ, 380 }, 381 [2] = { 382 /* Carry IRQ */ 383 .start = 70, 384 .flags = IORESOURCE_IRQ, 385 }, 386 [3] = { 387 /* Alarm IRQ */ 388 .start = 68, 389 .flags = IORESOURCE_IRQ, 390 }, 391 }; 392 393 static struct platform_device rtc_device = { 394 .name = "sh-rtc", 395 .id = -1, 396 .num_resources = ARRAY_SIZE(rtc_resources), 397 .resource = rtc_resources, 398 }; 399 400 static struct r8a66597_platdata r8a66597_data = { 401 .on_chip = 1, 402 }; 403 404 static struct resource sh7723_usb_host_resources[] = { 405 [0] = { 406 .start = 0xa4d80000, 407 .end = 0xa4d800ff, 408 .flags = IORESOURCE_MEM, 409 }, 410 [1] = { 411 .start = 65, 412 .end = 65, 413 .flags = IORESOURCE_IRQ | IRQF_TRIGGER_LOW, 414 }, 415 }; 416 417 static struct platform_device sh7723_usb_host_device = { 418 .name = "r8a66597_hcd", 419 .id = 0, 420 .dev = { 421 .dma_mask = NULL, /* not use dma */ 422 .coherent_dma_mask = 0xffffffff, 423 .platform_data = &r8a66597_data, 424 }, 425 .num_resources = ARRAY_SIZE(sh7723_usb_host_resources), 426 .resource = sh7723_usb_host_resources, 427 }; 428 429 static struct resource iic_resources[] = { 430 [0] = { 431 .name = "IIC", 432 .start = 0x04470000, 433 .end = 0x04470017, 434 .flags = IORESOURCE_MEM, 435 }, 436 [1] = { 437 .start = 96, 438 .end = 99, 439 .flags = IORESOURCE_IRQ, 440 }, 441 }; 442 443 static struct platform_device iic_device = { 444 .name = "i2c-sh_mobile", 445 .id = 0, /* "i2c0" clock */ 446 .num_resources = ARRAY_SIZE(iic_resources), 447 .resource = iic_resources, 448 }; 449 450 static struct platform_device *sh7723_devices[] __initdata = { 451 &cmt_device, 452 &tmu0_device, 453 &tmu1_device, 454 &tmu2_device, 455 &tmu3_device, 456 &tmu4_device, 457 &tmu5_device, 458 &sci_device, 459 &rtc_device, 460 &iic_device, 461 &sh7723_usb_host_device, 462 &vpu_device, 463 &veu0_device, 464 &veu1_device, 465 }; 466 467 static int __init sh7723_devices_setup(void) 468 { 469 platform_resource_setup_memory(&vpu_device, "vpu", 2 << 20); 470 platform_resource_setup_memory(&veu0_device, "veu0", 2 << 20); 471 platform_resource_setup_memory(&veu1_device, "veu1", 2 << 20); 472 473 return platform_add_devices(sh7723_devices, 474 ARRAY_SIZE(sh7723_devices)); 475 } 476 __initcall(sh7723_devices_setup); 477 478 static struct platform_device *sh7723_early_devices[] __initdata = { 479 &cmt_device, 480 &tmu0_device, 481 &tmu1_device, 482 &tmu2_device, 483 &tmu3_device, 484 &tmu4_device, 485 &tmu5_device, 486 }; 487 488 void __init plat_early_device_setup(void) 489 { 490 early_platform_add_devices(sh7723_early_devices, 491 ARRAY_SIZE(sh7723_early_devices)); 492 } 493 494 #define RAMCR_CACHE_L2FC 0x0002 495 #define RAMCR_CACHE_L2E 0x0001 496 #define L2_CACHE_ENABLE (RAMCR_CACHE_L2E|RAMCR_CACHE_L2FC) 497 void __uses_jump_to_uncached l2_cache_init(void) 498 { 499 /* Enable L2 cache */ 500 ctrl_outl(L2_CACHE_ENABLE, RAMCR); 501 } 502 503 enum { 504 UNUSED=0, 505 506 /* interrupt sources */ 507 IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7, 508 HUDI, 509 DMAC1A_DEI0,DMAC1A_DEI1,DMAC1A_DEI2,DMAC1A_DEI3, 510 _2DG_TRI,_2DG_INI,_2DG_CEI, 511 DMAC0A_DEI0,DMAC0A_DEI1,DMAC0A_DEI2,DMAC0A_DEI3, 512 VIO_CEUI,VIO_BEUI,VIO_VEU2HI,VIO_VOUI, 513 SCIFA_SCIFA0, 514 VPU_VPUI, 515 TPU_TPUI, 516 ADC_ADI, 517 USB_USI0, 518 RTC_ATI,RTC_PRI,RTC_CUI, 519 DMAC1B_DEI4,DMAC1B_DEI5,DMAC1B_DADERR, 520 DMAC0B_DEI4,DMAC0B_DEI5,DMAC0B_DADERR, 521 KEYSC_KEYI, 522 SCIF_SCIF0,SCIF_SCIF1,SCIF_SCIF2, 523 MSIOF_MSIOFI0,MSIOF_MSIOFI1, 524 SCIFA_SCIFA1, 525 FLCTL_FLSTEI,FLCTL_FLTENDI,FLCTL_FLTREQ0I,FLCTL_FLTREQ1I, 526 I2C_ALI,I2C_TACKI,I2C_WAITI,I2C_DTEI, 527 SDHI0_SDHII0,SDHI0_SDHII1,SDHI0_SDHII2, 528 CMT_CMTI, 529 TSIF_TSIFI, 530 SIU_SIUI, 531 SCIFA_SCIFA2, 532 TMU0_TUNI0, TMU0_TUNI1, TMU0_TUNI2, 533 IRDA_IRDAI, 534 ATAPI_ATAPII, 535 SDHI1_SDHII0,SDHI1_SDHII1,SDHI1_SDHII2, 536 VEU2H1_VEU2HI, 537 LCDC_LCDCI, 538 TMU1_TUNI0,TMU1_TUNI1,TMU1_TUNI2, 539 540 /* interrupt groups */ 541 DMAC1A, DMAC0A, VIO, DMAC0B, FLCTL, I2C, _2DG, 542 SDHI1, RTC, DMAC1B, SDHI0, 543 }; 544 545 static struct intc_vect vectors[] __initdata = { 546 INTC_VECT(IRQ0, 0x600), INTC_VECT(IRQ1, 0x620), 547 INTC_VECT(IRQ2, 0x640), INTC_VECT(IRQ3, 0x660), 548 INTC_VECT(IRQ4, 0x680), INTC_VECT(IRQ5, 0x6a0), 549 INTC_VECT(IRQ6, 0x6c0), INTC_VECT(IRQ7, 0x6e0), 550 551 INTC_VECT(DMAC1A_DEI0,0x700), 552 INTC_VECT(DMAC1A_DEI1,0x720), 553 INTC_VECT(DMAC1A_DEI2,0x740), 554 INTC_VECT(DMAC1A_DEI3,0x760), 555 556 INTC_VECT(_2DG_TRI, 0x780), 557 INTC_VECT(_2DG_INI, 0x7A0), 558 INTC_VECT(_2DG_CEI, 0x7C0), 559 560 INTC_VECT(DMAC0A_DEI0,0x800), 561 INTC_VECT(DMAC0A_DEI1,0x820), 562 INTC_VECT(DMAC0A_DEI2,0x840), 563 INTC_VECT(DMAC0A_DEI3,0x860), 564 565 INTC_VECT(VIO_CEUI,0x880), 566 INTC_VECT(VIO_BEUI,0x8A0), 567 INTC_VECT(VIO_VEU2HI,0x8C0), 568 INTC_VECT(VIO_VOUI,0x8E0), 569 570 INTC_VECT(SCIFA_SCIFA0,0x900), 571 INTC_VECT(VPU_VPUI,0x980), 572 INTC_VECT(TPU_TPUI,0x9A0), 573 INTC_VECT(ADC_ADI,0x9E0), 574 INTC_VECT(USB_USI0,0xA20), 575 576 INTC_VECT(RTC_ATI,0xA80), 577 INTC_VECT(RTC_PRI,0xAA0), 578 INTC_VECT(RTC_CUI,0xAC0), 579 580 INTC_VECT(DMAC1B_DEI4,0xB00), 581 INTC_VECT(DMAC1B_DEI5,0xB20), 582 INTC_VECT(DMAC1B_DADERR,0xB40), 583 584 INTC_VECT(DMAC0B_DEI4,0xB80), 585 INTC_VECT(DMAC0B_DEI5,0xBA0), 586 INTC_VECT(DMAC0B_DADERR,0xBC0), 587 588 INTC_VECT(KEYSC_KEYI,0xBE0), 589 INTC_VECT(SCIF_SCIF0,0xC00), 590 INTC_VECT(SCIF_SCIF1,0xC20), 591 INTC_VECT(SCIF_SCIF2,0xC40), 592 INTC_VECT(MSIOF_MSIOFI0,0xC80), 593 INTC_VECT(MSIOF_MSIOFI1,0xCA0), 594 INTC_VECT(SCIFA_SCIFA1,0xD00), 595 596 INTC_VECT(FLCTL_FLSTEI,0xD80), 597 INTC_VECT(FLCTL_FLTENDI,0xDA0), 598 INTC_VECT(FLCTL_FLTREQ0I,0xDC0), 599 INTC_VECT(FLCTL_FLTREQ1I,0xDE0), 600 601 INTC_VECT(I2C_ALI,0xE00), 602 INTC_VECT(I2C_TACKI,0xE20), 603 INTC_VECT(I2C_WAITI,0xE40), 604 INTC_VECT(I2C_DTEI,0xE60), 605 606 INTC_VECT(SDHI0_SDHII0,0xE80), 607 INTC_VECT(SDHI0_SDHII1,0xEA0), 608 INTC_VECT(SDHI0_SDHII2,0xEC0), 609 610 INTC_VECT(CMT_CMTI,0xF00), 611 INTC_VECT(TSIF_TSIFI,0xF20), 612 INTC_VECT(SIU_SIUI,0xF80), 613 INTC_VECT(SCIFA_SCIFA2,0xFA0), 614 615 INTC_VECT(TMU0_TUNI0,0x400), 616 INTC_VECT(TMU0_TUNI1,0x420), 617 INTC_VECT(TMU0_TUNI2,0x440), 618 619 INTC_VECT(IRDA_IRDAI,0x480), 620 INTC_VECT(ATAPI_ATAPII,0x4A0), 621 622 INTC_VECT(SDHI1_SDHII0,0x4E0), 623 INTC_VECT(SDHI1_SDHII1,0x500), 624 INTC_VECT(SDHI1_SDHII2,0x520), 625 626 INTC_VECT(VEU2H1_VEU2HI,0x560), 627 INTC_VECT(LCDC_LCDCI,0x580), 628 629 INTC_VECT(TMU1_TUNI0,0x920), 630 INTC_VECT(TMU1_TUNI1,0x940), 631 INTC_VECT(TMU1_TUNI2,0x960), 632 633 }; 634 635 static struct intc_group groups[] __initdata = { 636 INTC_GROUP(DMAC1A,DMAC1A_DEI0,DMAC1A_DEI1,DMAC1A_DEI2,DMAC1A_DEI3), 637 INTC_GROUP(DMAC0A,DMAC0A_DEI0,DMAC0A_DEI1,DMAC0A_DEI2,DMAC0A_DEI3), 638 INTC_GROUP(VIO, VIO_CEUI,VIO_BEUI,VIO_VEU2HI,VIO_VOUI), 639 INTC_GROUP(DMAC0B, DMAC0B_DEI4,DMAC0B_DEI5,DMAC0B_DADERR), 640 INTC_GROUP(FLCTL,FLCTL_FLSTEI,FLCTL_FLTENDI,FLCTL_FLTREQ0I,FLCTL_FLTREQ1I), 641 INTC_GROUP(I2C,I2C_ALI,I2C_TACKI,I2C_WAITI,I2C_DTEI), 642 INTC_GROUP(_2DG, _2DG_TRI,_2DG_INI,_2DG_CEI), 643 INTC_GROUP(SDHI1, SDHI1_SDHII0,SDHI1_SDHII1,SDHI1_SDHII2), 644 INTC_GROUP(RTC, RTC_ATI,RTC_PRI,RTC_CUI), 645 INTC_GROUP(DMAC1B, DMAC1B_DEI4,DMAC1B_DEI5,DMAC1B_DADERR), 646 INTC_GROUP(SDHI0,SDHI0_SDHII0,SDHI0_SDHII1,SDHI0_SDHII2), 647 }; 648 649 static struct intc_mask_reg mask_registers[] __initdata = { 650 { 0xa4080080, 0xa40800c0, 8, /* IMR0 / IMCR0 */ 651 { 0, TMU1_TUNI2,TMU1_TUNI1,TMU1_TUNI0,0,SDHI1_SDHII2,SDHI1_SDHII1,SDHI1_SDHII0} }, 652 { 0xa4080084, 0xa40800c4, 8, /* IMR1 / IMCR1 */ 653 { VIO_VOUI, VIO_VEU2HI,VIO_BEUI,VIO_CEUI,DMAC0A_DEI3,DMAC0A_DEI2,DMAC0A_DEI1,DMAC0A_DEI0 } }, 654 { 0xa4080088, 0xa40800c8, 8, /* IMR2 / IMCR2 */ 655 { 0, 0, 0, VPU_VPUI,0,0,0,SCIFA_SCIFA0 } }, 656 { 0xa408008c, 0xa40800cc, 8, /* IMR3 / IMCR3 */ 657 { DMAC1A_DEI3,DMAC1A_DEI2,DMAC1A_DEI1,DMAC1A_DEI0,0,0,0,IRDA_IRDAI } }, 658 { 0xa4080090, 0xa40800d0, 8, /* IMR4 / IMCR4 */ 659 { 0,TMU0_TUNI2,TMU0_TUNI1,TMU0_TUNI0,VEU2H1_VEU2HI,0,0,LCDC_LCDCI } }, 660 { 0xa4080094, 0xa40800d4, 8, /* IMR5 / IMCR5 */ 661 { KEYSC_KEYI,DMAC0B_DADERR,DMAC0B_DEI5,DMAC0B_DEI4,0,SCIF_SCIF2,SCIF_SCIF1,SCIF_SCIF0 } }, 662 { 0xa4080098, 0xa40800d8, 8, /* IMR6 / IMCR6 */ 663 { 0,0,0,SCIFA_SCIFA1,ADC_ADI,0,MSIOF_MSIOFI1,MSIOF_MSIOFI0 } }, 664 { 0xa408009c, 0xa40800dc, 8, /* IMR7 / IMCR7 */ 665 { I2C_DTEI, I2C_WAITI, I2C_TACKI, I2C_ALI, 666 FLCTL_FLTREQ1I, FLCTL_FLTREQ0I, FLCTL_FLTENDI, FLCTL_FLSTEI } }, 667 { 0xa40800a0, 0xa40800e0, 8, /* IMR8 / IMCR8 */ 668 { 0,SDHI0_SDHII2,SDHI0_SDHII1,SDHI0_SDHII0,0,0,SCIFA_SCIFA2,SIU_SIUI } }, 669 { 0xa40800a4, 0xa40800e4, 8, /* IMR9 / IMCR9 */ 670 { 0, 0, 0, CMT_CMTI, 0, 0, USB_USI0,0 } }, 671 { 0xa40800a8, 0xa40800e8, 8, /* IMR10 / IMCR10 */ 672 { 0, DMAC1B_DADERR,DMAC1B_DEI5,DMAC1B_DEI4,0,RTC_ATI,RTC_PRI,RTC_CUI } }, 673 { 0xa40800ac, 0xa40800ec, 8, /* IMR11 / IMCR11 */ 674 { 0,_2DG_CEI,_2DG_INI,_2DG_TRI,0,TPU_TPUI,0,TSIF_TSIFI } }, 675 { 0xa40800b0, 0xa40800f0, 8, /* IMR12 / IMCR12 */ 676 { 0,0,0,0,0,0,0,ATAPI_ATAPII } }, 677 { 0xa4140044, 0xa4140064, 8, /* INTMSK00 / INTMSKCLR00 */ 678 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } }, 679 }; 680 681 static struct intc_prio_reg prio_registers[] __initdata = { 682 { 0xa4080000, 0, 16, 4, /* IPRA */ { TMU0_TUNI0, TMU0_TUNI1, TMU0_TUNI2, IRDA_IRDAI } }, 683 { 0xa4080004, 0, 16, 4, /* IPRB */ { VEU2H1_VEU2HI, LCDC_LCDCI, DMAC1A, 0} }, 684 { 0xa4080008, 0, 16, 4, /* IPRC */ { TMU1_TUNI0, TMU1_TUNI1, TMU1_TUNI2, 0} }, 685 { 0xa408000c, 0, 16, 4, /* IPRD */ { } }, 686 { 0xa4080010, 0, 16, 4, /* IPRE */ { DMAC0A, VIO, SCIFA_SCIFA0, VPU_VPUI } }, 687 { 0xa4080014, 0, 16, 4, /* IPRF */ { KEYSC_KEYI, DMAC0B, USB_USI0, CMT_CMTI } }, 688 { 0xa4080018, 0, 16, 4, /* IPRG */ { SCIF_SCIF0, SCIF_SCIF1, SCIF_SCIF2,0 } }, 689 { 0xa408001c, 0, 16, 4, /* IPRH */ { MSIOF_MSIOFI0,MSIOF_MSIOFI1, FLCTL, I2C } }, 690 { 0xa4080020, 0, 16, 4, /* IPRI */ { SCIFA_SCIFA1,0,TSIF_TSIFI,_2DG } }, 691 { 0xa4080024, 0, 16, 4, /* IPRJ */ { ADC_ADI,0,SIU_SIUI,SDHI1 } }, 692 { 0xa4080028, 0, 16, 4, /* IPRK */ { RTC,DMAC1B,0,SDHI0 } }, 693 { 0xa408002c, 0, 16, 4, /* IPRL */ { SCIFA_SCIFA2,0,TPU_TPUI,ATAPI_ATAPII } }, 694 { 0xa4140010, 0, 32, 4, /* INTPRI00 */ 695 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } }, 696 }; 697 698 static struct intc_sense_reg sense_registers[] __initdata = { 699 { 0xa414001c, 16, 2, /* ICR1 */ 700 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } }, 701 }; 702 703 static struct intc_mask_reg ack_registers[] __initdata = { 704 { 0xa4140024, 0, 8, /* INTREQ00 */ 705 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } }, 706 }; 707 708 static DECLARE_INTC_DESC_ACK(intc_desc, "sh7723", vectors, groups, 709 mask_registers, prio_registers, sense_registers, 710 ack_registers); 711 712 void __init plat_irq_setup(void) 713 { 714 register_intc_controller(&intc_desc); 715 } 716