1 /* 2 * SH7723 Setup 3 * 4 * Copyright (C) 2008 Paul Mundt 5 * 6 * This file is subject to the terms and conditions of the GNU General Public 7 * License. See the file "COPYING" in the main directory of this archive 8 * for more details. 9 */ 10 #include <linux/platform_device.h> 11 #include <linux/init.h> 12 #include <linux/serial.h> 13 #include <linux/mm.h> 14 #include <linux/serial_sci.h> 15 #include <linux/uio_driver.h> 16 #include <linux/usb/r8a66597.h> 17 #include <linux/sh_timer.h> 18 #include <linux/io.h> 19 #include <asm/clock.h> 20 #include <asm/mmzone.h> 21 #include <cpu/sh7723.h> 22 23 /* Serial */ 24 static struct plat_sci_port scif0_platform_data = { 25 .mapbase = 0xffe00000, 26 .flags = UPF_BOOT_AUTOCONF, 27 .type = PORT_SCIF, 28 .irqs = { 80, 80, 80, 80 }, 29 .clk = "scif0", 30 }; 31 32 static struct platform_device scif0_device = { 33 .name = "sh-sci", 34 .id = 0, 35 .dev = { 36 .platform_data = &scif0_platform_data, 37 }, 38 }; 39 40 static struct plat_sci_port scif1_platform_data = { 41 .mapbase = 0xffe10000, 42 .flags = UPF_BOOT_AUTOCONF, 43 .type = PORT_SCIF, 44 .irqs = { 81, 81, 81, 81 }, 45 .clk = "scif1", 46 }; 47 48 static struct platform_device scif1_device = { 49 .name = "sh-sci", 50 .id = 1, 51 .dev = { 52 .platform_data = &scif1_platform_data, 53 }, 54 }; 55 56 static struct plat_sci_port scif2_platform_data = { 57 .mapbase = 0xffe20000, 58 .flags = UPF_BOOT_AUTOCONF, 59 .type = PORT_SCIF, 60 .irqs = { 82, 82, 82, 82 }, 61 .clk = "scif2", 62 }; 63 64 static struct platform_device scif2_device = { 65 .name = "sh-sci", 66 .id = 2, 67 .dev = { 68 .platform_data = &scif2_platform_data, 69 }, 70 }; 71 72 static struct plat_sci_port scif3_platform_data = { 73 .mapbase = 0xa4e30000, 74 .flags = UPF_BOOT_AUTOCONF, 75 .type = PORT_SCIFA, 76 .irqs = { 56, 56, 56, 56 }, 77 .clk = "scif3", 78 }; 79 80 static struct platform_device scif3_device = { 81 .name = "sh-sci", 82 .id = 3, 83 .dev = { 84 .platform_data = &scif3_platform_data, 85 }, 86 }; 87 88 static struct plat_sci_port scif4_platform_data = { 89 .mapbase = 0xa4e40000, 90 .flags = UPF_BOOT_AUTOCONF, 91 .type = PORT_SCIFA, 92 .irqs = { 88, 88, 88, 88 }, 93 .clk = "scif4", 94 }; 95 96 static struct platform_device scif4_device = { 97 .name = "sh-sci", 98 .id = 4, 99 .dev = { 100 .platform_data = &scif4_platform_data, 101 }, 102 }; 103 104 static struct plat_sci_port scif5_platform_data = { 105 .mapbase = 0xa4e50000, 106 .flags = UPF_BOOT_AUTOCONF, 107 .type = PORT_SCIFA, 108 .irqs = { 109, 109, 109, 109 }, 109 .clk = "scif5", 110 }; 111 112 static struct platform_device scif5_device = { 113 .name = "sh-sci", 114 .id = 5, 115 .dev = { 116 .platform_data = &scif5_platform_data, 117 }, 118 }; 119 120 static struct uio_info vpu_platform_data = { 121 .name = "VPU5", 122 .version = "0", 123 .irq = 60, 124 }; 125 126 static struct resource vpu_resources[] = { 127 [0] = { 128 .name = "VPU", 129 .start = 0xfe900000, 130 .end = 0xfe902807, 131 .flags = IORESOURCE_MEM, 132 }, 133 [1] = { 134 /* place holder for contiguous memory */ 135 }, 136 }; 137 138 static struct platform_device vpu_device = { 139 .name = "uio_pdrv_genirq", 140 .id = 0, 141 .dev = { 142 .platform_data = &vpu_platform_data, 143 }, 144 .resource = vpu_resources, 145 .num_resources = ARRAY_SIZE(vpu_resources), 146 .archdata = { 147 .hwblk_id = HWBLK_VPU, 148 }, 149 }; 150 151 static struct uio_info veu0_platform_data = { 152 .name = "VEU2H", 153 .version = "0", 154 .irq = 54, 155 }; 156 157 static struct resource veu0_resources[] = { 158 [0] = { 159 .name = "VEU2H0", 160 .start = 0xfe920000, 161 .end = 0xfe92027b, 162 .flags = IORESOURCE_MEM, 163 }, 164 [1] = { 165 /* place holder for contiguous memory */ 166 }, 167 }; 168 169 static struct platform_device veu0_device = { 170 .name = "uio_pdrv_genirq", 171 .id = 1, 172 .dev = { 173 .platform_data = &veu0_platform_data, 174 }, 175 .resource = veu0_resources, 176 .num_resources = ARRAY_SIZE(veu0_resources), 177 .archdata = { 178 .hwblk_id = HWBLK_VEU2H0, 179 }, 180 }; 181 182 static struct uio_info veu1_platform_data = { 183 .name = "VEU2H", 184 .version = "0", 185 .irq = 27, 186 }; 187 188 static struct resource veu1_resources[] = { 189 [0] = { 190 .name = "VEU2H1", 191 .start = 0xfe924000, 192 .end = 0xfe92427b, 193 .flags = IORESOURCE_MEM, 194 }, 195 [1] = { 196 /* place holder for contiguous memory */ 197 }, 198 }; 199 200 static struct platform_device veu1_device = { 201 .name = "uio_pdrv_genirq", 202 .id = 2, 203 .dev = { 204 .platform_data = &veu1_platform_data, 205 }, 206 .resource = veu1_resources, 207 .num_resources = ARRAY_SIZE(veu1_resources), 208 .archdata = { 209 .hwblk_id = HWBLK_VEU2H1, 210 }, 211 }; 212 213 static struct sh_timer_config cmt_platform_data = { 214 .name = "CMT", 215 .channel_offset = 0x60, 216 .timer_bit = 5, 217 .clk = "cmt0", 218 .clockevent_rating = 125, 219 .clocksource_rating = 125, 220 }; 221 222 static struct resource cmt_resources[] = { 223 [0] = { 224 .name = "CMT", 225 .start = 0x044a0060, 226 .end = 0x044a006b, 227 .flags = IORESOURCE_MEM, 228 }, 229 [1] = { 230 .start = 104, 231 .flags = IORESOURCE_IRQ, 232 }, 233 }; 234 235 static struct platform_device cmt_device = { 236 .name = "sh_cmt", 237 .id = 0, 238 .dev = { 239 .platform_data = &cmt_platform_data, 240 }, 241 .resource = cmt_resources, 242 .num_resources = ARRAY_SIZE(cmt_resources), 243 .archdata = { 244 .hwblk_id = HWBLK_CMT, 245 }, 246 }; 247 248 static struct sh_timer_config tmu0_platform_data = { 249 .name = "TMU0", 250 .channel_offset = 0x04, 251 .timer_bit = 0, 252 .clk = "tmu0", 253 .clockevent_rating = 200, 254 }; 255 256 static struct resource tmu0_resources[] = { 257 [0] = { 258 .name = "TMU0", 259 .start = 0xffd80008, 260 .end = 0xffd80013, 261 .flags = IORESOURCE_MEM, 262 }, 263 [1] = { 264 .start = 16, 265 .flags = IORESOURCE_IRQ, 266 }, 267 }; 268 269 static struct platform_device tmu0_device = { 270 .name = "sh_tmu", 271 .id = 0, 272 .dev = { 273 .platform_data = &tmu0_platform_data, 274 }, 275 .resource = tmu0_resources, 276 .num_resources = ARRAY_SIZE(tmu0_resources), 277 .archdata = { 278 .hwblk_id = HWBLK_TMU0, 279 }, 280 }; 281 282 static struct sh_timer_config tmu1_platform_data = { 283 .name = "TMU1", 284 .channel_offset = 0x10, 285 .timer_bit = 1, 286 .clk = "tmu0", 287 .clocksource_rating = 200, 288 }; 289 290 static struct resource tmu1_resources[] = { 291 [0] = { 292 .name = "TMU1", 293 .start = 0xffd80014, 294 .end = 0xffd8001f, 295 .flags = IORESOURCE_MEM, 296 }, 297 [1] = { 298 .start = 17, 299 .flags = IORESOURCE_IRQ, 300 }, 301 }; 302 303 static struct platform_device tmu1_device = { 304 .name = "sh_tmu", 305 .id = 1, 306 .dev = { 307 .platform_data = &tmu1_platform_data, 308 }, 309 .resource = tmu1_resources, 310 .num_resources = ARRAY_SIZE(tmu1_resources), 311 .archdata = { 312 .hwblk_id = HWBLK_TMU0, 313 }, 314 }; 315 316 static struct sh_timer_config tmu2_platform_data = { 317 .name = "TMU2", 318 .channel_offset = 0x1c, 319 .timer_bit = 2, 320 .clk = "tmu0", 321 }; 322 323 static struct resource tmu2_resources[] = { 324 [0] = { 325 .name = "TMU2", 326 .start = 0xffd80020, 327 .end = 0xffd8002b, 328 .flags = IORESOURCE_MEM, 329 }, 330 [1] = { 331 .start = 18, 332 .flags = IORESOURCE_IRQ, 333 }, 334 }; 335 336 static struct platform_device tmu2_device = { 337 .name = "sh_tmu", 338 .id = 2, 339 .dev = { 340 .platform_data = &tmu2_platform_data, 341 }, 342 .resource = tmu2_resources, 343 .num_resources = ARRAY_SIZE(tmu2_resources), 344 .archdata = { 345 .hwblk_id = HWBLK_TMU0, 346 }, 347 }; 348 349 static struct sh_timer_config tmu3_platform_data = { 350 .name = "TMU3", 351 .channel_offset = 0x04, 352 .timer_bit = 0, 353 .clk = "tmu1", 354 }; 355 356 static struct resource tmu3_resources[] = { 357 [0] = { 358 .name = "TMU3", 359 .start = 0xffd90008, 360 .end = 0xffd90013, 361 .flags = IORESOURCE_MEM, 362 }, 363 [1] = { 364 .start = 57, 365 .flags = IORESOURCE_IRQ, 366 }, 367 }; 368 369 static struct platform_device tmu3_device = { 370 .name = "sh_tmu", 371 .id = 3, 372 .dev = { 373 .platform_data = &tmu3_platform_data, 374 }, 375 .resource = tmu3_resources, 376 .num_resources = ARRAY_SIZE(tmu3_resources), 377 .archdata = { 378 .hwblk_id = HWBLK_TMU1, 379 }, 380 }; 381 382 static struct sh_timer_config tmu4_platform_data = { 383 .name = "TMU4", 384 .channel_offset = 0x10, 385 .timer_bit = 1, 386 .clk = "tmu1", 387 }; 388 389 static struct resource tmu4_resources[] = { 390 [0] = { 391 .name = "TMU4", 392 .start = 0xffd90014, 393 .end = 0xffd9001f, 394 .flags = IORESOURCE_MEM, 395 }, 396 [1] = { 397 .start = 58, 398 .flags = IORESOURCE_IRQ, 399 }, 400 }; 401 402 static struct platform_device tmu4_device = { 403 .name = "sh_tmu", 404 .id = 4, 405 .dev = { 406 .platform_data = &tmu4_platform_data, 407 }, 408 .resource = tmu4_resources, 409 .num_resources = ARRAY_SIZE(tmu4_resources), 410 .archdata = { 411 .hwblk_id = HWBLK_TMU1, 412 }, 413 }; 414 415 static struct sh_timer_config tmu5_platform_data = { 416 .name = "TMU5", 417 .channel_offset = 0x1c, 418 .timer_bit = 2, 419 .clk = "tmu1", 420 }; 421 422 static struct resource tmu5_resources[] = { 423 [0] = { 424 .name = "TMU5", 425 .start = 0xffd90020, 426 .end = 0xffd9002b, 427 .flags = IORESOURCE_MEM, 428 }, 429 [1] = { 430 .start = 57, 431 .flags = IORESOURCE_IRQ, 432 }, 433 }; 434 435 static struct platform_device tmu5_device = { 436 .name = "sh_tmu", 437 .id = 5, 438 .dev = { 439 .platform_data = &tmu5_platform_data, 440 }, 441 .resource = tmu5_resources, 442 .num_resources = ARRAY_SIZE(tmu5_resources), 443 .archdata = { 444 .hwblk_id = HWBLK_TMU1, 445 }, 446 }; 447 448 static struct resource rtc_resources[] = { 449 [0] = { 450 .start = 0xa465fec0, 451 .end = 0xa465fec0 + 0x58 - 1, 452 .flags = IORESOURCE_IO, 453 }, 454 [1] = { 455 /* Period IRQ */ 456 .start = 69, 457 .flags = IORESOURCE_IRQ, 458 }, 459 [2] = { 460 /* Carry IRQ */ 461 .start = 70, 462 .flags = IORESOURCE_IRQ, 463 }, 464 [3] = { 465 /* Alarm IRQ */ 466 .start = 68, 467 .flags = IORESOURCE_IRQ, 468 }, 469 }; 470 471 static struct platform_device rtc_device = { 472 .name = "sh-rtc", 473 .id = -1, 474 .num_resources = ARRAY_SIZE(rtc_resources), 475 .resource = rtc_resources, 476 .archdata = { 477 .hwblk_id = HWBLK_RTC, 478 }, 479 }; 480 481 static struct r8a66597_platdata r8a66597_data = { 482 .on_chip = 1, 483 }; 484 485 static struct resource sh7723_usb_host_resources[] = { 486 [0] = { 487 .start = 0xa4d80000, 488 .end = 0xa4d800ff, 489 .flags = IORESOURCE_MEM, 490 }, 491 [1] = { 492 .start = 65, 493 .end = 65, 494 .flags = IORESOURCE_IRQ | IRQF_TRIGGER_LOW, 495 }, 496 }; 497 498 static struct platform_device sh7723_usb_host_device = { 499 .name = "r8a66597_hcd", 500 .id = 0, 501 .dev = { 502 .dma_mask = NULL, /* not use dma */ 503 .coherent_dma_mask = 0xffffffff, 504 .platform_data = &r8a66597_data, 505 }, 506 .num_resources = ARRAY_SIZE(sh7723_usb_host_resources), 507 .resource = sh7723_usb_host_resources, 508 .archdata = { 509 .hwblk_id = HWBLK_USB, 510 }, 511 }; 512 513 static struct resource iic_resources[] = { 514 [0] = { 515 .name = "IIC", 516 .start = 0x04470000, 517 .end = 0x04470017, 518 .flags = IORESOURCE_MEM, 519 }, 520 [1] = { 521 .start = 96, 522 .end = 99, 523 .flags = IORESOURCE_IRQ, 524 }, 525 }; 526 527 static struct platform_device iic_device = { 528 .name = "i2c-sh_mobile", 529 .id = 0, /* "i2c0" clock */ 530 .num_resources = ARRAY_SIZE(iic_resources), 531 .resource = iic_resources, 532 .archdata = { 533 .hwblk_id = HWBLK_IIC, 534 }, 535 }; 536 537 static struct platform_device *sh7723_devices[] __initdata = { 538 &scif0_device, 539 &scif1_device, 540 &scif2_device, 541 &scif3_device, 542 &scif4_device, 543 &scif5_device, 544 &cmt_device, 545 &tmu0_device, 546 &tmu1_device, 547 &tmu2_device, 548 &tmu3_device, 549 &tmu4_device, 550 &tmu5_device, 551 &rtc_device, 552 &iic_device, 553 &sh7723_usb_host_device, 554 &vpu_device, 555 &veu0_device, 556 &veu1_device, 557 }; 558 559 static int __init sh7723_devices_setup(void) 560 { 561 platform_resource_setup_memory(&vpu_device, "vpu", 2 << 20); 562 platform_resource_setup_memory(&veu0_device, "veu0", 2 << 20); 563 platform_resource_setup_memory(&veu1_device, "veu1", 2 << 20); 564 565 return platform_add_devices(sh7723_devices, 566 ARRAY_SIZE(sh7723_devices)); 567 } 568 arch_initcall(sh7723_devices_setup); 569 570 static struct platform_device *sh7723_early_devices[] __initdata = { 571 &scif0_device, 572 &scif1_device, 573 &scif2_device, 574 &scif3_device, 575 &scif4_device, 576 &scif5_device, 577 &cmt_device, 578 &tmu0_device, 579 &tmu1_device, 580 &tmu2_device, 581 &tmu3_device, 582 &tmu4_device, 583 &tmu5_device, 584 }; 585 586 void __init plat_early_device_setup(void) 587 { 588 early_platform_add_devices(sh7723_early_devices, 589 ARRAY_SIZE(sh7723_early_devices)); 590 } 591 592 #define RAMCR_CACHE_L2FC 0x0002 593 #define RAMCR_CACHE_L2E 0x0001 594 #define L2_CACHE_ENABLE (RAMCR_CACHE_L2E|RAMCR_CACHE_L2FC) 595 596 void l2_cache_init(void) 597 { 598 /* Enable L2 cache */ 599 __raw_writel(L2_CACHE_ENABLE, RAMCR); 600 } 601 602 enum { 603 UNUSED=0, 604 ENABLED, 605 DISABLED, 606 607 /* interrupt sources */ 608 IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7, 609 HUDI, 610 DMAC1A_DEI0,DMAC1A_DEI1,DMAC1A_DEI2,DMAC1A_DEI3, 611 _2DG_TRI,_2DG_INI,_2DG_CEI, 612 DMAC0A_DEI0,DMAC0A_DEI1,DMAC0A_DEI2,DMAC0A_DEI3, 613 VIO_CEUI,VIO_BEUI,VIO_VEU2HI,VIO_VOUI, 614 SCIFA_SCIFA0, 615 VPU_VPUI, 616 TPU_TPUI, 617 ADC_ADI, 618 USB_USI0, 619 RTC_ATI,RTC_PRI,RTC_CUI, 620 DMAC1B_DEI4,DMAC1B_DEI5,DMAC1B_DADERR, 621 DMAC0B_DEI4,DMAC0B_DEI5,DMAC0B_DADERR, 622 KEYSC_KEYI, 623 SCIF_SCIF0,SCIF_SCIF1,SCIF_SCIF2, 624 MSIOF_MSIOFI0,MSIOF_MSIOFI1, 625 SCIFA_SCIFA1, 626 FLCTL_FLSTEI,FLCTL_FLTENDI,FLCTL_FLTREQ0I,FLCTL_FLTREQ1I, 627 I2C_ALI,I2C_TACKI,I2C_WAITI,I2C_DTEI, 628 CMT_CMTI, 629 TSIF_TSIFI, 630 SIU_SIUI, 631 SCIFA_SCIFA2, 632 TMU0_TUNI0, TMU0_TUNI1, TMU0_TUNI2, 633 IRDA_IRDAI, 634 ATAPI_ATAPII, 635 VEU2H1_VEU2HI, 636 LCDC_LCDCI, 637 TMU1_TUNI0,TMU1_TUNI1,TMU1_TUNI2, 638 639 /* interrupt groups */ 640 DMAC1A, DMAC0A, VIO, DMAC0B, FLCTL, I2C, _2DG, 641 SDHI1, RTC, DMAC1B, SDHI0, 642 }; 643 644 static struct intc_vect vectors[] __initdata = { 645 INTC_VECT(IRQ0, 0x600), INTC_VECT(IRQ1, 0x620), 646 INTC_VECT(IRQ2, 0x640), INTC_VECT(IRQ3, 0x660), 647 INTC_VECT(IRQ4, 0x680), INTC_VECT(IRQ5, 0x6a0), 648 INTC_VECT(IRQ6, 0x6c0), INTC_VECT(IRQ7, 0x6e0), 649 650 INTC_VECT(DMAC1A_DEI0,0x700), 651 INTC_VECT(DMAC1A_DEI1,0x720), 652 INTC_VECT(DMAC1A_DEI2,0x740), 653 INTC_VECT(DMAC1A_DEI3,0x760), 654 655 INTC_VECT(_2DG_TRI, 0x780), 656 INTC_VECT(_2DG_INI, 0x7A0), 657 INTC_VECT(_2DG_CEI, 0x7C0), 658 659 INTC_VECT(DMAC0A_DEI0,0x800), 660 INTC_VECT(DMAC0A_DEI1,0x820), 661 INTC_VECT(DMAC0A_DEI2,0x840), 662 INTC_VECT(DMAC0A_DEI3,0x860), 663 664 INTC_VECT(VIO_CEUI,0x880), 665 INTC_VECT(VIO_BEUI,0x8A0), 666 INTC_VECT(VIO_VEU2HI,0x8C0), 667 INTC_VECT(VIO_VOUI,0x8E0), 668 669 INTC_VECT(SCIFA_SCIFA0,0x900), 670 INTC_VECT(VPU_VPUI,0x980), 671 INTC_VECT(TPU_TPUI,0x9A0), 672 INTC_VECT(ADC_ADI,0x9E0), 673 INTC_VECT(USB_USI0,0xA20), 674 675 INTC_VECT(RTC_ATI,0xA80), 676 INTC_VECT(RTC_PRI,0xAA0), 677 INTC_VECT(RTC_CUI,0xAC0), 678 679 INTC_VECT(DMAC1B_DEI4,0xB00), 680 INTC_VECT(DMAC1B_DEI5,0xB20), 681 INTC_VECT(DMAC1B_DADERR,0xB40), 682 683 INTC_VECT(DMAC0B_DEI4,0xB80), 684 INTC_VECT(DMAC0B_DEI5,0xBA0), 685 INTC_VECT(DMAC0B_DADERR,0xBC0), 686 687 INTC_VECT(KEYSC_KEYI,0xBE0), 688 INTC_VECT(SCIF_SCIF0,0xC00), 689 INTC_VECT(SCIF_SCIF1,0xC20), 690 INTC_VECT(SCIF_SCIF2,0xC40), 691 INTC_VECT(MSIOF_MSIOFI0,0xC80), 692 INTC_VECT(MSIOF_MSIOFI1,0xCA0), 693 INTC_VECT(SCIFA_SCIFA1,0xD00), 694 695 INTC_VECT(FLCTL_FLSTEI,0xD80), 696 INTC_VECT(FLCTL_FLTENDI,0xDA0), 697 INTC_VECT(FLCTL_FLTREQ0I,0xDC0), 698 INTC_VECT(FLCTL_FLTREQ1I,0xDE0), 699 700 INTC_VECT(I2C_ALI,0xE00), 701 INTC_VECT(I2C_TACKI,0xE20), 702 INTC_VECT(I2C_WAITI,0xE40), 703 INTC_VECT(I2C_DTEI,0xE60), 704 705 INTC_VECT(SDHI0, 0xE80), 706 INTC_VECT(SDHI0, 0xEA0), 707 INTC_VECT(SDHI0, 0xEC0), 708 709 INTC_VECT(CMT_CMTI,0xF00), 710 INTC_VECT(TSIF_TSIFI,0xF20), 711 INTC_VECT(SIU_SIUI,0xF80), 712 INTC_VECT(SCIFA_SCIFA2,0xFA0), 713 714 INTC_VECT(TMU0_TUNI0,0x400), 715 INTC_VECT(TMU0_TUNI1,0x420), 716 INTC_VECT(TMU0_TUNI2,0x440), 717 718 INTC_VECT(IRDA_IRDAI,0x480), 719 INTC_VECT(ATAPI_ATAPII,0x4A0), 720 721 INTC_VECT(SDHI1, 0x4E0), 722 INTC_VECT(SDHI1, 0x500), 723 INTC_VECT(SDHI1, 0x520), 724 725 INTC_VECT(VEU2H1_VEU2HI,0x560), 726 INTC_VECT(LCDC_LCDCI,0x580), 727 728 INTC_VECT(TMU1_TUNI0,0x920), 729 INTC_VECT(TMU1_TUNI1,0x940), 730 INTC_VECT(TMU1_TUNI2,0x960), 731 732 }; 733 734 static struct intc_group groups[] __initdata = { 735 INTC_GROUP(DMAC1A,DMAC1A_DEI0,DMAC1A_DEI1,DMAC1A_DEI2,DMAC1A_DEI3), 736 INTC_GROUP(DMAC0A,DMAC0A_DEI0,DMAC0A_DEI1,DMAC0A_DEI2,DMAC0A_DEI3), 737 INTC_GROUP(VIO, VIO_CEUI,VIO_BEUI,VIO_VEU2HI,VIO_VOUI), 738 INTC_GROUP(DMAC0B, DMAC0B_DEI4,DMAC0B_DEI5,DMAC0B_DADERR), 739 INTC_GROUP(FLCTL,FLCTL_FLSTEI,FLCTL_FLTENDI,FLCTL_FLTREQ0I,FLCTL_FLTREQ1I), 740 INTC_GROUP(I2C,I2C_ALI,I2C_TACKI,I2C_WAITI,I2C_DTEI), 741 INTC_GROUP(_2DG, _2DG_TRI,_2DG_INI,_2DG_CEI), 742 INTC_GROUP(RTC, RTC_ATI,RTC_PRI,RTC_CUI), 743 INTC_GROUP(DMAC1B, DMAC1B_DEI4,DMAC1B_DEI5,DMAC1B_DADERR), 744 }; 745 746 static struct intc_mask_reg mask_registers[] __initdata = { 747 { 0xa4080080, 0xa40800c0, 8, /* IMR0 / IMCR0 */ 748 { 0, TMU1_TUNI2, TMU1_TUNI1, TMU1_TUNI0, 749 0, DISABLED, ENABLED, ENABLED } }, 750 { 0xa4080084, 0xa40800c4, 8, /* IMR1 / IMCR1 */ 751 { VIO_VOUI, VIO_VEU2HI,VIO_BEUI,VIO_CEUI,DMAC0A_DEI3,DMAC0A_DEI2,DMAC0A_DEI1,DMAC0A_DEI0 } }, 752 { 0xa4080088, 0xa40800c8, 8, /* IMR2 / IMCR2 */ 753 { 0, 0, 0, VPU_VPUI,0,0,0,SCIFA_SCIFA0 } }, 754 { 0xa408008c, 0xa40800cc, 8, /* IMR3 / IMCR3 */ 755 { DMAC1A_DEI3,DMAC1A_DEI2,DMAC1A_DEI1,DMAC1A_DEI0,0,0,0,IRDA_IRDAI } }, 756 { 0xa4080090, 0xa40800d0, 8, /* IMR4 / IMCR4 */ 757 { 0,TMU0_TUNI2,TMU0_TUNI1,TMU0_TUNI0,VEU2H1_VEU2HI,0,0,LCDC_LCDCI } }, 758 { 0xa4080094, 0xa40800d4, 8, /* IMR5 / IMCR5 */ 759 { KEYSC_KEYI,DMAC0B_DADERR,DMAC0B_DEI5,DMAC0B_DEI4,0,SCIF_SCIF2,SCIF_SCIF1,SCIF_SCIF0 } }, 760 { 0xa4080098, 0xa40800d8, 8, /* IMR6 / IMCR6 */ 761 { 0,0,0,SCIFA_SCIFA1,ADC_ADI,0,MSIOF_MSIOFI1,MSIOF_MSIOFI0 } }, 762 { 0xa408009c, 0xa40800dc, 8, /* IMR7 / IMCR7 */ 763 { I2C_DTEI, I2C_WAITI, I2C_TACKI, I2C_ALI, 764 FLCTL_FLTREQ1I, FLCTL_FLTREQ0I, FLCTL_FLTENDI, FLCTL_FLSTEI } }, 765 { 0xa40800a0, 0xa40800e0, 8, /* IMR8 / IMCR8 */ 766 { 0, DISABLED, ENABLED, ENABLED, 767 0, 0, SCIFA_SCIFA2, SIU_SIUI } }, 768 { 0xa40800a4, 0xa40800e4, 8, /* IMR9 / IMCR9 */ 769 { 0, 0, 0, CMT_CMTI, 0, 0, USB_USI0,0 } }, 770 { 0xa40800a8, 0xa40800e8, 8, /* IMR10 / IMCR10 */ 771 { 0, DMAC1B_DADERR,DMAC1B_DEI5,DMAC1B_DEI4,0,RTC_ATI,RTC_PRI,RTC_CUI } }, 772 { 0xa40800ac, 0xa40800ec, 8, /* IMR11 / IMCR11 */ 773 { 0,_2DG_CEI,_2DG_INI,_2DG_TRI,0,TPU_TPUI,0,TSIF_TSIFI } }, 774 { 0xa40800b0, 0xa40800f0, 8, /* IMR12 / IMCR12 */ 775 { 0,0,0,0,0,0,0,ATAPI_ATAPII } }, 776 { 0xa4140044, 0xa4140064, 8, /* INTMSK00 / INTMSKCLR00 */ 777 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } }, 778 }; 779 780 static struct intc_prio_reg prio_registers[] __initdata = { 781 { 0xa4080000, 0, 16, 4, /* IPRA */ { TMU0_TUNI0, TMU0_TUNI1, TMU0_TUNI2, IRDA_IRDAI } }, 782 { 0xa4080004, 0, 16, 4, /* IPRB */ { VEU2H1_VEU2HI, LCDC_LCDCI, DMAC1A, 0} }, 783 { 0xa4080008, 0, 16, 4, /* IPRC */ { TMU1_TUNI0, TMU1_TUNI1, TMU1_TUNI2, 0} }, 784 { 0xa408000c, 0, 16, 4, /* IPRD */ { } }, 785 { 0xa4080010, 0, 16, 4, /* IPRE */ { DMAC0A, VIO, SCIFA_SCIFA0, VPU_VPUI } }, 786 { 0xa4080014, 0, 16, 4, /* IPRF */ { KEYSC_KEYI, DMAC0B, USB_USI0, CMT_CMTI } }, 787 { 0xa4080018, 0, 16, 4, /* IPRG */ { SCIF_SCIF0, SCIF_SCIF1, SCIF_SCIF2,0 } }, 788 { 0xa408001c, 0, 16, 4, /* IPRH */ { MSIOF_MSIOFI0,MSIOF_MSIOFI1, FLCTL, I2C } }, 789 { 0xa4080020, 0, 16, 4, /* IPRI */ { SCIFA_SCIFA1,0,TSIF_TSIFI,_2DG } }, 790 { 0xa4080024, 0, 16, 4, /* IPRJ */ { ADC_ADI,0,SIU_SIUI,SDHI1 } }, 791 { 0xa4080028, 0, 16, 4, /* IPRK */ { RTC,DMAC1B,0,SDHI0 } }, 792 { 0xa408002c, 0, 16, 4, /* IPRL */ { SCIFA_SCIFA2,0,TPU_TPUI,ATAPI_ATAPII } }, 793 { 0xa4140010, 0, 32, 4, /* INTPRI00 */ 794 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } }, 795 }; 796 797 static struct intc_sense_reg sense_registers[] __initdata = { 798 { 0xa414001c, 16, 2, /* ICR1 */ 799 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } }, 800 }; 801 802 static struct intc_mask_reg ack_registers[] __initdata = { 803 { 0xa4140024, 0, 8, /* INTREQ00 */ 804 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } }, 805 }; 806 807 static struct intc_desc intc_desc __initdata = { 808 .name = "sh7723", 809 .force_enable = ENABLED, 810 .force_disable = DISABLED, 811 .hw = INTC_HW_DESC(vectors, groups, mask_registers, 812 prio_registers, sense_registers, ack_registers), 813 }; 814 815 void __init plat_irq_setup(void) 816 { 817 register_intc_controller(&intc_desc); 818 } 819