1 /* 2 * SH7722 Setup 3 * 4 * Copyright (C) 2006 - 2008 Paul Mundt 5 * 6 * This file is subject to the terms and conditions of the GNU General Public 7 * License. See the file "COPYING" in the main directory of this archive 8 * for more details. 9 */ 10 #include <linux/init.h> 11 #include <linux/mm.h> 12 #include <linux/platform_device.h> 13 #include <linux/serial.h> 14 #include <linux/serial_sci.h> 15 #include <linux/sh_dma.h> 16 #include <linux/sh_timer.h> 17 #include <linux/sh_intc.h> 18 #include <linux/uio_driver.h> 19 #include <linux/usb/m66592.h> 20 21 #include <asm/clock.h> 22 #include <asm/mmzone.h> 23 #include <asm/siu.h> 24 25 #include <cpu/dma-register.h> 26 #include <cpu/sh7722.h> 27 #include <cpu/serial.h> 28 29 static const struct sh_dmae_slave_config sh7722_dmae_slaves[] = { 30 { 31 .slave_id = SHDMA_SLAVE_SCIF0_TX, 32 .addr = 0xffe0000c, 33 .chcr = DM_FIX | SM_INC | RS_ERS | TS_INDEX2VAL(XMIT_SZ_8BIT), 34 .mid_rid = 0x21, 35 }, { 36 .slave_id = SHDMA_SLAVE_SCIF0_RX, 37 .addr = 0xffe00014, 38 .chcr = DM_INC | SM_FIX | RS_ERS | TS_INDEX2VAL(XMIT_SZ_8BIT), 39 .mid_rid = 0x22, 40 }, { 41 .slave_id = SHDMA_SLAVE_SCIF1_TX, 42 .addr = 0xffe1000c, 43 .chcr = DM_FIX | SM_INC | RS_ERS | TS_INDEX2VAL(XMIT_SZ_8BIT), 44 .mid_rid = 0x25, 45 }, { 46 .slave_id = SHDMA_SLAVE_SCIF1_RX, 47 .addr = 0xffe10014, 48 .chcr = DM_INC | SM_FIX | RS_ERS | TS_INDEX2VAL(XMIT_SZ_8BIT), 49 .mid_rid = 0x26, 50 }, { 51 .slave_id = SHDMA_SLAVE_SCIF2_TX, 52 .addr = 0xffe2000c, 53 .chcr = DM_FIX | SM_INC | RS_ERS | TS_INDEX2VAL(XMIT_SZ_8BIT), 54 .mid_rid = 0x29, 55 }, { 56 .slave_id = SHDMA_SLAVE_SCIF2_RX, 57 .addr = 0xffe20014, 58 .chcr = DM_INC | SM_FIX | RS_ERS | TS_INDEX2VAL(XMIT_SZ_8BIT), 59 .mid_rid = 0x2a, 60 }, { 61 .slave_id = SHDMA_SLAVE_SIUA_TX, 62 .addr = 0xa454c098, 63 .chcr = DM_FIX | SM_INC | RS_ERS | TS_INDEX2VAL(XMIT_SZ_32BIT), 64 .mid_rid = 0xb1, 65 }, { 66 .slave_id = SHDMA_SLAVE_SIUA_RX, 67 .addr = 0xa454c090, 68 .chcr = DM_INC | SM_FIX | RS_ERS | TS_INDEX2VAL(XMIT_SZ_32BIT), 69 .mid_rid = 0xb2, 70 }, { 71 .slave_id = SHDMA_SLAVE_SIUB_TX, 72 .addr = 0xa454c09c, 73 .chcr = DM_FIX | SM_INC | RS_ERS | TS_INDEX2VAL(XMIT_SZ_32BIT), 74 .mid_rid = 0xb5, 75 }, { 76 .slave_id = SHDMA_SLAVE_SIUB_RX, 77 .addr = 0xa454c094, 78 .chcr = DM_INC | SM_FIX | RS_ERS | TS_INDEX2VAL(XMIT_SZ_32BIT), 79 .mid_rid = 0xb6, 80 }, { 81 .slave_id = SHDMA_SLAVE_SDHI0_TX, 82 .addr = 0x04ce0030, 83 .chcr = DM_FIX | SM_INC | RS_ERS | TS_INDEX2VAL(XMIT_SZ_16BIT), 84 .mid_rid = 0xc1, 85 }, { 86 .slave_id = SHDMA_SLAVE_SDHI0_RX, 87 .addr = 0x04ce0030, 88 .chcr = DM_INC | SM_FIX | RS_ERS | TS_INDEX2VAL(XMIT_SZ_16BIT), 89 .mid_rid = 0xc2, 90 }, 91 }; 92 93 static const struct sh_dmae_channel sh7722_dmae_channels[] = { 94 { 95 .offset = 0, 96 .dmars = 0, 97 .dmars_bit = 0, 98 }, { 99 .offset = 0x10, 100 .dmars = 0, 101 .dmars_bit = 8, 102 }, { 103 .offset = 0x20, 104 .dmars = 4, 105 .dmars_bit = 0, 106 }, { 107 .offset = 0x30, 108 .dmars = 4, 109 .dmars_bit = 8, 110 }, { 111 .offset = 0x50, 112 .dmars = 8, 113 .dmars_bit = 0, 114 }, { 115 .offset = 0x60, 116 .dmars = 8, 117 .dmars_bit = 8, 118 } 119 }; 120 121 static const unsigned int ts_shift[] = TS_SHIFT; 122 123 static struct sh_dmae_pdata dma_platform_data = { 124 .slave = sh7722_dmae_slaves, 125 .slave_num = ARRAY_SIZE(sh7722_dmae_slaves), 126 .channel = sh7722_dmae_channels, 127 .channel_num = ARRAY_SIZE(sh7722_dmae_channels), 128 .ts_low_shift = CHCR_TS_LOW_SHIFT, 129 .ts_low_mask = CHCR_TS_LOW_MASK, 130 .ts_high_shift = CHCR_TS_HIGH_SHIFT, 131 .ts_high_mask = CHCR_TS_HIGH_MASK, 132 .ts_shift = ts_shift, 133 .ts_shift_num = ARRAY_SIZE(ts_shift), 134 .dmaor_init = DMAOR_INIT, 135 }; 136 137 static struct resource sh7722_dmae_resources[] = { 138 [0] = { 139 /* Channel registers and DMAOR */ 140 .start = 0xfe008020, 141 .end = 0xfe00808f, 142 .flags = IORESOURCE_MEM, 143 }, 144 [1] = { 145 /* DMARSx */ 146 .start = 0xfe009000, 147 .end = 0xfe00900b, 148 .flags = IORESOURCE_MEM, 149 }, 150 { 151 .name = "error_irq", 152 .start = evt2irq(0xbc0), 153 .end = evt2irq(0xbc0), 154 .flags = IORESOURCE_IRQ, 155 }, 156 { 157 /* IRQ for channels 0-3 */ 158 .start = evt2irq(0x800), 159 .end = evt2irq(0x860), 160 .flags = IORESOURCE_IRQ, 161 }, 162 { 163 /* IRQ for channels 4-5 */ 164 .start = evt2irq(0xb80), 165 .end = evt2irq(0xba0), 166 .flags = IORESOURCE_IRQ, 167 }, 168 }; 169 170 struct platform_device dma_device = { 171 .name = "sh-dma-engine", 172 .id = -1, 173 .resource = sh7722_dmae_resources, 174 .num_resources = ARRAY_SIZE(sh7722_dmae_resources), 175 .dev = { 176 .platform_data = &dma_platform_data, 177 }, 178 }; 179 180 /* Serial */ 181 static struct plat_sci_port scif0_platform_data = { 182 .scscr = SCSCR_REIE, 183 .type = PORT_SCIF, 184 .ops = &sh7722_sci_port_ops, 185 .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE, 186 }; 187 188 static struct resource scif0_resources[] = { 189 DEFINE_RES_MEM(0xffe00000, 0x100), 190 DEFINE_RES_IRQ(evt2irq(0xc00)), 191 }; 192 193 static struct platform_device scif0_device = { 194 .name = "sh-sci", 195 .id = 0, 196 .resource = scif0_resources, 197 .num_resources = ARRAY_SIZE(scif0_resources), 198 .dev = { 199 .platform_data = &scif0_platform_data, 200 }, 201 }; 202 203 static struct plat_sci_port scif1_platform_data = { 204 .scscr = SCSCR_REIE, 205 .type = PORT_SCIF, 206 .ops = &sh7722_sci_port_ops, 207 .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE, 208 }; 209 210 static struct resource scif1_resources[] = { 211 DEFINE_RES_MEM(0xffe10000, 0x100), 212 DEFINE_RES_IRQ(evt2irq(0xc20)), 213 }; 214 215 static struct platform_device scif1_device = { 216 .name = "sh-sci", 217 .id = 1, 218 .resource = scif1_resources, 219 .num_resources = ARRAY_SIZE(scif1_resources), 220 .dev = { 221 .platform_data = &scif1_platform_data, 222 }, 223 }; 224 225 static struct plat_sci_port scif2_platform_data = { 226 .scscr = SCSCR_REIE, 227 .type = PORT_SCIF, 228 .ops = &sh7722_sci_port_ops, 229 .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE, 230 }; 231 232 static struct resource scif2_resources[] = { 233 DEFINE_RES_MEM(0xffe20000, 0x100), 234 DEFINE_RES_IRQ(evt2irq(0xc40)), 235 }; 236 237 static struct platform_device scif2_device = { 238 .name = "sh-sci", 239 .id = 2, 240 .resource = scif2_resources, 241 .num_resources = ARRAY_SIZE(scif2_resources), 242 .dev = { 243 .platform_data = &scif2_platform_data, 244 }, 245 }; 246 247 static struct resource rtc_resources[] = { 248 [0] = { 249 .start = 0xa465fec0, 250 .end = 0xa465fec0 + 0x58 - 1, 251 .flags = IORESOURCE_IO, 252 }, 253 [1] = { 254 /* Period IRQ */ 255 .start = evt2irq(0x7a0), 256 .flags = IORESOURCE_IRQ, 257 }, 258 [2] = { 259 /* Carry IRQ */ 260 .start = evt2irq(0x7c0), 261 .flags = IORESOURCE_IRQ, 262 }, 263 [3] = { 264 /* Alarm IRQ */ 265 .start = evt2irq(0x780), 266 .flags = IORESOURCE_IRQ, 267 }, 268 }; 269 270 static struct platform_device rtc_device = { 271 .name = "sh-rtc", 272 .id = -1, 273 .num_resources = ARRAY_SIZE(rtc_resources), 274 .resource = rtc_resources, 275 }; 276 277 static struct m66592_platdata usbf_platdata = { 278 .on_chip = 1, 279 }; 280 281 static struct resource usbf_resources[] = { 282 [0] = { 283 .name = "USBF", 284 .start = 0x04480000, 285 .end = 0x044800FF, 286 .flags = IORESOURCE_MEM, 287 }, 288 [1] = { 289 .start = evt2irq(0xa20), 290 .end = evt2irq(0xa20), 291 .flags = IORESOURCE_IRQ, 292 }, 293 }; 294 295 static struct platform_device usbf_device = { 296 .name = "m66592_udc", 297 .id = 0, /* "usbf0" clock */ 298 .dev = { 299 .dma_mask = NULL, 300 .coherent_dma_mask = 0xffffffff, 301 .platform_data = &usbf_platdata, 302 }, 303 .num_resources = ARRAY_SIZE(usbf_resources), 304 .resource = usbf_resources, 305 }; 306 307 static struct resource iic_resources[] = { 308 [0] = { 309 .name = "IIC", 310 .start = 0x04470000, 311 .end = 0x04470017, 312 .flags = IORESOURCE_MEM, 313 }, 314 [1] = { 315 .start = evt2irq(0xe00), 316 .end = evt2irq(0xe60), 317 .flags = IORESOURCE_IRQ, 318 }, 319 }; 320 321 static struct platform_device iic_device = { 322 .name = "i2c-sh_mobile", 323 .id = 0, /* "i2c0" clock */ 324 .num_resources = ARRAY_SIZE(iic_resources), 325 .resource = iic_resources, 326 }; 327 328 static struct uio_info vpu_platform_data = { 329 .name = "VPU4", 330 .version = "0", 331 .irq = evt2irq(0x980), 332 }; 333 334 static struct resource vpu_resources[] = { 335 [0] = { 336 .name = "VPU", 337 .start = 0xfe900000, 338 .end = 0xfe9022eb, 339 .flags = IORESOURCE_MEM, 340 }, 341 [1] = { 342 /* place holder for contiguous memory */ 343 }, 344 }; 345 346 static struct platform_device vpu_device = { 347 .name = "uio_pdrv_genirq", 348 .id = 0, 349 .dev = { 350 .platform_data = &vpu_platform_data, 351 }, 352 .resource = vpu_resources, 353 .num_resources = ARRAY_SIZE(vpu_resources), 354 }; 355 356 static struct uio_info veu_platform_data = { 357 .name = "VEU", 358 .version = "0", 359 .irq = evt2irq(0x8c0), 360 }; 361 362 static struct resource veu_resources[] = { 363 [0] = { 364 .name = "VEU", 365 .start = 0xfe920000, 366 .end = 0xfe9200b7, 367 .flags = IORESOURCE_MEM, 368 }, 369 [1] = { 370 /* place holder for contiguous memory */ 371 }, 372 }; 373 374 static struct platform_device veu_device = { 375 .name = "uio_pdrv_genirq", 376 .id = 1, 377 .dev = { 378 .platform_data = &veu_platform_data, 379 }, 380 .resource = veu_resources, 381 .num_resources = ARRAY_SIZE(veu_resources), 382 }; 383 384 static struct uio_info jpu_platform_data = { 385 .name = "JPU", 386 .version = "0", 387 .irq = evt2irq(0x560), 388 }; 389 390 static struct resource jpu_resources[] = { 391 [0] = { 392 .name = "JPU", 393 .start = 0xfea00000, 394 .end = 0xfea102d3, 395 .flags = IORESOURCE_MEM, 396 }, 397 [1] = { 398 /* place holder for contiguous memory */ 399 }, 400 }; 401 402 static struct platform_device jpu_device = { 403 .name = "uio_pdrv_genirq", 404 .id = 2, 405 .dev = { 406 .platform_data = &jpu_platform_data, 407 }, 408 .resource = jpu_resources, 409 .num_resources = ARRAY_SIZE(jpu_resources), 410 }; 411 412 static struct sh_timer_config cmt_platform_data = { 413 .channels_mask = 0x20, 414 }; 415 416 static struct resource cmt_resources[] = { 417 DEFINE_RES_MEM(0x044a0000, 0x70), 418 DEFINE_RES_IRQ(evt2irq(0xf00)), 419 }; 420 421 static struct platform_device cmt_device = { 422 .name = "sh-cmt-32", 423 .id = 0, 424 .dev = { 425 .platform_data = &cmt_platform_data, 426 }, 427 .resource = cmt_resources, 428 .num_resources = ARRAY_SIZE(cmt_resources), 429 }; 430 431 static struct sh_timer_config tmu0_platform_data = { 432 .channels_mask = 7, 433 }; 434 435 static struct resource tmu0_resources[] = { 436 DEFINE_RES_MEM(0xffd80000, 0x2c), 437 DEFINE_RES_IRQ(evt2irq(0x400)), 438 DEFINE_RES_IRQ(evt2irq(0x420)), 439 DEFINE_RES_IRQ(evt2irq(0x440)), 440 }; 441 442 static struct platform_device tmu0_device = { 443 .name = "sh-tmu", 444 .id = 0, 445 .dev = { 446 .platform_data = &tmu0_platform_data, 447 }, 448 .resource = tmu0_resources, 449 .num_resources = ARRAY_SIZE(tmu0_resources), 450 }; 451 452 static struct siu_platform siu_platform_data = { 453 .dma_slave_tx_a = SHDMA_SLAVE_SIUA_TX, 454 .dma_slave_rx_a = SHDMA_SLAVE_SIUA_RX, 455 .dma_slave_tx_b = SHDMA_SLAVE_SIUB_TX, 456 .dma_slave_rx_b = SHDMA_SLAVE_SIUB_RX, 457 }; 458 459 static struct resource siu_resources[] = { 460 [0] = { 461 .start = 0xa4540000, 462 .end = 0xa454c10f, 463 .flags = IORESOURCE_MEM, 464 }, 465 [1] = { 466 .start = evt2irq(0xf80), 467 .flags = IORESOURCE_IRQ, 468 }, 469 }; 470 471 static struct platform_device siu_device = { 472 .name = "siu-pcm-audio", 473 .id = -1, 474 .dev = { 475 .platform_data = &siu_platform_data, 476 }, 477 .resource = siu_resources, 478 .num_resources = ARRAY_SIZE(siu_resources), 479 }; 480 481 static struct platform_device *sh7722_devices[] __initdata = { 482 &scif0_device, 483 &scif1_device, 484 &scif2_device, 485 &cmt_device, 486 &tmu0_device, 487 &rtc_device, 488 &usbf_device, 489 &iic_device, 490 &vpu_device, 491 &veu_device, 492 &jpu_device, 493 &siu_device, 494 &dma_device, 495 }; 496 497 static int __init sh7722_devices_setup(void) 498 { 499 platform_resource_setup_memory(&vpu_device, "vpu", 1 << 20); 500 platform_resource_setup_memory(&veu_device, "veu", 2 << 20); 501 platform_resource_setup_memory(&jpu_device, "jpu", 2 << 20); 502 503 return platform_add_devices(sh7722_devices, 504 ARRAY_SIZE(sh7722_devices)); 505 } 506 arch_initcall(sh7722_devices_setup); 507 508 static struct platform_device *sh7722_early_devices[] __initdata = { 509 &scif0_device, 510 &scif1_device, 511 &scif2_device, 512 &cmt_device, 513 &tmu0_device, 514 }; 515 516 void __init plat_early_device_setup(void) 517 { 518 early_platform_add_devices(sh7722_early_devices, 519 ARRAY_SIZE(sh7722_early_devices)); 520 } 521 522 enum { 523 UNUSED=0, 524 ENABLED, 525 DISABLED, 526 527 /* interrupt sources */ 528 IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7, 529 HUDI, 530 SIM_ERI, SIM_RXI, SIM_TXI, SIM_TEI, 531 RTC_ATI, RTC_PRI, RTC_CUI, 532 DMAC0, DMAC1, DMAC2, DMAC3, 533 VIO_CEUI, VIO_BEUI, VIO_VEUI, VOU, 534 VPU, TPU, 535 USB_USBI0, USB_USBI1, 536 DMAC4, DMAC5, DMAC_DADERR, 537 KEYSC, 538 SCIF0, SCIF1, SCIF2, SIOF0, SIOF1, SIO, 539 FLCTL_FLSTEI, FLCTL_FLENDI, FLCTL_FLTREQ0I, FLCTL_FLTREQ1I, 540 I2C_ALI, I2C_TACKI, I2C_WAITI, I2C_DTEI, 541 CMT, TSIF, SIU, TWODG, 542 TMU0, TMU1, TMU2, 543 IRDA, JPU, LCDC, 544 545 /* interrupt groups */ 546 SIM, RTC, DMAC0123, VIOVOU, USB, DMAC45, FLCTL, I2C, SDHI, 547 }; 548 549 static struct intc_vect vectors[] __initdata = { 550 INTC_VECT(IRQ0, 0x600), INTC_VECT(IRQ1, 0x620), 551 INTC_VECT(IRQ2, 0x640), INTC_VECT(IRQ3, 0x660), 552 INTC_VECT(IRQ4, 0x680), INTC_VECT(IRQ5, 0x6a0), 553 INTC_VECT(IRQ6, 0x6c0), INTC_VECT(IRQ7, 0x6e0), 554 INTC_VECT(SIM_ERI, 0x700), INTC_VECT(SIM_RXI, 0x720), 555 INTC_VECT(SIM_TXI, 0x740), INTC_VECT(SIM_TEI, 0x760), 556 INTC_VECT(RTC_ATI, 0x780), INTC_VECT(RTC_PRI, 0x7a0), 557 INTC_VECT(RTC_CUI, 0x7c0), 558 INTC_VECT(DMAC0, 0x800), INTC_VECT(DMAC1, 0x820), 559 INTC_VECT(DMAC2, 0x840), INTC_VECT(DMAC3, 0x860), 560 INTC_VECT(VIO_CEUI, 0x880), INTC_VECT(VIO_BEUI, 0x8a0), 561 INTC_VECT(VIO_VEUI, 0x8c0), INTC_VECT(VOU, 0x8e0), 562 INTC_VECT(VPU, 0x980), INTC_VECT(TPU, 0x9a0), 563 INTC_VECT(USB_USBI0, 0xa20), INTC_VECT(USB_USBI1, 0xa40), 564 INTC_VECT(DMAC4, 0xb80), INTC_VECT(DMAC5, 0xba0), 565 INTC_VECT(DMAC_DADERR, 0xbc0), INTC_VECT(KEYSC, 0xbe0), 566 INTC_VECT(SCIF0, 0xc00), INTC_VECT(SCIF1, 0xc20), 567 INTC_VECT(SCIF2, 0xc40), INTC_VECT(SIOF0, 0xc80), 568 INTC_VECT(SIOF1, 0xca0), INTC_VECT(SIO, 0xd00), 569 INTC_VECT(FLCTL_FLSTEI, 0xd80), INTC_VECT(FLCTL_FLENDI, 0xda0), 570 INTC_VECT(FLCTL_FLTREQ0I, 0xdc0), INTC_VECT(FLCTL_FLTREQ1I, 0xde0), 571 INTC_VECT(I2C_ALI, 0xe00), INTC_VECT(I2C_TACKI, 0xe20), 572 INTC_VECT(I2C_WAITI, 0xe40), INTC_VECT(I2C_DTEI, 0xe60), 573 INTC_VECT(SDHI, 0xe80), INTC_VECT(SDHI, 0xea0), 574 INTC_VECT(SDHI, 0xec0), INTC_VECT(SDHI, 0xee0), 575 INTC_VECT(CMT, 0xf00), INTC_VECT(TSIF, 0xf20), 576 INTC_VECT(SIU, 0xf80), INTC_VECT(TWODG, 0xfa0), 577 INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420), 578 INTC_VECT(TMU2, 0x440), INTC_VECT(IRDA, 0x480), 579 INTC_VECT(JPU, 0x560), INTC_VECT(LCDC, 0x580), 580 }; 581 582 static struct intc_group groups[] __initdata = { 583 INTC_GROUP(SIM, SIM_ERI, SIM_RXI, SIM_TXI, SIM_TEI), 584 INTC_GROUP(RTC, RTC_ATI, RTC_PRI, RTC_CUI), 585 INTC_GROUP(DMAC0123, DMAC0, DMAC1, DMAC2, DMAC3), 586 INTC_GROUP(VIOVOU, VIO_CEUI, VIO_BEUI, VIO_VEUI, VOU), 587 INTC_GROUP(USB, USB_USBI0, USB_USBI1), 588 INTC_GROUP(DMAC45, DMAC4, DMAC5, DMAC_DADERR), 589 INTC_GROUP(FLCTL, FLCTL_FLSTEI, FLCTL_FLENDI, 590 FLCTL_FLTREQ0I, FLCTL_FLTREQ1I), 591 INTC_GROUP(I2C, I2C_ALI, I2C_TACKI, I2C_WAITI, I2C_DTEI), 592 }; 593 594 static struct intc_mask_reg mask_registers[] __initdata = { 595 { 0xa4080080, 0xa40800c0, 8, /* IMR0 / IMCR0 */ 596 { } }, 597 { 0xa4080084, 0xa40800c4, 8, /* IMR1 / IMCR1 */ 598 { VOU, VIO_VEUI, VIO_BEUI, VIO_CEUI, DMAC3, DMAC2, DMAC1, DMAC0 } }, 599 { 0xa4080088, 0xa40800c8, 8, /* IMR2 / IMCR2 */ 600 { 0, 0, 0, VPU, } }, 601 { 0xa408008c, 0xa40800cc, 8, /* IMR3 / IMCR3 */ 602 { SIM_TEI, SIM_TXI, SIM_RXI, SIM_ERI, 0, 0, 0, IRDA } }, 603 { 0xa4080090, 0xa40800d0, 8, /* IMR4 / IMCR4 */ 604 { 0, TMU2, TMU1, TMU0, JPU, 0, 0, LCDC } }, 605 { 0xa4080094, 0xa40800d4, 8, /* IMR5 / IMCR5 */ 606 { KEYSC, DMAC_DADERR, DMAC5, DMAC4, 0, SCIF2, SCIF1, SCIF0 } }, 607 { 0xa4080098, 0xa40800d8, 8, /* IMR6 / IMCR6 */ 608 { 0, 0, 0, SIO, 0, 0, SIOF1, SIOF0 } }, 609 { 0xa408009c, 0xa40800dc, 8, /* IMR7 / IMCR7 */ 610 { I2C_DTEI, I2C_WAITI, I2C_TACKI, I2C_ALI, 611 FLCTL_FLTREQ1I, FLCTL_FLTREQ0I, FLCTL_FLENDI, FLCTL_FLSTEI } }, 612 { 0xa40800a0, 0xa40800e0, 8, /* IMR8 / IMCR8 */ 613 { DISABLED, ENABLED, ENABLED, ENABLED, 0, 0, TWODG, SIU } }, 614 { 0xa40800a4, 0xa40800e4, 8, /* IMR9 / IMCR9 */ 615 { 0, 0, 0, CMT, 0, USB_USBI1, USB_USBI0, } }, 616 { 0xa40800a8, 0xa40800e8, 8, /* IMR10 / IMCR10 */ 617 { } }, 618 { 0xa40800ac, 0xa40800ec, 8, /* IMR11 / IMCR11 */ 619 { 0, RTC_CUI, RTC_PRI, RTC_ATI, 0, TPU, 0, TSIF } }, 620 { 0xa4140044, 0xa4140064, 8, /* INTMSK00 / INTMSKCLR00 */ 621 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } }, 622 }; 623 624 static struct intc_prio_reg prio_registers[] __initdata = { 625 { 0xa4080000, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, IRDA } }, 626 { 0xa4080004, 0, 16, 4, /* IPRB */ { JPU, LCDC, SIM } }, 627 { 0xa4080008, 0, 16, 4, /* IPRC */ { } }, 628 { 0xa408000c, 0, 16, 4, /* IPRD */ { } }, 629 { 0xa4080010, 0, 16, 4, /* IPRE */ { DMAC0123, VIOVOU, 0, VPU } }, 630 { 0xa4080014, 0, 16, 4, /* IPRF */ { KEYSC, DMAC45, USB, CMT } }, 631 { 0xa4080018, 0, 16, 4, /* IPRG */ { SCIF0, SCIF1, SCIF2 } }, 632 { 0xa408001c, 0, 16, 4, /* IPRH */ { SIOF0, SIOF1, FLCTL, I2C } }, 633 { 0xa4080020, 0, 16, 4, /* IPRI */ { SIO, 0, TSIF, RTC } }, 634 { 0xa4080024, 0, 16, 4, /* IPRJ */ { 0, 0, SIU } }, 635 { 0xa4080028, 0, 16, 4, /* IPRK */ { 0, 0, 0, SDHI } }, 636 { 0xa408002c, 0, 16, 4, /* IPRL */ { TWODG, 0, TPU } }, 637 { 0xa4140010, 0, 32, 4, /* INTPRI00 */ 638 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } }, 639 }; 640 641 static struct intc_sense_reg sense_registers[] __initdata = { 642 { 0xa414001c, 16, 2, /* ICR1 */ 643 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } }, 644 }; 645 646 static struct intc_mask_reg ack_registers[] __initdata = { 647 { 0xa4140024, 0, 8, /* INTREQ00 */ 648 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } }, 649 }; 650 651 static struct intc_desc intc_desc __initdata = { 652 .name = "sh7722", 653 .force_enable = ENABLED, 654 .force_disable = DISABLED, 655 .hw = INTC_HW_DESC(vectors, groups, mask_registers, 656 prio_registers, sense_registers, ack_registers), 657 }; 658 659 void __init plat_irq_setup(void) 660 { 661 register_intc_controller(&intc_desc); 662 } 663 664 void __init plat_mem_setup(void) 665 { 666 /* Register the URAM space as Node 1 */ 667 setup_bootmem_node(1, 0x055f0000, 0x05610000); 668 } 669