1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * SH7722 Setup 4 * 5 * Copyright (C) 2006 - 2008 Paul Mundt 6 */ 7 #include <linux/init.h> 8 #include <linux/mm.h> 9 #include <linux/platform_device.h> 10 #include <linux/serial.h> 11 #include <linux/serial_sci.h> 12 #include <linux/sh_dma.h> 13 #include <linux/sh_timer.h> 14 #include <linux/sh_intc.h> 15 #include <linux/uio_driver.h> 16 #include <linux/usb/m66592.h> 17 18 #include <asm/clock.h> 19 #include <asm/mmzone.h> 20 #include <asm/siu.h> 21 22 #include <cpu/dma-register.h> 23 #include <cpu/sh7722.h> 24 #include <cpu/serial.h> 25 26 static const struct sh_dmae_slave_config sh7722_dmae_slaves[] = { 27 { 28 .slave_id = SHDMA_SLAVE_SCIF0_TX, 29 .addr = 0xffe0000c, 30 .chcr = DM_FIX | SM_INC | RS_ERS | TS_INDEX2VAL(XMIT_SZ_8BIT), 31 .mid_rid = 0x21, 32 }, { 33 .slave_id = SHDMA_SLAVE_SCIF0_RX, 34 .addr = 0xffe00014, 35 .chcr = DM_INC | SM_FIX | RS_ERS | TS_INDEX2VAL(XMIT_SZ_8BIT), 36 .mid_rid = 0x22, 37 }, { 38 .slave_id = SHDMA_SLAVE_SCIF1_TX, 39 .addr = 0xffe1000c, 40 .chcr = DM_FIX | SM_INC | RS_ERS | TS_INDEX2VAL(XMIT_SZ_8BIT), 41 .mid_rid = 0x25, 42 }, { 43 .slave_id = SHDMA_SLAVE_SCIF1_RX, 44 .addr = 0xffe10014, 45 .chcr = DM_INC | SM_FIX | RS_ERS | TS_INDEX2VAL(XMIT_SZ_8BIT), 46 .mid_rid = 0x26, 47 }, { 48 .slave_id = SHDMA_SLAVE_SCIF2_TX, 49 .addr = 0xffe2000c, 50 .chcr = DM_FIX | SM_INC | RS_ERS | TS_INDEX2VAL(XMIT_SZ_8BIT), 51 .mid_rid = 0x29, 52 }, { 53 .slave_id = SHDMA_SLAVE_SCIF2_RX, 54 .addr = 0xffe20014, 55 .chcr = DM_INC | SM_FIX | RS_ERS | TS_INDEX2VAL(XMIT_SZ_8BIT), 56 .mid_rid = 0x2a, 57 }, { 58 .slave_id = SHDMA_SLAVE_SIUA_TX, 59 .addr = 0xa454c098, 60 .chcr = DM_FIX | SM_INC | RS_ERS | TS_INDEX2VAL(XMIT_SZ_32BIT), 61 .mid_rid = 0xb1, 62 }, { 63 .slave_id = SHDMA_SLAVE_SIUA_RX, 64 .addr = 0xa454c090, 65 .chcr = DM_INC | SM_FIX | RS_ERS | TS_INDEX2VAL(XMIT_SZ_32BIT), 66 .mid_rid = 0xb2, 67 }, { 68 .slave_id = SHDMA_SLAVE_SIUB_TX, 69 .addr = 0xa454c09c, 70 .chcr = DM_FIX | SM_INC | RS_ERS | TS_INDEX2VAL(XMIT_SZ_32BIT), 71 .mid_rid = 0xb5, 72 }, { 73 .slave_id = SHDMA_SLAVE_SIUB_RX, 74 .addr = 0xa454c094, 75 .chcr = DM_INC | SM_FIX | RS_ERS | TS_INDEX2VAL(XMIT_SZ_32BIT), 76 .mid_rid = 0xb6, 77 }, { 78 .slave_id = SHDMA_SLAVE_SDHI0_TX, 79 .addr = 0x04ce0030, 80 .chcr = DM_FIX | SM_INC | RS_ERS | TS_INDEX2VAL(XMIT_SZ_16BIT), 81 .mid_rid = 0xc1, 82 }, { 83 .slave_id = SHDMA_SLAVE_SDHI0_RX, 84 .addr = 0x04ce0030, 85 .chcr = DM_INC | SM_FIX | RS_ERS | TS_INDEX2VAL(XMIT_SZ_16BIT), 86 .mid_rid = 0xc2, 87 }, 88 }; 89 90 static const struct sh_dmae_channel sh7722_dmae_channels[] = { 91 { 92 .offset = 0, 93 .dmars = 0, 94 .dmars_bit = 0, 95 }, { 96 .offset = 0x10, 97 .dmars = 0, 98 .dmars_bit = 8, 99 }, { 100 .offset = 0x20, 101 .dmars = 4, 102 .dmars_bit = 0, 103 }, { 104 .offset = 0x30, 105 .dmars = 4, 106 .dmars_bit = 8, 107 }, { 108 .offset = 0x50, 109 .dmars = 8, 110 .dmars_bit = 0, 111 }, { 112 .offset = 0x60, 113 .dmars = 8, 114 .dmars_bit = 8, 115 } 116 }; 117 118 static const unsigned int ts_shift[] = TS_SHIFT; 119 120 static struct sh_dmae_pdata dma_platform_data = { 121 .slave = sh7722_dmae_slaves, 122 .slave_num = ARRAY_SIZE(sh7722_dmae_slaves), 123 .channel = sh7722_dmae_channels, 124 .channel_num = ARRAY_SIZE(sh7722_dmae_channels), 125 .ts_low_shift = CHCR_TS_LOW_SHIFT, 126 .ts_low_mask = CHCR_TS_LOW_MASK, 127 .ts_high_shift = CHCR_TS_HIGH_SHIFT, 128 .ts_high_mask = CHCR_TS_HIGH_MASK, 129 .ts_shift = ts_shift, 130 .ts_shift_num = ARRAY_SIZE(ts_shift), 131 .dmaor_init = DMAOR_INIT, 132 }; 133 134 static struct resource sh7722_dmae_resources[] = { 135 [0] = { 136 /* Channel registers and DMAOR */ 137 .start = 0xfe008020, 138 .end = 0xfe00808f, 139 .flags = IORESOURCE_MEM, 140 }, 141 [1] = { 142 /* DMARSx */ 143 .start = 0xfe009000, 144 .end = 0xfe00900b, 145 .flags = IORESOURCE_MEM, 146 }, 147 { 148 .name = "error_irq", 149 .start = evt2irq(0xbc0), 150 .end = evt2irq(0xbc0), 151 .flags = IORESOURCE_IRQ, 152 }, 153 { 154 /* IRQ for channels 0-3 */ 155 .start = evt2irq(0x800), 156 .end = evt2irq(0x860), 157 .flags = IORESOURCE_IRQ, 158 }, 159 { 160 /* IRQ for channels 4-5 */ 161 .start = evt2irq(0xb80), 162 .end = evt2irq(0xba0), 163 .flags = IORESOURCE_IRQ, 164 }, 165 }; 166 167 struct platform_device dma_device = { 168 .name = "sh-dma-engine", 169 .id = -1, 170 .resource = sh7722_dmae_resources, 171 .num_resources = ARRAY_SIZE(sh7722_dmae_resources), 172 .dev = { 173 .platform_data = &dma_platform_data, 174 }, 175 }; 176 177 /* Serial */ 178 static struct plat_sci_port scif0_platform_data = { 179 .scscr = SCSCR_REIE, 180 .type = PORT_SCIF, 181 .ops = &sh7722_sci_port_ops, 182 .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE, 183 }; 184 185 static struct resource scif0_resources[] = { 186 DEFINE_RES_MEM(0xffe00000, 0x100), 187 DEFINE_RES_IRQ(evt2irq(0xc00)), 188 }; 189 190 static struct platform_device scif0_device = { 191 .name = "sh-sci", 192 .id = 0, 193 .resource = scif0_resources, 194 .num_resources = ARRAY_SIZE(scif0_resources), 195 .dev = { 196 .platform_data = &scif0_platform_data, 197 }, 198 }; 199 200 static struct plat_sci_port scif1_platform_data = { 201 .scscr = SCSCR_REIE, 202 .type = PORT_SCIF, 203 .ops = &sh7722_sci_port_ops, 204 .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE, 205 }; 206 207 static struct resource scif1_resources[] = { 208 DEFINE_RES_MEM(0xffe10000, 0x100), 209 DEFINE_RES_IRQ(evt2irq(0xc20)), 210 }; 211 212 static struct platform_device scif1_device = { 213 .name = "sh-sci", 214 .id = 1, 215 .resource = scif1_resources, 216 .num_resources = ARRAY_SIZE(scif1_resources), 217 .dev = { 218 .platform_data = &scif1_platform_data, 219 }, 220 }; 221 222 static struct plat_sci_port scif2_platform_data = { 223 .scscr = SCSCR_REIE, 224 .type = PORT_SCIF, 225 .ops = &sh7722_sci_port_ops, 226 .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE, 227 }; 228 229 static struct resource scif2_resources[] = { 230 DEFINE_RES_MEM(0xffe20000, 0x100), 231 DEFINE_RES_IRQ(evt2irq(0xc40)), 232 }; 233 234 static struct platform_device scif2_device = { 235 .name = "sh-sci", 236 .id = 2, 237 .resource = scif2_resources, 238 .num_resources = ARRAY_SIZE(scif2_resources), 239 .dev = { 240 .platform_data = &scif2_platform_data, 241 }, 242 }; 243 244 static struct resource rtc_resources[] = { 245 [0] = { 246 .start = 0xa465fec0, 247 .end = 0xa465fec0 + 0x58 - 1, 248 .flags = IORESOURCE_IO, 249 }, 250 [1] = { 251 /* Period IRQ */ 252 .start = evt2irq(0x7a0), 253 .flags = IORESOURCE_IRQ, 254 }, 255 [2] = { 256 /* Carry IRQ */ 257 .start = evt2irq(0x7c0), 258 .flags = IORESOURCE_IRQ, 259 }, 260 [3] = { 261 /* Alarm IRQ */ 262 .start = evt2irq(0x780), 263 .flags = IORESOURCE_IRQ, 264 }, 265 }; 266 267 static struct platform_device rtc_device = { 268 .name = "sh-rtc", 269 .id = -1, 270 .num_resources = ARRAY_SIZE(rtc_resources), 271 .resource = rtc_resources, 272 }; 273 274 static struct m66592_platdata usbf_platdata = { 275 .on_chip = 1, 276 }; 277 278 static struct resource usbf_resources[] = { 279 [0] = { 280 .name = "USBF", 281 .start = 0x04480000, 282 .end = 0x044800FF, 283 .flags = IORESOURCE_MEM, 284 }, 285 [1] = { 286 .start = evt2irq(0xa20), 287 .end = evt2irq(0xa20), 288 .flags = IORESOURCE_IRQ, 289 }, 290 }; 291 292 static struct platform_device usbf_device = { 293 .name = "m66592_udc", 294 .id = 0, /* "usbf0" clock */ 295 .dev = { 296 .dma_mask = NULL, 297 .coherent_dma_mask = 0xffffffff, 298 .platform_data = &usbf_platdata, 299 }, 300 .num_resources = ARRAY_SIZE(usbf_resources), 301 .resource = usbf_resources, 302 }; 303 304 static struct resource iic_resources[] = { 305 [0] = { 306 .name = "IIC", 307 .start = 0x04470000, 308 .end = 0x04470017, 309 .flags = IORESOURCE_MEM, 310 }, 311 [1] = { 312 .start = evt2irq(0xe00), 313 .end = evt2irq(0xe60), 314 .flags = IORESOURCE_IRQ, 315 }, 316 }; 317 318 static struct platform_device iic_device = { 319 .name = "i2c-sh_mobile", 320 .id = 0, /* "i2c0" clock */ 321 .num_resources = ARRAY_SIZE(iic_resources), 322 .resource = iic_resources, 323 }; 324 325 static struct uio_info vpu_platform_data = { 326 .name = "VPU4", 327 .version = "0", 328 .irq = evt2irq(0x980), 329 }; 330 331 static struct resource vpu_resources[] = { 332 [0] = { 333 .name = "VPU", 334 .start = 0xfe900000, 335 .end = 0xfe9022eb, 336 .flags = IORESOURCE_MEM, 337 }, 338 [1] = { 339 /* place holder for contiguous memory */ 340 }, 341 }; 342 343 static struct platform_device vpu_device = { 344 .name = "uio_pdrv_genirq", 345 .id = 0, 346 .dev = { 347 .platform_data = &vpu_platform_data, 348 }, 349 .resource = vpu_resources, 350 .num_resources = ARRAY_SIZE(vpu_resources), 351 }; 352 353 static struct uio_info veu_platform_data = { 354 .name = "VEU", 355 .version = "0", 356 .irq = evt2irq(0x8c0), 357 }; 358 359 static struct resource veu_resources[] = { 360 [0] = { 361 .name = "VEU", 362 .start = 0xfe920000, 363 .end = 0xfe9200b7, 364 .flags = IORESOURCE_MEM, 365 }, 366 [1] = { 367 /* place holder for contiguous memory */ 368 }, 369 }; 370 371 static struct platform_device veu_device = { 372 .name = "uio_pdrv_genirq", 373 .id = 1, 374 .dev = { 375 .platform_data = &veu_platform_data, 376 }, 377 .resource = veu_resources, 378 .num_resources = ARRAY_SIZE(veu_resources), 379 }; 380 381 static struct uio_info jpu_platform_data = { 382 .name = "JPU", 383 .version = "0", 384 .irq = evt2irq(0x560), 385 }; 386 387 static struct resource jpu_resources[] = { 388 [0] = { 389 .name = "JPU", 390 .start = 0xfea00000, 391 .end = 0xfea102d3, 392 .flags = IORESOURCE_MEM, 393 }, 394 [1] = { 395 /* place holder for contiguous memory */ 396 }, 397 }; 398 399 static struct platform_device jpu_device = { 400 .name = "uio_pdrv_genirq", 401 .id = 2, 402 .dev = { 403 .platform_data = &jpu_platform_data, 404 }, 405 .resource = jpu_resources, 406 .num_resources = ARRAY_SIZE(jpu_resources), 407 }; 408 409 static struct sh_timer_config cmt_platform_data = { 410 .channels_mask = 0x20, 411 }; 412 413 static struct resource cmt_resources[] = { 414 DEFINE_RES_MEM(0x044a0000, 0x70), 415 DEFINE_RES_IRQ(evt2irq(0xf00)), 416 }; 417 418 static struct platform_device cmt_device = { 419 .name = "sh-cmt-32", 420 .id = 0, 421 .dev = { 422 .platform_data = &cmt_platform_data, 423 }, 424 .resource = cmt_resources, 425 .num_resources = ARRAY_SIZE(cmt_resources), 426 }; 427 428 static struct sh_timer_config tmu0_platform_data = { 429 .channels_mask = 7, 430 }; 431 432 static struct resource tmu0_resources[] = { 433 DEFINE_RES_MEM(0xffd80000, 0x2c), 434 DEFINE_RES_IRQ(evt2irq(0x400)), 435 DEFINE_RES_IRQ(evt2irq(0x420)), 436 DEFINE_RES_IRQ(evt2irq(0x440)), 437 }; 438 439 static struct platform_device tmu0_device = { 440 .name = "sh-tmu", 441 .id = 0, 442 .dev = { 443 .platform_data = &tmu0_platform_data, 444 }, 445 .resource = tmu0_resources, 446 .num_resources = ARRAY_SIZE(tmu0_resources), 447 }; 448 449 static struct siu_platform siu_platform_data = { 450 .dma_slave_tx_a = SHDMA_SLAVE_SIUA_TX, 451 .dma_slave_rx_a = SHDMA_SLAVE_SIUA_RX, 452 .dma_slave_tx_b = SHDMA_SLAVE_SIUB_TX, 453 .dma_slave_rx_b = SHDMA_SLAVE_SIUB_RX, 454 }; 455 456 static struct resource siu_resources[] = { 457 [0] = { 458 .start = 0xa4540000, 459 .end = 0xa454c10f, 460 .flags = IORESOURCE_MEM, 461 }, 462 [1] = { 463 .start = evt2irq(0xf80), 464 .flags = IORESOURCE_IRQ, 465 }, 466 }; 467 468 static struct platform_device siu_device = { 469 .name = "siu-pcm-audio", 470 .id = -1, 471 .dev = { 472 .platform_data = &siu_platform_data, 473 }, 474 .resource = siu_resources, 475 .num_resources = ARRAY_SIZE(siu_resources), 476 }; 477 478 static struct platform_device *sh7722_devices[] __initdata = { 479 &scif0_device, 480 &scif1_device, 481 &scif2_device, 482 &cmt_device, 483 &tmu0_device, 484 &rtc_device, 485 &usbf_device, 486 &iic_device, 487 &vpu_device, 488 &veu_device, 489 &jpu_device, 490 &siu_device, 491 &dma_device, 492 }; 493 494 static int __init sh7722_devices_setup(void) 495 { 496 platform_resource_setup_memory(&vpu_device, "vpu", 1 << 20); 497 platform_resource_setup_memory(&veu_device, "veu", 2 << 20); 498 platform_resource_setup_memory(&jpu_device, "jpu", 2 << 20); 499 500 return platform_add_devices(sh7722_devices, 501 ARRAY_SIZE(sh7722_devices)); 502 } 503 arch_initcall(sh7722_devices_setup); 504 505 static struct platform_device *sh7722_early_devices[] __initdata = { 506 &scif0_device, 507 &scif1_device, 508 &scif2_device, 509 &cmt_device, 510 &tmu0_device, 511 }; 512 513 void __init plat_early_device_setup(void) 514 { 515 early_platform_add_devices(sh7722_early_devices, 516 ARRAY_SIZE(sh7722_early_devices)); 517 } 518 519 enum { 520 UNUSED=0, 521 ENABLED, 522 DISABLED, 523 524 /* interrupt sources */ 525 IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7, 526 HUDI, 527 SIM_ERI, SIM_RXI, SIM_TXI, SIM_TEI, 528 RTC_ATI, RTC_PRI, RTC_CUI, 529 DMAC0, DMAC1, DMAC2, DMAC3, 530 VIO_CEUI, VIO_BEUI, VIO_VEUI, VOU, 531 VPU, TPU, 532 USB_USBI0, USB_USBI1, 533 DMAC4, DMAC5, DMAC_DADERR, 534 KEYSC, 535 SCIF0, SCIF1, SCIF2, SIOF0, SIOF1, SIO, 536 FLCTL_FLSTEI, FLCTL_FLENDI, FLCTL_FLTREQ0I, FLCTL_FLTREQ1I, 537 I2C_ALI, I2C_TACKI, I2C_WAITI, I2C_DTEI, 538 CMT, TSIF, SIU, TWODG, 539 TMU0, TMU1, TMU2, 540 IRDA, JPU, LCDC, 541 542 /* interrupt groups */ 543 SIM, RTC, DMAC0123, VIOVOU, USB, DMAC45, FLCTL, I2C, SDHI, 544 }; 545 546 static struct intc_vect vectors[] __initdata = { 547 INTC_VECT(IRQ0, 0x600), INTC_VECT(IRQ1, 0x620), 548 INTC_VECT(IRQ2, 0x640), INTC_VECT(IRQ3, 0x660), 549 INTC_VECT(IRQ4, 0x680), INTC_VECT(IRQ5, 0x6a0), 550 INTC_VECT(IRQ6, 0x6c0), INTC_VECT(IRQ7, 0x6e0), 551 INTC_VECT(SIM_ERI, 0x700), INTC_VECT(SIM_RXI, 0x720), 552 INTC_VECT(SIM_TXI, 0x740), INTC_VECT(SIM_TEI, 0x760), 553 INTC_VECT(RTC_ATI, 0x780), INTC_VECT(RTC_PRI, 0x7a0), 554 INTC_VECT(RTC_CUI, 0x7c0), 555 INTC_VECT(DMAC0, 0x800), INTC_VECT(DMAC1, 0x820), 556 INTC_VECT(DMAC2, 0x840), INTC_VECT(DMAC3, 0x860), 557 INTC_VECT(VIO_CEUI, 0x880), INTC_VECT(VIO_BEUI, 0x8a0), 558 INTC_VECT(VIO_VEUI, 0x8c0), INTC_VECT(VOU, 0x8e0), 559 INTC_VECT(VPU, 0x980), INTC_VECT(TPU, 0x9a0), 560 INTC_VECT(USB_USBI0, 0xa20), INTC_VECT(USB_USBI1, 0xa40), 561 INTC_VECT(DMAC4, 0xb80), INTC_VECT(DMAC5, 0xba0), 562 INTC_VECT(DMAC_DADERR, 0xbc0), INTC_VECT(KEYSC, 0xbe0), 563 INTC_VECT(SCIF0, 0xc00), INTC_VECT(SCIF1, 0xc20), 564 INTC_VECT(SCIF2, 0xc40), INTC_VECT(SIOF0, 0xc80), 565 INTC_VECT(SIOF1, 0xca0), INTC_VECT(SIO, 0xd00), 566 INTC_VECT(FLCTL_FLSTEI, 0xd80), INTC_VECT(FLCTL_FLENDI, 0xda0), 567 INTC_VECT(FLCTL_FLTREQ0I, 0xdc0), INTC_VECT(FLCTL_FLTREQ1I, 0xde0), 568 INTC_VECT(I2C_ALI, 0xe00), INTC_VECT(I2C_TACKI, 0xe20), 569 INTC_VECT(I2C_WAITI, 0xe40), INTC_VECT(I2C_DTEI, 0xe60), 570 INTC_VECT(SDHI, 0xe80), INTC_VECT(SDHI, 0xea0), 571 INTC_VECT(SDHI, 0xec0), INTC_VECT(SDHI, 0xee0), 572 INTC_VECT(CMT, 0xf00), INTC_VECT(TSIF, 0xf20), 573 INTC_VECT(SIU, 0xf80), INTC_VECT(TWODG, 0xfa0), 574 INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420), 575 INTC_VECT(TMU2, 0x440), INTC_VECT(IRDA, 0x480), 576 INTC_VECT(JPU, 0x560), INTC_VECT(LCDC, 0x580), 577 }; 578 579 static struct intc_group groups[] __initdata = { 580 INTC_GROUP(SIM, SIM_ERI, SIM_RXI, SIM_TXI, SIM_TEI), 581 INTC_GROUP(RTC, RTC_ATI, RTC_PRI, RTC_CUI), 582 INTC_GROUP(DMAC0123, DMAC0, DMAC1, DMAC2, DMAC3), 583 INTC_GROUP(VIOVOU, VIO_CEUI, VIO_BEUI, VIO_VEUI, VOU), 584 INTC_GROUP(USB, USB_USBI0, USB_USBI1), 585 INTC_GROUP(DMAC45, DMAC4, DMAC5, DMAC_DADERR), 586 INTC_GROUP(FLCTL, FLCTL_FLSTEI, FLCTL_FLENDI, 587 FLCTL_FLTREQ0I, FLCTL_FLTREQ1I), 588 INTC_GROUP(I2C, I2C_ALI, I2C_TACKI, I2C_WAITI, I2C_DTEI), 589 }; 590 591 static struct intc_mask_reg mask_registers[] __initdata = { 592 { 0xa4080080, 0xa40800c0, 8, /* IMR0 / IMCR0 */ 593 { } }, 594 { 0xa4080084, 0xa40800c4, 8, /* IMR1 / IMCR1 */ 595 { VOU, VIO_VEUI, VIO_BEUI, VIO_CEUI, DMAC3, DMAC2, DMAC1, DMAC0 } }, 596 { 0xa4080088, 0xa40800c8, 8, /* IMR2 / IMCR2 */ 597 { 0, 0, 0, VPU, } }, 598 { 0xa408008c, 0xa40800cc, 8, /* IMR3 / IMCR3 */ 599 { SIM_TEI, SIM_TXI, SIM_RXI, SIM_ERI, 0, 0, 0, IRDA } }, 600 { 0xa4080090, 0xa40800d0, 8, /* IMR4 / IMCR4 */ 601 { 0, TMU2, TMU1, TMU0, JPU, 0, 0, LCDC } }, 602 { 0xa4080094, 0xa40800d4, 8, /* IMR5 / IMCR5 */ 603 { KEYSC, DMAC_DADERR, DMAC5, DMAC4, 0, SCIF2, SCIF1, SCIF0 } }, 604 { 0xa4080098, 0xa40800d8, 8, /* IMR6 / IMCR6 */ 605 { 0, 0, 0, SIO, 0, 0, SIOF1, SIOF0 } }, 606 { 0xa408009c, 0xa40800dc, 8, /* IMR7 / IMCR7 */ 607 { I2C_DTEI, I2C_WAITI, I2C_TACKI, I2C_ALI, 608 FLCTL_FLTREQ1I, FLCTL_FLTREQ0I, FLCTL_FLENDI, FLCTL_FLSTEI } }, 609 { 0xa40800a0, 0xa40800e0, 8, /* IMR8 / IMCR8 */ 610 { DISABLED, ENABLED, ENABLED, ENABLED, 0, 0, TWODG, SIU } }, 611 { 0xa40800a4, 0xa40800e4, 8, /* IMR9 / IMCR9 */ 612 { 0, 0, 0, CMT, 0, USB_USBI1, USB_USBI0, } }, 613 { 0xa40800a8, 0xa40800e8, 8, /* IMR10 / IMCR10 */ 614 { } }, 615 { 0xa40800ac, 0xa40800ec, 8, /* IMR11 / IMCR11 */ 616 { 0, RTC_CUI, RTC_PRI, RTC_ATI, 0, TPU, 0, TSIF } }, 617 { 0xa4140044, 0xa4140064, 8, /* INTMSK00 / INTMSKCLR00 */ 618 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } }, 619 }; 620 621 static struct intc_prio_reg prio_registers[] __initdata = { 622 { 0xa4080000, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, IRDA } }, 623 { 0xa4080004, 0, 16, 4, /* IPRB */ { JPU, LCDC, SIM } }, 624 { 0xa4080008, 0, 16, 4, /* IPRC */ { } }, 625 { 0xa408000c, 0, 16, 4, /* IPRD */ { } }, 626 { 0xa4080010, 0, 16, 4, /* IPRE */ { DMAC0123, VIOVOU, 0, VPU } }, 627 { 0xa4080014, 0, 16, 4, /* IPRF */ { KEYSC, DMAC45, USB, CMT } }, 628 { 0xa4080018, 0, 16, 4, /* IPRG */ { SCIF0, SCIF1, SCIF2 } }, 629 { 0xa408001c, 0, 16, 4, /* IPRH */ { SIOF0, SIOF1, FLCTL, I2C } }, 630 { 0xa4080020, 0, 16, 4, /* IPRI */ { SIO, 0, TSIF, RTC } }, 631 { 0xa4080024, 0, 16, 4, /* IPRJ */ { 0, 0, SIU } }, 632 { 0xa4080028, 0, 16, 4, /* IPRK */ { 0, 0, 0, SDHI } }, 633 { 0xa408002c, 0, 16, 4, /* IPRL */ { TWODG, 0, TPU } }, 634 { 0xa4140010, 0, 32, 4, /* INTPRI00 */ 635 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } }, 636 }; 637 638 static struct intc_sense_reg sense_registers[] __initdata = { 639 { 0xa414001c, 16, 2, /* ICR1 */ 640 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } }, 641 }; 642 643 static struct intc_mask_reg ack_registers[] __initdata = { 644 { 0xa4140024, 0, 8, /* INTREQ00 */ 645 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } }, 646 }; 647 648 static struct intc_desc intc_desc __initdata = { 649 .name = "sh7722", 650 .force_enable = ENABLED, 651 .force_disable = DISABLED, 652 .hw = INTC_HW_DESC(vectors, groups, mask_registers, 653 prio_registers, sense_registers, ack_registers), 654 }; 655 656 void __init plat_irq_setup(void) 657 { 658 register_intc_controller(&intc_desc); 659 } 660 661 void __init plat_mem_setup(void) 662 { 663 /* Register the URAM space as Node 1 */ 664 setup_bootmem_node(1, 0x055f0000, 0x05610000); 665 } 666