1 /* 2 * SH7722 Setup 3 * 4 * Copyright (C) 2006 - 2008 Paul Mundt 5 * 6 * This file is subject to the terms and conditions of the GNU General Public 7 * License. See the file "COPYING" in the main directory of this archive 8 * for more details. 9 */ 10 #include <linux/platform_device.h> 11 #include <linux/init.h> 12 #include <linux/serial.h> 13 #include <linux/serial_sci.h> 14 #include <linux/mm.h> 15 #include <linux/uio_driver.h> 16 #include <linux/usb/m66592.h> 17 #include <linux/sh_timer.h> 18 #include <asm/clock.h> 19 #include <asm/mmzone.h> 20 #include <asm/dma-sh.h> 21 #include <asm/siu.h> 22 #include <cpu/sh7722.h> 23 24 static struct sh_dmae_slave_config sh7722_dmae_slaves[] = { 25 { 26 .slave_id = SHDMA_SLAVE_SCIF0_TX, 27 .addr = 0xffe0000c, 28 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT), 29 .mid_rid = 0x21, 30 }, { 31 .slave_id = SHDMA_SLAVE_SCIF0_RX, 32 .addr = 0xffe00014, 33 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT), 34 .mid_rid = 0x22, 35 }, { 36 .slave_id = SHDMA_SLAVE_SCIF1_TX, 37 .addr = 0xffe1000c, 38 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT), 39 .mid_rid = 0x25, 40 }, { 41 .slave_id = SHDMA_SLAVE_SCIF1_RX, 42 .addr = 0xffe10014, 43 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT), 44 .mid_rid = 0x26, 45 }, { 46 .slave_id = SHDMA_SLAVE_SCIF2_TX, 47 .addr = 0xffe2000c, 48 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT), 49 .mid_rid = 0x29, 50 }, { 51 .slave_id = SHDMA_SLAVE_SCIF2_RX, 52 .addr = 0xffe20014, 53 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT), 54 .mid_rid = 0x2a, 55 }, { 56 .slave_id = SHDMA_SLAVE_SIUA_TX, 57 .addr = 0xa454c098, 58 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT), 59 .mid_rid = 0xb1, 60 }, { 61 .slave_id = SHDMA_SLAVE_SIUA_RX, 62 .addr = 0xa454c090, 63 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT), 64 .mid_rid = 0xb2, 65 }, { 66 .slave_id = SHDMA_SLAVE_SIUB_TX, 67 .addr = 0xa454c09c, 68 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT), 69 .mid_rid = 0xb5, 70 }, { 71 .slave_id = SHDMA_SLAVE_SIUB_RX, 72 .addr = 0xa454c094, 73 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT), 74 .mid_rid = 0xb6, 75 }, 76 }; 77 78 static struct sh_dmae_pdata dma_platform_data = { 79 .mode = 0, 80 .config = sh7722_dmae_slaves, 81 .config_num = ARRAY_SIZE(sh7722_dmae_slaves), 82 }; 83 84 struct platform_device dma_device = { 85 .name = "sh-dma-engine", 86 .id = -1, 87 .dev = { 88 .platform_data = &dma_platform_data, 89 }, 90 }; 91 92 /* Serial */ 93 static struct plat_sci_port scif0_platform_data = { 94 .mapbase = 0xffe00000, 95 .flags = UPF_BOOT_AUTOCONF, 96 .type = PORT_SCIF, 97 .irqs = { 80, 80, 80, 80 }, 98 .clk = "scif0", 99 }; 100 101 static struct platform_device scif0_device = { 102 .name = "sh-sci", 103 .id = 0, 104 .dev = { 105 .platform_data = &scif0_platform_data, 106 }, 107 }; 108 109 static struct plat_sci_port scif1_platform_data = { 110 .mapbase = 0xffe10000, 111 .flags = UPF_BOOT_AUTOCONF, 112 .type = PORT_SCIF, 113 .irqs = { 81, 81, 81, 81 }, 114 .clk = "scif1", 115 }; 116 117 static struct platform_device scif1_device = { 118 .name = "sh-sci", 119 .id = 1, 120 .dev = { 121 .platform_data = &scif1_platform_data, 122 }, 123 }; 124 125 static struct plat_sci_port scif2_platform_data = { 126 .mapbase = 0xffe20000, 127 .flags = UPF_BOOT_AUTOCONF, 128 .type = PORT_SCIF, 129 .irqs = { 82, 82, 82, 82 }, 130 .clk = "scif2", 131 }; 132 133 static struct platform_device scif2_device = { 134 .name = "sh-sci", 135 .id = 2, 136 .dev = { 137 .platform_data = &scif2_platform_data, 138 }, 139 }; 140 141 static struct resource rtc_resources[] = { 142 [0] = { 143 .start = 0xa465fec0, 144 .end = 0xa465fec0 + 0x58 - 1, 145 .flags = IORESOURCE_IO, 146 }, 147 [1] = { 148 /* Period IRQ */ 149 .start = 45, 150 .flags = IORESOURCE_IRQ, 151 }, 152 [2] = { 153 /* Carry IRQ */ 154 .start = 46, 155 .flags = IORESOURCE_IRQ, 156 }, 157 [3] = { 158 /* Alarm IRQ */ 159 .start = 44, 160 .flags = IORESOURCE_IRQ, 161 }, 162 }; 163 164 static struct platform_device rtc_device = { 165 .name = "sh-rtc", 166 .id = -1, 167 .num_resources = ARRAY_SIZE(rtc_resources), 168 .resource = rtc_resources, 169 .archdata = { 170 .hwblk_id = HWBLK_RTC, 171 }, 172 }; 173 174 static struct m66592_platdata usbf_platdata = { 175 .on_chip = 1, 176 }; 177 178 static struct resource usbf_resources[] = { 179 [0] = { 180 .name = "USBF", 181 .start = 0x04480000, 182 .end = 0x044800FF, 183 .flags = IORESOURCE_MEM, 184 }, 185 [1] = { 186 .start = 65, 187 .end = 65, 188 .flags = IORESOURCE_IRQ, 189 }, 190 }; 191 192 static struct platform_device usbf_device = { 193 .name = "m66592_udc", 194 .id = 0, /* "usbf0" clock */ 195 .dev = { 196 .dma_mask = NULL, 197 .coherent_dma_mask = 0xffffffff, 198 .platform_data = &usbf_platdata, 199 }, 200 .num_resources = ARRAY_SIZE(usbf_resources), 201 .resource = usbf_resources, 202 .archdata = { 203 .hwblk_id = HWBLK_USBF, 204 }, 205 }; 206 207 static struct resource iic_resources[] = { 208 [0] = { 209 .name = "IIC", 210 .start = 0x04470000, 211 .end = 0x04470017, 212 .flags = IORESOURCE_MEM, 213 }, 214 [1] = { 215 .start = 96, 216 .end = 99, 217 .flags = IORESOURCE_IRQ, 218 }, 219 }; 220 221 static struct platform_device iic_device = { 222 .name = "i2c-sh_mobile", 223 .id = 0, /* "i2c0" clock */ 224 .num_resources = ARRAY_SIZE(iic_resources), 225 .resource = iic_resources, 226 .archdata = { 227 .hwblk_id = HWBLK_IIC, 228 }, 229 }; 230 231 static struct uio_info vpu_platform_data = { 232 .name = "VPU4", 233 .version = "0", 234 .irq = 60, 235 }; 236 237 static struct resource vpu_resources[] = { 238 [0] = { 239 .name = "VPU", 240 .start = 0xfe900000, 241 .end = 0xfe9022eb, 242 .flags = IORESOURCE_MEM, 243 }, 244 [1] = { 245 /* place holder for contiguous memory */ 246 }, 247 }; 248 249 static struct platform_device vpu_device = { 250 .name = "uio_pdrv_genirq", 251 .id = 0, 252 .dev = { 253 .platform_data = &vpu_platform_data, 254 }, 255 .resource = vpu_resources, 256 .num_resources = ARRAY_SIZE(vpu_resources), 257 .archdata = { 258 .hwblk_id = HWBLK_VPU, 259 }, 260 }; 261 262 static struct uio_info veu_platform_data = { 263 .name = "VEU", 264 .version = "0", 265 .irq = 54, 266 }; 267 268 static struct resource veu_resources[] = { 269 [0] = { 270 .name = "VEU", 271 .start = 0xfe920000, 272 .end = 0xfe9200b7, 273 .flags = IORESOURCE_MEM, 274 }, 275 [1] = { 276 /* place holder for contiguous memory */ 277 }, 278 }; 279 280 static struct platform_device veu_device = { 281 .name = "uio_pdrv_genirq", 282 .id = 1, 283 .dev = { 284 .platform_data = &veu_platform_data, 285 }, 286 .resource = veu_resources, 287 .num_resources = ARRAY_SIZE(veu_resources), 288 .archdata = { 289 .hwblk_id = HWBLK_VEU, 290 }, 291 }; 292 293 static struct uio_info jpu_platform_data = { 294 .name = "JPU", 295 .version = "0", 296 .irq = 27, 297 }; 298 299 static struct resource jpu_resources[] = { 300 [0] = { 301 .name = "JPU", 302 .start = 0xfea00000, 303 .end = 0xfea102d3, 304 .flags = IORESOURCE_MEM, 305 }, 306 [1] = { 307 /* place holder for contiguous memory */ 308 }, 309 }; 310 311 static struct platform_device jpu_device = { 312 .name = "uio_pdrv_genirq", 313 .id = 2, 314 .dev = { 315 .platform_data = &jpu_platform_data, 316 }, 317 .resource = jpu_resources, 318 .num_resources = ARRAY_SIZE(jpu_resources), 319 .archdata = { 320 .hwblk_id = HWBLK_JPU, 321 }, 322 }; 323 324 static struct sh_timer_config cmt_platform_data = { 325 .name = "CMT", 326 .channel_offset = 0x60, 327 .timer_bit = 5, 328 .clk = "cmt0", 329 .clockevent_rating = 125, 330 .clocksource_rating = 125, 331 }; 332 333 static struct resource cmt_resources[] = { 334 [0] = { 335 .name = "CMT", 336 .start = 0x044a0060, 337 .end = 0x044a006b, 338 .flags = IORESOURCE_MEM, 339 }, 340 [1] = { 341 .start = 104, 342 .flags = IORESOURCE_IRQ, 343 }, 344 }; 345 346 static struct platform_device cmt_device = { 347 .name = "sh_cmt", 348 .id = 0, 349 .dev = { 350 .platform_data = &cmt_platform_data, 351 }, 352 .resource = cmt_resources, 353 .num_resources = ARRAY_SIZE(cmt_resources), 354 .archdata = { 355 .hwblk_id = HWBLK_CMT, 356 }, 357 }; 358 359 static struct sh_timer_config tmu0_platform_data = { 360 .name = "TMU0", 361 .channel_offset = 0x04, 362 .timer_bit = 0, 363 .clk = "tmu0", 364 .clockevent_rating = 200, 365 }; 366 367 static struct resource tmu0_resources[] = { 368 [0] = { 369 .name = "TMU0", 370 .start = 0xffd80008, 371 .end = 0xffd80013, 372 .flags = IORESOURCE_MEM, 373 }, 374 [1] = { 375 .start = 16, 376 .flags = IORESOURCE_IRQ, 377 }, 378 }; 379 380 static struct platform_device tmu0_device = { 381 .name = "sh_tmu", 382 .id = 0, 383 .dev = { 384 .platform_data = &tmu0_platform_data, 385 }, 386 .resource = tmu0_resources, 387 .num_resources = ARRAY_SIZE(tmu0_resources), 388 .archdata = { 389 .hwblk_id = HWBLK_TMU, 390 }, 391 }; 392 393 static struct sh_timer_config tmu1_platform_data = { 394 .name = "TMU1", 395 .channel_offset = 0x10, 396 .timer_bit = 1, 397 .clk = "tmu0", 398 .clocksource_rating = 200, 399 }; 400 401 static struct resource tmu1_resources[] = { 402 [0] = { 403 .name = "TMU1", 404 .start = 0xffd80014, 405 .end = 0xffd8001f, 406 .flags = IORESOURCE_MEM, 407 }, 408 [1] = { 409 .start = 17, 410 .flags = IORESOURCE_IRQ, 411 }, 412 }; 413 414 static struct platform_device tmu1_device = { 415 .name = "sh_tmu", 416 .id = 1, 417 .dev = { 418 .platform_data = &tmu1_platform_data, 419 }, 420 .resource = tmu1_resources, 421 .num_resources = ARRAY_SIZE(tmu1_resources), 422 .archdata = { 423 .hwblk_id = HWBLK_TMU, 424 }, 425 }; 426 427 static struct sh_timer_config tmu2_platform_data = { 428 .name = "TMU2", 429 .channel_offset = 0x1c, 430 .timer_bit = 2, 431 .clk = "tmu0", 432 }; 433 434 static struct resource tmu2_resources[] = { 435 [0] = { 436 .name = "TMU2", 437 .start = 0xffd80020, 438 .end = 0xffd8002b, 439 .flags = IORESOURCE_MEM, 440 }, 441 [1] = { 442 .start = 18, 443 .flags = IORESOURCE_IRQ, 444 }, 445 }; 446 447 static struct platform_device tmu2_device = { 448 .name = "sh_tmu", 449 .id = 2, 450 .dev = { 451 .platform_data = &tmu2_platform_data, 452 }, 453 .resource = tmu2_resources, 454 .num_resources = ARRAY_SIZE(tmu2_resources), 455 .archdata = { 456 .hwblk_id = HWBLK_TMU, 457 }, 458 }; 459 460 static struct siu_platform siu_platform_data = { 461 .dma_dev = &dma_device.dev, 462 .dma_slave_tx_a = SHDMA_SLAVE_SIUA_TX, 463 .dma_slave_rx_a = SHDMA_SLAVE_SIUA_RX, 464 .dma_slave_tx_b = SHDMA_SLAVE_SIUB_TX, 465 .dma_slave_rx_b = SHDMA_SLAVE_SIUB_RX, 466 }; 467 468 static struct resource siu_resources[] = { 469 [0] = { 470 .start = 0xa4540000, 471 .end = 0xa454c10f, 472 .flags = IORESOURCE_MEM, 473 }, 474 [1] = { 475 .start = 108, 476 .flags = IORESOURCE_IRQ, 477 }, 478 }; 479 480 static struct platform_device siu_device = { 481 .name = "sh_siu", 482 .id = -1, 483 .dev = { 484 .platform_data = &siu_platform_data, 485 }, 486 .resource = siu_resources, 487 .num_resources = ARRAY_SIZE(siu_resources), 488 .archdata = { 489 .hwblk_id = HWBLK_SIU, 490 }, 491 }; 492 493 static struct platform_device *sh7722_devices[] __initdata = { 494 &scif0_device, 495 &scif1_device, 496 &scif2_device, 497 &cmt_device, 498 &tmu0_device, 499 &tmu1_device, 500 &tmu2_device, 501 &rtc_device, 502 &usbf_device, 503 &iic_device, 504 &vpu_device, 505 &veu_device, 506 &jpu_device, 507 &siu_device, 508 &dma_device, 509 }; 510 511 static int __init sh7722_devices_setup(void) 512 { 513 platform_resource_setup_memory(&vpu_device, "vpu", 1 << 20); 514 platform_resource_setup_memory(&veu_device, "veu", 2 << 20); 515 platform_resource_setup_memory(&jpu_device, "jpu", 2 << 20); 516 517 return platform_add_devices(sh7722_devices, 518 ARRAY_SIZE(sh7722_devices)); 519 } 520 arch_initcall(sh7722_devices_setup); 521 522 static struct platform_device *sh7722_early_devices[] __initdata = { 523 &scif0_device, 524 &scif1_device, 525 &scif2_device, 526 &cmt_device, 527 &tmu0_device, 528 &tmu1_device, 529 &tmu2_device, 530 }; 531 532 void __init plat_early_device_setup(void) 533 { 534 early_platform_add_devices(sh7722_early_devices, 535 ARRAY_SIZE(sh7722_early_devices)); 536 } 537 538 enum { 539 UNUSED=0, 540 ENABLED, 541 DISABLED, 542 543 /* interrupt sources */ 544 IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7, 545 HUDI, 546 SIM_ERI, SIM_RXI, SIM_TXI, SIM_TEI, 547 RTC_ATI, RTC_PRI, RTC_CUI, 548 DMAC0, DMAC1, DMAC2, DMAC3, 549 VIO_CEUI, VIO_BEUI, VIO_VEUI, VOU, 550 VPU, TPU, 551 USB_USBI0, USB_USBI1, 552 DMAC4, DMAC5, DMAC_DADERR, 553 KEYSC, 554 SCIF0, SCIF1, SCIF2, SIOF0, SIOF1, SIO, 555 FLCTL_FLSTEI, FLCTL_FLENDI, FLCTL_FLTREQ0I, FLCTL_FLTREQ1I, 556 I2C_ALI, I2C_TACKI, I2C_WAITI, I2C_DTEI, 557 CMT, TSIF, SIU, TWODG, 558 TMU0, TMU1, TMU2, 559 IRDA, JPU, LCDC, 560 561 /* interrupt groups */ 562 SIM, RTC, DMAC0123, VIOVOU, USB, DMAC45, FLCTL, I2C, SDHI, 563 }; 564 565 static struct intc_vect vectors[] __initdata = { 566 INTC_VECT(IRQ0, 0x600), INTC_VECT(IRQ1, 0x620), 567 INTC_VECT(IRQ2, 0x640), INTC_VECT(IRQ3, 0x660), 568 INTC_VECT(IRQ4, 0x680), INTC_VECT(IRQ5, 0x6a0), 569 INTC_VECT(IRQ6, 0x6c0), INTC_VECT(IRQ7, 0x6e0), 570 INTC_VECT(SIM_ERI, 0x700), INTC_VECT(SIM_RXI, 0x720), 571 INTC_VECT(SIM_TXI, 0x740), INTC_VECT(SIM_TEI, 0x760), 572 INTC_VECT(RTC_ATI, 0x780), INTC_VECT(RTC_PRI, 0x7a0), 573 INTC_VECT(RTC_CUI, 0x7c0), 574 INTC_VECT(DMAC0, 0x800), INTC_VECT(DMAC1, 0x820), 575 INTC_VECT(DMAC2, 0x840), INTC_VECT(DMAC3, 0x860), 576 INTC_VECT(VIO_CEUI, 0x880), INTC_VECT(VIO_BEUI, 0x8a0), 577 INTC_VECT(VIO_VEUI, 0x8c0), INTC_VECT(VOU, 0x8e0), 578 INTC_VECT(VPU, 0x980), INTC_VECT(TPU, 0x9a0), 579 INTC_VECT(USB_USBI0, 0xa20), INTC_VECT(USB_USBI1, 0xa40), 580 INTC_VECT(DMAC4, 0xb80), INTC_VECT(DMAC5, 0xba0), 581 INTC_VECT(DMAC_DADERR, 0xbc0), INTC_VECT(KEYSC, 0xbe0), 582 INTC_VECT(SCIF0, 0xc00), INTC_VECT(SCIF1, 0xc20), 583 INTC_VECT(SCIF2, 0xc40), INTC_VECT(SIOF0, 0xc80), 584 INTC_VECT(SIOF1, 0xca0), INTC_VECT(SIO, 0xd00), 585 INTC_VECT(FLCTL_FLSTEI, 0xd80), INTC_VECT(FLCTL_FLENDI, 0xda0), 586 INTC_VECT(FLCTL_FLTREQ0I, 0xdc0), INTC_VECT(FLCTL_FLTREQ1I, 0xde0), 587 INTC_VECT(I2C_ALI, 0xe00), INTC_VECT(I2C_TACKI, 0xe20), 588 INTC_VECT(I2C_WAITI, 0xe40), INTC_VECT(I2C_DTEI, 0xe60), 589 INTC_VECT(SDHI, 0xe80), INTC_VECT(SDHI, 0xea0), 590 INTC_VECT(SDHI, 0xec0), INTC_VECT(SDHI, 0xee0), 591 INTC_VECT(CMT, 0xf00), INTC_VECT(TSIF, 0xf20), 592 INTC_VECT(SIU, 0xf80), INTC_VECT(TWODG, 0xfa0), 593 INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420), 594 INTC_VECT(TMU2, 0x440), INTC_VECT(IRDA, 0x480), 595 INTC_VECT(JPU, 0x560), INTC_VECT(LCDC, 0x580), 596 }; 597 598 static struct intc_group groups[] __initdata = { 599 INTC_GROUP(SIM, SIM_ERI, SIM_RXI, SIM_TXI, SIM_TEI), 600 INTC_GROUP(RTC, RTC_ATI, RTC_PRI, RTC_CUI), 601 INTC_GROUP(DMAC0123, DMAC0, DMAC1, DMAC2, DMAC3), 602 INTC_GROUP(VIOVOU, VIO_CEUI, VIO_BEUI, VIO_VEUI, VOU), 603 INTC_GROUP(USB, USB_USBI0, USB_USBI1), 604 INTC_GROUP(DMAC45, DMAC4, DMAC5, DMAC_DADERR), 605 INTC_GROUP(FLCTL, FLCTL_FLSTEI, FLCTL_FLENDI, 606 FLCTL_FLTREQ0I, FLCTL_FLTREQ1I), 607 INTC_GROUP(I2C, I2C_ALI, I2C_TACKI, I2C_WAITI, I2C_DTEI), 608 }; 609 610 static struct intc_mask_reg mask_registers[] __initdata = { 611 { 0xa4080080, 0xa40800c0, 8, /* IMR0 / IMCR0 */ 612 { } }, 613 { 0xa4080084, 0xa40800c4, 8, /* IMR1 / IMCR1 */ 614 { VOU, VIO_VEUI, VIO_BEUI, VIO_CEUI, DMAC3, DMAC2, DMAC1, DMAC0 } }, 615 { 0xa4080088, 0xa40800c8, 8, /* IMR2 / IMCR2 */ 616 { 0, 0, 0, VPU, } }, 617 { 0xa408008c, 0xa40800cc, 8, /* IMR3 / IMCR3 */ 618 { SIM_TEI, SIM_TXI, SIM_RXI, SIM_ERI, 0, 0, 0, IRDA } }, 619 { 0xa4080090, 0xa40800d0, 8, /* IMR4 / IMCR4 */ 620 { 0, TMU2, TMU1, TMU0, JPU, 0, 0, LCDC } }, 621 { 0xa4080094, 0xa40800d4, 8, /* IMR5 / IMCR5 */ 622 { KEYSC, DMAC_DADERR, DMAC5, DMAC4, 0, SCIF2, SCIF1, SCIF0 } }, 623 { 0xa4080098, 0xa40800d8, 8, /* IMR6 / IMCR6 */ 624 { 0, 0, 0, SIO, 0, 0, SIOF1, SIOF0 } }, 625 { 0xa408009c, 0xa40800dc, 8, /* IMR7 / IMCR7 */ 626 { I2C_DTEI, I2C_WAITI, I2C_TACKI, I2C_ALI, 627 FLCTL_FLTREQ1I, FLCTL_FLTREQ0I, FLCTL_FLENDI, FLCTL_FLSTEI } }, 628 { 0xa40800a0, 0xa40800e0, 8, /* IMR8 / IMCR8 */ 629 { DISABLED, DISABLED, ENABLED, ENABLED, 0, 0, TWODG, SIU } }, 630 { 0xa40800a4, 0xa40800e4, 8, /* IMR9 / IMCR9 */ 631 { 0, 0, 0, CMT, 0, USB_USBI1, USB_USBI0, } }, 632 { 0xa40800a8, 0xa40800e8, 8, /* IMR10 / IMCR10 */ 633 { } }, 634 { 0xa40800ac, 0xa40800ec, 8, /* IMR11 / IMCR11 */ 635 { 0, RTC_CUI, RTC_PRI, RTC_ATI, 0, TPU, 0, TSIF } }, 636 { 0xa4140044, 0xa4140064, 8, /* INTMSK00 / INTMSKCLR00 */ 637 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } }, 638 }; 639 640 static struct intc_prio_reg prio_registers[] __initdata = { 641 { 0xa4080000, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, IRDA } }, 642 { 0xa4080004, 0, 16, 4, /* IPRB */ { JPU, LCDC, SIM } }, 643 { 0xa4080008, 0, 16, 4, /* IPRC */ { } }, 644 { 0xa408000c, 0, 16, 4, /* IPRD */ { } }, 645 { 0xa4080010, 0, 16, 4, /* IPRE */ { DMAC0123, VIOVOU, 0, VPU } }, 646 { 0xa4080014, 0, 16, 4, /* IPRF */ { KEYSC, DMAC45, USB, CMT } }, 647 { 0xa4080018, 0, 16, 4, /* IPRG */ { SCIF0, SCIF1, SCIF2 } }, 648 { 0xa408001c, 0, 16, 4, /* IPRH */ { SIOF0, SIOF1, FLCTL, I2C } }, 649 { 0xa4080020, 0, 16, 4, /* IPRI */ { SIO, 0, TSIF, RTC } }, 650 { 0xa4080024, 0, 16, 4, /* IPRJ */ { 0, 0, SIU } }, 651 { 0xa4080028, 0, 16, 4, /* IPRK */ { 0, 0, 0, SDHI } }, 652 { 0xa408002c, 0, 16, 4, /* IPRL */ { TWODG, 0, TPU } }, 653 { 0xa4140010, 0, 32, 4, /* INTPRI00 */ 654 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } }, 655 }; 656 657 static struct intc_sense_reg sense_registers[] __initdata = { 658 { 0xa414001c, 16, 2, /* ICR1 */ 659 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } }, 660 }; 661 662 static struct intc_mask_reg ack_registers[] __initdata = { 663 { 0xa4140024, 0, 8, /* INTREQ00 */ 664 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } }, 665 }; 666 667 static struct intc_desc intc_desc __initdata = { 668 .name = "sh7722", 669 .force_enable = ENABLED, 670 .force_disable = DISABLED, 671 .hw = INTC_HW_DESC(vectors, groups, mask_registers, 672 prio_registers, sense_registers, ack_registers), 673 }; 674 675 void __init plat_irq_setup(void) 676 { 677 register_intc_controller(&intc_desc); 678 } 679 680 void __init plat_mem_setup(void) 681 { 682 /* Register the URAM space as Node 1 */ 683 setup_bootmem_node(1, 0x055f0000, 0x05610000); 684 } 685