1 /* 2 * SH7722 Setup 3 * 4 * Copyright (C) 2006 - 2008 Paul Mundt 5 * 6 * This file is subject to the terms and conditions of the GNU General Public 7 * License. See the file "COPYING" in the main directory of this archive 8 * for more details. 9 */ 10 #include <linux/init.h> 11 #include <linux/mm.h> 12 #include <linux/platform_device.h> 13 #include <linux/serial.h> 14 #include <linux/serial_sci.h> 15 #include <linux/sh_timer.h> 16 #include <linux/uio_driver.h> 17 #include <linux/usb/m66592.h> 18 19 #include <asm/clock.h> 20 #include <asm/dmaengine.h> 21 #include <asm/mmzone.h> 22 #include <asm/siu.h> 23 24 #include <cpu/dma-register.h> 25 #include <cpu/sh7722.h> 26 27 static struct sh_dmae_slave_config sh7722_dmae_slaves[] = { 28 { 29 .slave_id = SHDMA_SLAVE_SCIF0_TX, 30 .addr = 0xffe0000c, 31 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT), 32 .mid_rid = 0x21, 33 }, { 34 .slave_id = SHDMA_SLAVE_SCIF0_RX, 35 .addr = 0xffe00014, 36 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT), 37 .mid_rid = 0x22, 38 }, { 39 .slave_id = SHDMA_SLAVE_SCIF1_TX, 40 .addr = 0xffe1000c, 41 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT), 42 .mid_rid = 0x25, 43 }, { 44 .slave_id = SHDMA_SLAVE_SCIF1_RX, 45 .addr = 0xffe10014, 46 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT), 47 .mid_rid = 0x26, 48 }, { 49 .slave_id = SHDMA_SLAVE_SCIF2_TX, 50 .addr = 0xffe2000c, 51 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT), 52 .mid_rid = 0x29, 53 }, { 54 .slave_id = SHDMA_SLAVE_SCIF2_RX, 55 .addr = 0xffe20014, 56 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT), 57 .mid_rid = 0x2a, 58 }, { 59 .slave_id = SHDMA_SLAVE_SIUA_TX, 60 .addr = 0xa454c098, 61 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT), 62 .mid_rid = 0xb1, 63 }, { 64 .slave_id = SHDMA_SLAVE_SIUA_RX, 65 .addr = 0xa454c090, 66 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT), 67 .mid_rid = 0xb2, 68 }, { 69 .slave_id = SHDMA_SLAVE_SIUB_TX, 70 .addr = 0xa454c09c, 71 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT), 72 .mid_rid = 0xb5, 73 }, { 74 .slave_id = SHDMA_SLAVE_SIUB_RX, 75 .addr = 0xa454c094, 76 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT), 77 .mid_rid = 0xb6, 78 }, 79 }; 80 81 static struct sh_dmae_channel sh7722_dmae_channels[] = { 82 { 83 .offset = 0, 84 .dmars = 0, 85 .dmars_bit = 0, 86 }, { 87 .offset = 0x10, 88 .dmars = 0, 89 .dmars_bit = 8, 90 }, { 91 .offset = 0x20, 92 .dmars = 4, 93 .dmars_bit = 0, 94 }, { 95 .offset = 0x30, 96 .dmars = 4, 97 .dmars_bit = 8, 98 }, { 99 .offset = 0x50, 100 .dmars = 8, 101 .dmars_bit = 0, 102 }, { 103 .offset = 0x60, 104 .dmars = 8, 105 .dmars_bit = 8, 106 } 107 }; 108 109 static unsigned int ts_shift[] = TS_SHIFT; 110 111 static struct sh_dmae_pdata dma_platform_data = { 112 .slave = sh7722_dmae_slaves, 113 .slave_num = ARRAY_SIZE(sh7722_dmae_slaves), 114 .channel = sh7722_dmae_channels, 115 .channel_num = ARRAY_SIZE(sh7722_dmae_channels), 116 .ts_low_shift = CHCR_TS_LOW_SHIFT, 117 .ts_low_mask = CHCR_TS_LOW_MASK, 118 .ts_high_shift = CHCR_TS_HIGH_SHIFT, 119 .ts_high_mask = CHCR_TS_HIGH_MASK, 120 .ts_shift = ts_shift, 121 .ts_shift_num = ARRAY_SIZE(ts_shift), 122 .dmaor_init = DMAOR_INIT, 123 }; 124 125 static struct resource sh7722_dmae_resources[] = { 126 [0] = { 127 /* Channel registers and DMAOR */ 128 .start = 0xfe008020, 129 .end = 0xfe00808f, 130 .flags = IORESOURCE_MEM, 131 }, 132 [1] = { 133 /* DMARSx */ 134 .start = 0xfe009000, 135 .end = 0xfe00900b, 136 .flags = IORESOURCE_MEM, 137 }, 138 { 139 /* DMA error IRQ */ 140 .start = 78, 141 .end = 78, 142 .flags = IORESOURCE_IRQ, 143 }, 144 { 145 /* IRQ for channels 0-3 */ 146 .start = 48, 147 .end = 51, 148 .flags = IORESOURCE_IRQ, 149 }, 150 { 151 /* IRQ for channels 4-5 */ 152 .start = 76, 153 .end = 77, 154 .flags = IORESOURCE_IRQ, 155 }, 156 }; 157 158 struct platform_device dma_device = { 159 .name = "sh-dma-engine", 160 .id = -1, 161 .resource = sh7722_dmae_resources, 162 .num_resources = ARRAY_SIZE(sh7722_dmae_resources), 163 .dev = { 164 .platform_data = &dma_platform_data, 165 }, 166 }; 167 168 /* Serial */ 169 static struct plat_sci_port scif0_platform_data = { 170 .mapbase = 0xffe00000, 171 .flags = UPF_BOOT_AUTOCONF, 172 .type = PORT_SCIF, 173 .irqs = { 80, 80, 80, 80 }, 174 .clk = "scif0", 175 }; 176 177 static struct platform_device scif0_device = { 178 .name = "sh-sci", 179 .id = 0, 180 .dev = { 181 .platform_data = &scif0_platform_data, 182 }, 183 }; 184 185 static struct plat_sci_port scif1_platform_data = { 186 .mapbase = 0xffe10000, 187 .flags = UPF_BOOT_AUTOCONF, 188 .type = PORT_SCIF, 189 .irqs = { 81, 81, 81, 81 }, 190 .clk = "scif1", 191 }; 192 193 static struct platform_device scif1_device = { 194 .name = "sh-sci", 195 .id = 1, 196 .dev = { 197 .platform_data = &scif1_platform_data, 198 }, 199 }; 200 201 static struct plat_sci_port scif2_platform_data = { 202 .mapbase = 0xffe20000, 203 .flags = UPF_BOOT_AUTOCONF, 204 .type = PORT_SCIF, 205 .irqs = { 82, 82, 82, 82 }, 206 .clk = "scif2", 207 }; 208 209 static struct platform_device scif2_device = { 210 .name = "sh-sci", 211 .id = 2, 212 .dev = { 213 .platform_data = &scif2_platform_data, 214 }, 215 }; 216 217 static struct resource rtc_resources[] = { 218 [0] = { 219 .start = 0xa465fec0, 220 .end = 0xa465fec0 + 0x58 - 1, 221 .flags = IORESOURCE_IO, 222 }, 223 [1] = { 224 /* Period IRQ */ 225 .start = 45, 226 .flags = IORESOURCE_IRQ, 227 }, 228 [2] = { 229 /* Carry IRQ */ 230 .start = 46, 231 .flags = IORESOURCE_IRQ, 232 }, 233 [3] = { 234 /* Alarm IRQ */ 235 .start = 44, 236 .flags = IORESOURCE_IRQ, 237 }, 238 }; 239 240 static struct platform_device rtc_device = { 241 .name = "sh-rtc", 242 .id = -1, 243 .num_resources = ARRAY_SIZE(rtc_resources), 244 .resource = rtc_resources, 245 .archdata = { 246 .hwblk_id = HWBLK_RTC, 247 }, 248 }; 249 250 static struct m66592_platdata usbf_platdata = { 251 .on_chip = 1, 252 }; 253 254 static struct resource usbf_resources[] = { 255 [0] = { 256 .name = "USBF", 257 .start = 0x04480000, 258 .end = 0x044800FF, 259 .flags = IORESOURCE_MEM, 260 }, 261 [1] = { 262 .start = 65, 263 .end = 65, 264 .flags = IORESOURCE_IRQ, 265 }, 266 }; 267 268 static struct platform_device usbf_device = { 269 .name = "m66592_udc", 270 .id = 0, /* "usbf0" clock */ 271 .dev = { 272 .dma_mask = NULL, 273 .coherent_dma_mask = 0xffffffff, 274 .platform_data = &usbf_platdata, 275 }, 276 .num_resources = ARRAY_SIZE(usbf_resources), 277 .resource = usbf_resources, 278 .archdata = { 279 .hwblk_id = HWBLK_USBF, 280 }, 281 }; 282 283 static struct resource iic_resources[] = { 284 [0] = { 285 .name = "IIC", 286 .start = 0x04470000, 287 .end = 0x04470017, 288 .flags = IORESOURCE_MEM, 289 }, 290 [1] = { 291 .start = 96, 292 .end = 99, 293 .flags = IORESOURCE_IRQ, 294 }, 295 }; 296 297 static struct platform_device iic_device = { 298 .name = "i2c-sh_mobile", 299 .id = 0, /* "i2c0" clock */ 300 .num_resources = ARRAY_SIZE(iic_resources), 301 .resource = iic_resources, 302 .archdata = { 303 .hwblk_id = HWBLK_IIC, 304 }, 305 }; 306 307 static struct uio_info vpu_platform_data = { 308 .name = "VPU4", 309 .version = "0", 310 .irq = 60, 311 }; 312 313 static struct resource vpu_resources[] = { 314 [0] = { 315 .name = "VPU", 316 .start = 0xfe900000, 317 .end = 0xfe9022eb, 318 .flags = IORESOURCE_MEM, 319 }, 320 [1] = { 321 /* place holder for contiguous memory */ 322 }, 323 }; 324 325 static struct platform_device vpu_device = { 326 .name = "uio_pdrv_genirq", 327 .id = 0, 328 .dev = { 329 .platform_data = &vpu_platform_data, 330 }, 331 .resource = vpu_resources, 332 .num_resources = ARRAY_SIZE(vpu_resources), 333 .archdata = { 334 .hwblk_id = HWBLK_VPU, 335 }, 336 }; 337 338 static struct uio_info veu_platform_data = { 339 .name = "VEU", 340 .version = "0", 341 .irq = 54, 342 }; 343 344 static struct resource veu_resources[] = { 345 [0] = { 346 .name = "VEU", 347 .start = 0xfe920000, 348 .end = 0xfe9200b7, 349 .flags = IORESOURCE_MEM, 350 }, 351 [1] = { 352 /* place holder for contiguous memory */ 353 }, 354 }; 355 356 static struct platform_device veu_device = { 357 .name = "uio_pdrv_genirq", 358 .id = 1, 359 .dev = { 360 .platform_data = &veu_platform_data, 361 }, 362 .resource = veu_resources, 363 .num_resources = ARRAY_SIZE(veu_resources), 364 .archdata = { 365 .hwblk_id = HWBLK_VEU, 366 }, 367 }; 368 369 static struct uio_info jpu_platform_data = { 370 .name = "JPU", 371 .version = "0", 372 .irq = 27, 373 }; 374 375 static struct resource jpu_resources[] = { 376 [0] = { 377 .name = "JPU", 378 .start = 0xfea00000, 379 .end = 0xfea102d3, 380 .flags = IORESOURCE_MEM, 381 }, 382 [1] = { 383 /* place holder for contiguous memory */ 384 }, 385 }; 386 387 static struct platform_device jpu_device = { 388 .name = "uio_pdrv_genirq", 389 .id = 2, 390 .dev = { 391 .platform_data = &jpu_platform_data, 392 }, 393 .resource = jpu_resources, 394 .num_resources = ARRAY_SIZE(jpu_resources), 395 .archdata = { 396 .hwblk_id = HWBLK_JPU, 397 }, 398 }; 399 400 static struct sh_timer_config cmt_platform_data = { 401 .name = "CMT", 402 .channel_offset = 0x60, 403 .timer_bit = 5, 404 .clk = "cmt0", 405 .clockevent_rating = 125, 406 .clocksource_rating = 125, 407 }; 408 409 static struct resource cmt_resources[] = { 410 [0] = { 411 .name = "CMT", 412 .start = 0x044a0060, 413 .end = 0x044a006b, 414 .flags = IORESOURCE_MEM, 415 }, 416 [1] = { 417 .start = 104, 418 .flags = IORESOURCE_IRQ, 419 }, 420 }; 421 422 static struct platform_device cmt_device = { 423 .name = "sh_cmt", 424 .id = 0, 425 .dev = { 426 .platform_data = &cmt_platform_data, 427 }, 428 .resource = cmt_resources, 429 .num_resources = ARRAY_SIZE(cmt_resources), 430 .archdata = { 431 .hwblk_id = HWBLK_CMT, 432 }, 433 }; 434 435 static struct sh_timer_config tmu0_platform_data = { 436 .name = "TMU0", 437 .channel_offset = 0x04, 438 .timer_bit = 0, 439 .clk = "tmu0", 440 .clockevent_rating = 200, 441 }; 442 443 static struct resource tmu0_resources[] = { 444 [0] = { 445 .name = "TMU0", 446 .start = 0xffd80008, 447 .end = 0xffd80013, 448 .flags = IORESOURCE_MEM, 449 }, 450 [1] = { 451 .start = 16, 452 .flags = IORESOURCE_IRQ, 453 }, 454 }; 455 456 static struct platform_device tmu0_device = { 457 .name = "sh_tmu", 458 .id = 0, 459 .dev = { 460 .platform_data = &tmu0_platform_data, 461 }, 462 .resource = tmu0_resources, 463 .num_resources = ARRAY_SIZE(tmu0_resources), 464 .archdata = { 465 .hwblk_id = HWBLK_TMU, 466 }, 467 }; 468 469 static struct sh_timer_config tmu1_platform_data = { 470 .name = "TMU1", 471 .channel_offset = 0x10, 472 .timer_bit = 1, 473 .clk = "tmu0", 474 .clocksource_rating = 200, 475 }; 476 477 static struct resource tmu1_resources[] = { 478 [0] = { 479 .name = "TMU1", 480 .start = 0xffd80014, 481 .end = 0xffd8001f, 482 .flags = IORESOURCE_MEM, 483 }, 484 [1] = { 485 .start = 17, 486 .flags = IORESOURCE_IRQ, 487 }, 488 }; 489 490 static struct platform_device tmu1_device = { 491 .name = "sh_tmu", 492 .id = 1, 493 .dev = { 494 .platform_data = &tmu1_platform_data, 495 }, 496 .resource = tmu1_resources, 497 .num_resources = ARRAY_SIZE(tmu1_resources), 498 .archdata = { 499 .hwblk_id = HWBLK_TMU, 500 }, 501 }; 502 503 static struct sh_timer_config tmu2_platform_data = { 504 .name = "TMU2", 505 .channel_offset = 0x1c, 506 .timer_bit = 2, 507 .clk = "tmu0", 508 }; 509 510 static struct resource tmu2_resources[] = { 511 [0] = { 512 .name = "TMU2", 513 .start = 0xffd80020, 514 .end = 0xffd8002b, 515 .flags = IORESOURCE_MEM, 516 }, 517 [1] = { 518 .start = 18, 519 .flags = IORESOURCE_IRQ, 520 }, 521 }; 522 523 static struct platform_device tmu2_device = { 524 .name = "sh_tmu", 525 .id = 2, 526 .dev = { 527 .platform_data = &tmu2_platform_data, 528 }, 529 .resource = tmu2_resources, 530 .num_resources = ARRAY_SIZE(tmu2_resources), 531 .archdata = { 532 .hwblk_id = HWBLK_TMU, 533 }, 534 }; 535 536 static struct siu_platform siu_platform_data = { 537 .dma_dev = &dma_device.dev, 538 .dma_slave_tx_a = SHDMA_SLAVE_SIUA_TX, 539 .dma_slave_rx_a = SHDMA_SLAVE_SIUA_RX, 540 .dma_slave_tx_b = SHDMA_SLAVE_SIUB_TX, 541 .dma_slave_rx_b = SHDMA_SLAVE_SIUB_RX, 542 }; 543 544 static struct resource siu_resources[] = { 545 [0] = { 546 .start = 0xa4540000, 547 .end = 0xa454c10f, 548 .flags = IORESOURCE_MEM, 549 }, 550 [1] = { 551 .start = 108, 552 .flags = IORESOURCE_IRQ, 553 }, 554 }; 555 556 static struct platform_device siu_device = { 557 .name = "sh_siu", 558 .id = -1, 559 .dev = { 560 .platform_data = &siu_platform_data, 561 }, 562 .resource = siu_resources, 563 .num_resources = ARRAY_SIZE(siu_resources), 564 .archdata = { 565 .hwblk_id = HWBLK_SIU, 566 }, 567 }; 568 569 static struct platform_device *sh7722_devices[] __initdata = { 570 &scif0_device, 571 &scif1_device, 572 &scif2_device, 573 &cmt_device, 574 &tmu0_device, 575 &tmu1_device, 576 &tmu2_device, 577 &rtc_device, 578 &usbf_device, 579 &iic_device, 580 &vpu_device, 581 &veu_device, 582 &jpu_device, 583 &siu_device, 584 &dma_device, 585 }; 586 587 static int __init sh7722_devices_setup(void) 588 { 589 platform_resource_setup_memory(&vpu_device, "vpu", 1 << 20); 590 platform_resource_setup_memory(&veu_device, "veu", 2 << 20); 591 platform_resource_setup_memory(&jpu_device, "jpu", 2 << 20); 592 593 return platform_add_devices(sh7722_devices, 594 ARRAY_SIZE(sh7722_devices)); 595 } 596 arch_initcall(sh7722_devices_setup); 597 598 static struct platform_device *sh7722_early_devices[] __initdata = { 599 &scif0_device, 600 &scif1_device, 601 &scif2_device, 602 &cmt_device, 603 &tmu0_device, 604 &tmu1_device, 605 &tmu2_device, 606 }; 607 608 void __init plat_early_device_setup(void) 609 { 610 early_platform_add_devices(sh7722_early_devices, 611 ARRAY_SIZE(sh7722_early_devices)); 612 } 613 614 enum { 615 UNUSED=0, 616 ENABLED, 617 DISABLED, 618 619 /* interrupt sources */ 620 IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7, 621 HUDI, 622 SIM_ERI, SIM_RXI, SIM_TXI, SIM_TEI, 623 RTC_ATI, RTC_PRI, RTC_CUI, 624 DMAC0, DMAC1, DMAC2, DMAC3, 625 VIO_CEUI, VIO_BEUI, VIO_VEUI, VOU, 626 VPU, TPU, 627 USB_USBI0, USB_USBI1, 628 DMAC4, DMAC5, DMAC_DADERR, 629 KEYSC, 630 SCIF0, SCIF1, SCIF2, SIOF0, SIOF1, SIO, 631 FLCTL_FLSTEI, FLCTL_FLENDI, FLCTL_FLTREQ0I, FLCTL_FLTREQ1I, 632 I2C_ALI, I2C_TACKI, I2C_WAITI, I2C_DTEI, 633 CMT, TSIF, SIU, TWODG, 634 TMU0, TMU1, TMU2, 635 IRDA, JPU, LCDC, 636 637 /* interrupt groups */ 638 SIM, RTC, DMAC0123, VIOVOU, USB, DMAC45, FLCTL, I2C, SDHI, 639 }; 640 641 static struct intc_vect vectors[] __initdata = { 642 INTC_VECT(IRQ0, 0x600), INTC_VECT(IRQ1, 0x620), 643 INTC_VECT(IRQ2, 0x640), INTC_VECT(IRQ3, 0x660), 644 INTC_VECT(IRQ4, 0x680), INTC_VECT(IRQ5, 0x6a0), 645 INTC_VECT(IRQ6, 0x6c0), INTC_VECT(IRQ7, 0x6e0), 646 INTC_VECT(SIM_ERI, 0x700), INTC_VECT(SIM_RXI, 0x720), 647 INTC_VECT(SIM_TXI, 0x740), INTC_VECT(SIM_TEI, 0x760), 648 INTC_VECT(RTC_ATI, 0x780), INTC_VECT(RTC_PRI, 0x7a0), 649 INTC_VECT(RTC_CUI, 0x7c0), 650 INTC_VECT(DMAC0, 0x800), INTC_VECT(DMAC1, 0x820), 651 INTC_VECT(DMAC2, 0x840), INTC_VECT(DMAC3, 0x860), 652 INTC_VECT(VIO_CEUI, 0x880), INTC_VECT(VIO_BEUI, 0x8a0), 653 INTC_VECT(VIO_VEUI, 0x8c0), INTC_VECT(VOU, 0x8e0), 654 INTC_VECT(VPU, 0x980), INTC_VECT(TPU, 0x9a0), 655 INTC_VECT(USB_USBI0, 0xa20), INTC_VECT(USB_USBI1, 0xa40), 656 INTC_VECT(DMAC4, 0xb80), INTC_VECT(DMAC5, 0xba0), 657 INTC_VECT(DMAC_DADERR, 0xbc0), INTC_VECT(KEYSC, 0xbe0), 658 INTC_VECT(SCIF0, 0xc00), INTC_VECT(SCIF1, 0xc20), 659 INTC_VECT(SCIF2, 0xc40), INTC_VECT(SIOF0, 0xc80), 660 INTC_VECT(SIOF1, 0xca0), INTC_VECT(SIO, 0xd00), 661 INTC_VECT(FLCTL_FLSTEI, 0xd80), INTC_VECT(FLCTL_FLENDI, 0xda0), 662 INTC_VECT(FLCTL_FLTREQ0I, 0xdc0), INTC_VECT(FLCTL_FLTREQ1I, 0xde0), 663 INTC_VECT(I2C_ALI, 0xe00), INTC_VECT(I2C_TACKI, 0xe20), 664 INTC_VECT(I2C_WAITI, 0xe40), INTC_VECT(I2C_DTEI, 0xe60), 665 INTC_VECT(SDHI, 0xe80), INTC_VECT(SDHI, 0xea0), 666 INTC_VECT(SDHI, 0xec0), INTC_VECT(SDHI, 0xee0), 667 INTC_VECT(CMT, 0xf00), INTC_VECT(TSIF, 0xf20), 668 INTC_VECT(SIU, 0xf80), INTC_VECT(TWODG, 0xfa0), 669 INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420), 670 INTC_VECT(TMU2, 0x440), INTC_VECT(IRDA, 0x480), 671 INTC_VECT(JPU, 0x560), INTC_VECT(LCDC, 0x580), 672 }; 673 674 static struct intc_group groups[] __initdata = { 675 INTC_GROUP(SIM, SIM_ERI, SIM_RXI, SIM_TXI, SIM_TEI), 676 INTC_GROUP(RTC, RTC_ATI, RTC_PRI, RTC_CUI), 677 INTC_GROUP(DMAC0123, DMAC0, DMAC1, DMAC2, DMAC3), 678 INTC_GROUP(VIOVOU, VIO_CEUI, VIO_BEUI, VIO_VEUI, VOU), 679 INTC_GROUP(USB, USB_USBI0, USB_USBI1), 680 INTC_GROUP(DMAC45, DMAC4, DMAC5, DMAC_DADERR), 681 INTC_GROUP(FLCTL, FLCTL_FLSTEI, FLCTL_FLENDI, 682 FLCTL_FLTREQ0I, FLCTL_FLTREQ1I), 683 INTC_GROUP(I2C, I2C_ALI, I2C_TACKI, I2C_WAITI, I2C_DTEI), 684 }; 685 686 static struct intc_mask_reg mask_registers[] __initdata = { 687 { 0xa4080080, 0xa40800c0, 8, /* IMR0 / IMCR0 */ 688 { } }, 689 { 0xa4080084, 0xa40800c4, 8, /* IMR1 / IMCR1 */ 690 { VOU, VIO_VEUI, VIO_BEUI, VIO_CEUI, DMAC3, DMAC2, DMAC1, DMAC0 } }, 691 { 0xa4080088, 0xa40800c8, 8, /* IMR2 / IMCR2 */ 692 { 0, 0, 0, VPU, } }, 693 { 0xa408008c, 0xa40800cc, 8, /* IMR3 / IMCR3 */ 694 { SIM_TEI, SIM_TXI, SIM_RXI, SIM_ERI, 0, 0, 0, IRDA } }, 695 { 0xa4080090, 0xa40800d0, 8, /* IMR4 / IMCR4 */ 696 { 0, TMU2, TMU1, TMU0, JPU, 0, 0, LCDC } }, 697 { 0xa4080094, 0xa40800d4, 8, /* IMR5 / IMCR5 */ 698 { KEYSC, DMAC_DADERR, DMAC5, DMAC4, 0, SCIF2, SCIF1, SCIF0 } }, 699 { 0xa4080098, 0xa40800d8, 8, /* IMR6 / IMCR6 */ 700 { 0, 0, 0, SIO, 0, 0, SIOF1, SIOF0 } }, 701 { 0xa408009c, 0xa40800dc, 8, /* IMR7 / IMCR7 */ 702 { I2C_DTEI, I2C_WAITI, I2C_TACKI, I2C_ALI, 703 FLCTL_FLTREQ1I, FLCTL_FLTREQ0I, FLCTL_FLENDI, FLCTL_FLSTEI } }, 704 { 0xa40800a0, 0xa40800e0, 8, /* IMR8 / IMCR8 */ 705 { DISABLED, DISABLED, ENABLED, ENABLED, 0, 0, TWODG, SIU } }, 706 { 0xa40800a4, 0xa40800e4, 8, /* IMR9 / IMCR9 */ 707 { 0, 0, 0, CMT, 0, USB_USBI1, USB_USBI0, } }, 708 { 0xa40800a8, 0xa40800e8, 8, /* IMR10 / IMCR10 */ 709 { } }, 710 { 0xa40800ac, 0xa40800ec, 8, /* IMR11 / IMCR11 */ 711 { 0, RTC_CUI, RTC_PRI, RTC_ATI, 0, TPU, 0, TSIF } }, 712 { 0xa4140044, 0xa4140064, 8, /* INTMSK00 / INTMSKCLR00 */ 713 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } }, 714 }; 715 716 static struct intc_prio_reg prio_registers[] __initdata = { 717 { 0xa4080000, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, IRDA } }, 718 { 0xa4080004, 0, 16, 4, /* IPRB */ { JPU, LCDC, SIM } }, 719 { 0xa4080008, 0, 16, 4, /* IPRC */ { } }, 720 { 0xa408000c, 0, 16, 4, /* IPRD */ { } }, 721 { 0xa4080010, 0, 16, 4, /* IPRE */ { DMAC0123, VIOVOU, 0, VPU } }, 722 { 0xa4080014, 0, 16, 4, /* IPRF */ { KEYSC, DMAC45, USB, CMT } }, 723 { 0xa4080018, 0, 16, 4, /* IPRG */ { SCIF0, SCIF1, SCIF2 } }, 724 { 0xa408001c, 0, 16, 4, /* IPRH */ { SIOF0, SIOF1, FLCTL, I2C } }, 725 { 0xa4080020, 0, 16, 4, /* IPRI */ { SIO, 0, TSIF, RTC } }, 726 { 0xa4080024, 0, 16, 4, /* IPRJ */ { 0, 0, SIU } }, 727 { 0xa4080028, 0, 16, 4, /* IPRK */ { 0, 0, 0, SDHI } }, 728 { 0xa408002c, 0, 16, 4, /* IPRL */ { TWODG, 0, TPU } }, 729 { 0xa4140010, 0, 32, 4, /* INTPRI00 */ 730 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } }, 731 }; 732 733 static struct intc_sense_reg sense_registers[] __initdata = { 734 { 0xa414001c, 16, 2, /* ICR1 */ 735 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } }, 736 }; 737 738 static struct intc_mask_reg ack_registers[] __initdata = { 739 { 0xa4140024, 0, 8, /* INTREQ00 */ 740 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } }, 741 }; 742 743 static struct intc_desc intc_desc __initdata = { 744 .name = "sh7722", 745 .force_enable = ENABLED, 746 .force_disable = DISABLED, 747 .hw = INTC_HW_DESC(vectors, groups, mask_registers, 748 prio_registers, sense_registers, ack_registers), 749 }; 750 751 void __init plat_irq_setup(void) 752 { 753 register_intc_controller(&intc_desc); 754 } 755 756 void __init plat_mem_setup(void) 757 { 758 /* Register the URAM space as Node 1 */ 759 setup_bootmem_node(1, 0x055f0000, 0x05610000); 760 } 761