1 /* 2 * SH7366 Setup 3 * 4 * Copyright (C) 2008 Renesas Solutions 5 * 6 * Based on linux/arch/sh/kernel/cpu/sh4a/setup-sh7722.c 7 * 8 * This file is subject to the terms and conditions of the GNU General Public 9 * License. See the file "COPYING" in the main directory of this archive 10 * for more details. 11 */ 12 #include <linux/platform_device.h> 13 #include <linux/init.h> 14 #include <linux/serial.h> 15 #include <linux/serial_sci.h> 16 #include <linux/uio_driver.h> 17 #include <linux/sh_timer.h> 18 #include <linux/sh_intc.h> 19 #include <linux/usb/r8a66597.h> 20 #include <asm/clock.h> 21 22 static struct plat_sci_port scif0_platform_data = { 23 .port_reg = 0xa405013e, 24 .flags = UPF_BOOT_AUTOCONF, 25 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 26 .type = PORT_SCIF, 27 }; 28 29 static struct resource scif0_resources[] = { 30 DEFINE_RES_MEM(0xffe00000, 0x100), 31 DEFINE_RES_IRQ(evt2irq(0xc00)), 32 }; 33 34 static struct platform_device scif0_device = { 35 .name = "sh-sci", 36 .id = 0, 37 .resource = scif0_resources, 38 .num_resources = ARRAY_SIZE(scif0_resources), 39 .dev = { 40 .platform_data = &scif0_platform_data, 41 }, 42 }; 43 44 static struct resource iic_resources[] = { 45 [0] = { 46 .name = "IIC", 47 .start = 0x04470000, 48 .end = 0x04470017, 49 .flags = IORESOURCE_MEM, 50 }, 51 [1] = { 52 .start = evt2irq(0xe00), 53 .end = evt2irq(0xe60), 54 .flags = IORESOURCE_IRQ, 55 }, 56 }; 57 58 static struct platform_device iic_device = { 59 .name = "i2c-sh_mobile", 60 .id = 0, /* "i2c0" clock */ 61 .num_resources = ARRAY_SIZE(iic_resources), 62 .resource = iic_resources, 63 }; 64 65 static struct r8a66597_platdata r8a66597_data = { 66 .on_chip = 1, 67 }; 68 69 static struct resource usb_host_resources[] = { 70 [0] = { 71 .start = 0xa4d80000, 72 .end = 0xa4d800ff, 73 .flags = IORESOURCE_MEM, 74 }, 75 [1] = { 76 .start = evt2irq(0xa20), 77 .end = evt2irq(0xa20), 78 .flags = IORESOURCE_IRQ | IRQF_TRIGGER_LOW, 79 }, 80 }; 81 82 static struct platform_device usb_host_device = { 83 .name = "r8a66597_hcd", 84 .id = -1, 85 .dev = { 86 .dma_mask = NULL, 87 .coherent_dma_mask = 0xffffffff, 88 .platform_data = &r8a66597_data, 89 }, 90 .num_resources = ARRAY_SIZE(usb_host_resources), 91 .resource = usb_host_resources, 92 }; 93 94 static struct uio_info vpu_platform_data = { 95 .name = "VPU5", 96 .version = "0", 97 .irq = evt2irq(0x980), 98 }; 99 100 static struct resource vpu_resources[] = { 101 [0] = { 102 .name = "VPU", 103 .start = 0xfe900000, 104 .end = 0xfe902807, 105 .flags = IORESOURCE_MEM, 106 }, 107 [1] = { 108 /* place holder for contiguous memory */ 109 }, 110 }; 111 112 static struct platform_device vpu_device = { 113 .name = "uio_pdrv_genirq", 114 .id = 0, 115 .dev = { 116 .platform_data = &vpu_platform_data, 117 }, 118 .resource = vpu_resources, 119 .num_resources = ARRAY_SIZE(vpu_resources), 120 }; 121 122 static struct uio_info veu0_platform_data = { 123 .name = "VEU", 124 .version = "0", 125 .irq = evt2irq(0x8c0), 126 }; 127 128 static struct resource veu0_resources[] = { 129 [0] = { 130 .name = "VEU(1)", 131 .start = 0xfe920000, 132 .end = 0xfe9200b7, 133 .flags = IORESOURCE_MEM, 134 }, 135 [1] = { 136 /* place holder for contiguous memory */ 137 }, 138 }; 139 140 static struct platform_device veu0_device = { 141 .name = "uio_pdrv_genirq", 142 .id = 1, 143 .dev = { 144 .platform_data = &veu0_platform_data, 145 }, 146 .resource = veu0_resources, 147 .num_resources = ARRAY_SIZE(veu0_resources), 148 }; 149 150 static struct uio_info veu1_platform_data = { 151 .name = "VEU", 152 .version = "0", 153 .irq = evt2irq(0x560), 154 }; 155 156 static struct resource veu1_resources[] = { 157 [0] = { 158 .name = "VEU(2)", 159 .start = 0xfe924000, 160 .end = 0xfe9240b7, 161 .flags = IORESOURCE_MEM, 162 }, 163 [1] = { 164 /* place holder for contiguous memory */ 165 }, 166 }; 167 168 static struct platform_device veu1_device = { 169 .name = "uio_pdrv_genirq", 170 .id = 2, 171 .dev = { 172 .platform_data = &veu1_platform_data, 173 }, 174 .resource = veu1_resources, 175 .num_resources = ARRAY_SIZE(veu1_resources), 176 }; 177 178 static struct sh_timer_config cmt_platform_data = { 179 .channels_mask = 0x20, 180 }; 181 182 static struct resource cmt_resources[] = { 183 DEFINE_RES_MEM(0x044a0000, 0x70), 184 DEFINE_RES_IRQ(evt2irq(0xf00)), 185 }; 186 187 static struct platform_device cmt_device = { 188 .name = "sh-cmt-32", 189 .id = 0, 190 .dev = { 191 .platform_data = &cmt_platform_data, 192 }, 193 .resource = cmt_resources, 194 .num_resources = ARRAY_SIZE(cmt_resources), 195 }; 196 197 static struct sh_timer_config tmu0_platform_data = { 198 .channels_mask = 7, 199 }; 200 201 static struct resource tmu0_resources[] = { 202 DEFINE_RES_MEM(0xffd80000, 0x2c), 203 DEFINE_RES_IRQ(evt2irq(0x400)), 204 DEFINE_RES_IRQ(evt2irq(0x420)), 205 DEFINE_RES_IRQ(evt2irq(0x440)), 206 }; 207 208 static struct platform_device tmu0_device = { 209 .name = "sh-tmu", 210 .id = 0, 211 .dev = { 212 .platform_data = &tmu0_platform_data, 213 }, 214 .resource = tmu0_resources, 215 .num_resources = ARRAY_SIZE(tmu0_resources), 216 }; 217 218 static struct platform_device *sh7366_devices[] __initdata = { 219 &scif0_device, 220 &cmt_device, 221 &tmu0_device, 222 &iic_device, 223 &usb_host_device, 224 &vpu_device, 225 &veu0_device, 226 &veu1_device, 227 }; 228 229 static int __init sh7366_devices_setup(void) 230 { 231 platform_resource_setup_memory(&vpu_device, "vpu", 2 << 20); 232 platform_resource_setup_memory(&veu0_device, "veu0", 2 << 20); 233 platform_resource_setup_memory(&veu1_device, "veu1", 2 << 20); 234 235 return platform_add_devices(sh7366_devices, 236 ARRAY_SIZE(sh7366_devices)); 237 } 238 arch_initcall(sh7366_devices_setup); 239 240 static struct platform_device *sh7366_early_devices[] __initdata = { 241 &scif0_device, 242 &cmt_device, 243 &tmu0_device, 244 }; 245 246 void __init plat_early_device_setup(void) 247 { 248 early_platform_add_devices(sh7366_early_devices, 249 ARRAY_SIZE(sh7366_early_devices)); 250 } 251 252 enum { 253 UNUSED=0, 254 ENABLED, 255 DISABLED, 256 257 /* interrupt sources */ 258 IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7, 259 ICB, 260 DMAC0, DMAC1, DMAC2, DMAC3, 261 VIO_CEUI, VIO_BEUI, VIO_VEUI, VOU, 262 MFI, VPU, USB, 263 MMC_MMC1I, MMC_MMC2I, MMC_MMC3I, 264 DMAC4, DMAC5, DMAC_DADERR, 265 SCIF, SCIFA1, SCIFA2, 266 DENC, MSIOF, 267 FLCTL_FLSTEI, FLCTL_FLENDI, FLCTL_FLTREQ0I, FLCTL_FLTREQ1I, 268 I2C_ALI, I2C_TACKI, I2C_WAITI, I2C_DTEI, 269 SDHI, CMT, TSIF, SIU, 270 TMU0, TMU1, TMU2, 271 VEU2, LCDC, 272 273 /* interrupt groups */ 274 275 DMAC0123, VIOVOU, MMC, DMAC45, FLCTL, I2C, 276 }; 277 278 static struct intc_vect vectors[] __initdata = { 279 INTC_VECT(IRQ0, 0x600), INTC_VECT(IRQ1, 0x620), 280 INTC_VECT(IRQ2, 0x640), INTC_VECT(IRQ3, 0x660), 281 INTC_VECT(IRQ4, 0x680), INTC_VECT(IRQ5, 0x6a0), 282 INTC_VECT(IRQ6, 0x6c0), INTC_VECT(IRQ7, 0x6e0), 283 INTC_VECT(ICB, 0x700), 284 INTC_VECT(DMAC0, 0x800), INTC_VECT(DMAC1, 0x820), 285 INTC_VECT(DMAC2, 0x840), INTC_VECT(DMAC3, 0x860), 286 INTC_VECT(VIO_CEUI, 0x880), INTC_VECT(VIO_BEUI, 0x8a0), 287 INTC_VECT(VIO_VEUI, 0x8c0), INTC_VECT(VOU, 0x8e0), 288 INTC_VECT(MFI, 0x900), INTC_VECT(VPU, 0x980), INTC_VECT(USB, 0xa20), 289 INTC_VECT(MMC_MMC1I, 0xb00), INTC_VECT(MMC_MMC2I, 0xb20), 290 INTC_VECT(MMC_MMC3I, 0xb40), 291 INTC_VECT(DMAC4, 0xb80), INTC_VECT(DMAC5, 0xba0), 292 INTC_VECT(DMAC_DADERR, 0xbc0), 293 INTC_VECT(SCIF, 0xc00), INTC_VECT(SCIFA1, 0xc20), 294 INTC_VECT(SCIFA2, 0xc40), 295 INTC_VECT(DENC, 0xc60), INTC_VECT(MSIOF, 0xc80), 296 INTC_VECT(FLCTL_FLSTEI, 0xd80), INTC_VECT(FLCTL_FLENDI, 0xda0), 297 INTC_VECT(FLCTL_FLTREQ0I, 0xdc0), INTC_VECT(FLCTL_FLTREQ1I, 0xde0), 298 INTC_VECT(I2C_ALI, 0xe00), INTC_VECT(I2C_TACKI, 0xe20), 299 INTC_VECT(I2C_WAITI, 0xe40), INTC_VECT(I2C_DTEI, 0xe60), 300 INTC_VECT(SDHI, 0xe80), INTC_VECT(SDHI, 0xea0), 301 INTC_VECT(SDHI, 0xec0), INTC_VECT(SDHI, 0xee0), 302 INTC_VECT(CMT, 0xf00), INTC_VECT(TSIF, 0xf20), 303 INTC_VECT(SIU, 0xf80), 304 INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420), 305 INTC_VECT(TMU2, 0x440), 306 INTC_VECT(VEU2, 0x560), INTC_VECT(LCDC, 0x580), 307 }; 308 309 static struct intc_group groups[] __initdata = { 310 INTC_GROUP(DMAC0123, DMAC0, DMAC1, DMAC2, DMAC3), 311 INTC_GROUP(VIOVOU, VIO_CEUI, VIO_BEUI, VIO_VEUI, VOU), 312 INTC_GROUP(MMC, MMC_MMC1I, MMC_MMC2I, MMC_MMC3I), 313 INTC_GROUP(DMAC45, DMAC4, DMAC5, DMAC_DADERR), 314 INTC_GROUP(FLCTL, FLCTL_FLSTEI, FLCTL_FLENDI, 315 FLCTL_FLTREQ0I, FLCTL_FLTREQ1I), 316 INTC_GROUP(I2C, I2C_ALI, I2C_TACKI, I2C_WAITI, I2C_DTEI), 317 }; 318 319 static struct intc_mask_reg mask_registers[] __initdata = { 320 { 0xa4080080, 0xa40800c0, 8, /* IMR0 / IMCR0 */ 321 { } }, 322 { 0xa4080084, 0xa40800c4, 8, /* IMR1 / IMCR1 */ 323 { VOU, VIO_VEUI, VIO_BEUI, VIO_CEUI, DMAC3, DMAC2, DMAC1, DMAC0 } }, 324 { 0xa4080088, 0xa40800c8, 8, /* IMR2 / IMCR2 */ 325 { 0, 0, 0, VPU, 0, 0, 0, MFI } }, 326 { 0xa408008c, 0xa40800cc, 8, /* IMR3 / IMCR3 */ 327 { 0, 0, 0, ICB } }, 328 { 0xa4080090, 0xa40800d0, 8, /* IMR4 / IMCR4 */ 329 { 0, TMU2, TMU1, TMU0, VEU2, 0, 0, LCDC } }, 330 { 0xa4080094, 0xa40800d4, 8, /* IMR5 / IMCR5 */ 331 { 0, DMAC_DADERR, DMAC5, DMAC4, DENC, SCIFA2, SCIFA1, SCIF } }, 332 { 0xa4080098, 0xa40800d8, 8, /* IMR6 / IMCR6 */ 333 { 0, 0, 0, 0, 0, 0, 0, MSIOF } }, 334 { 0xa408009c, 0xa40800dc, 8, /* IMR7 / IMCR7 */ 335 { I2C_DTEI, I2C_WAITI, I2C_TACKI, I2C_ALI, 336 FLCTL_FLTREQ1I, FLCTL_FLTREQ0I, FLCTL_FLENDI, FLCTL_FLSTEI } }, 337 { 0xa40800a0, 0xa40800e0, 8, /* IMR8 / IMCR8 */ 338 { DISABLED, ENABLED, ENABLED, ENABLED, 0, 0, 0, SIU } }, 339 { 0xa40800a4, 0xa40800e4, 8, /* IMR9 / IMCR9 */ 340 { 0, 0, 0, CMT, 0, USB, } }, 341 { 0xa40800a8, 0xa40800e8, 8, /* IMR10 / IMCR10 */ 342 { 0, MMC_MMC3I, MMC_MMC2I, MMC_MMC1I } }, 343 { 0xa40800ac, 0xa40800ec, 8, /* IMR11 / IMCR11 */ 344 { 0, 0, 0, 0, 0, 0, 0, TSIF } }, 345 { 0xa4140044, 0xa4140064, 8, /* INTMSK00 / INTMSKCLR00 */ 346 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } }, 347 }; 348 349 static struct intc_prio_reg prio_registers[] __initdata = { 350 { 0xa4080000, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2 } }, 351 { 0xa4080004, 0, 16, 4, /* IPRB */ { VEU2, LCDC, ICB } }, 352 { 0xa4080008, 0, 16, 4, /* IPRC */ { } }, 353 { 0xa408000c, 0, 16, 4, /* IPRD */ { } }, 354 { 0xa4080010, 0, 16, 4, /* IPRE */ { DMAC0123, VIOVOU, MFI, VPU } }, 355 { 0xa4080014, 0, 16, 4, /* IPRF */ { 0, DMAC45, USB, CMT } }, 356 { 0xa4080018, 0, 16, 4, /* IPRG */ { SCIF, SCIFA1, SCIFA2, DENC } }, 357 { 0xa408001c, 0, 16, 4, /* IPRH */ { MSIOF, 0, FLCTL, I2C } }, 358 { 0xa4080020, 0, 16, 4, /* IPRI */ { 0, 0, TSIF, } }, 359 { 0xa4080024, 0, 16, 4, /* IPRJ */ { 0, 0, SIU } }, 360 { 0xa4080028, 0, 16, 4, /* IPRK */ { 0, MMC, 0, SDHI } }, 361 { 0xa408002c, 0, 16, 4, /* IPRL */ { } }, 362 { 0xa4140010, 0, 32, 4, /* INTPRI00 */ 363 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } }, 364 }; 365 366 static struct intc_sense_reg sense_registers[] __initdata = { 367 { 0xa414001c, 16, 2, /* ICR1 */ 368 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } }, 369 }; 370 371 static struct intc_mask_reg ack_registers[] __initdata = { 372 { 0xa4140024, 0, 8, /* INTREQ00 */ 373 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } }, 374 }; 375 376 static struct intc_desc intc_desc __initdata = { 377 .name = "sh7366", 378 .force_enable = ENABLED, 379 .force_disable = DISABLED, 380 .hw = INTC_HW_DESC(vectors, groups, mask_registers, 381 prio_registers, sense_registers, ack_registers), 382 }; 383 384 void __init plat_irq_setup(void) 385 { 386 register_intc_controller(&intc_desc); 387 } 388 389 void __init plat_mem_setup(void) 390 { 391 /* TODO: Register Node 1 */ 392 } 393