1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * SH7366 Setup 4 * 5 * Copyright (C) 2008 Renesas Solutions 6 * 7 * Based on linux/arch/sh/kernel/cpu/sh4a/setup-sh7722.c 8 */ 9 #include <linux/platform_device.h> 10 #include <linux/init.h> 11 #include <linux/serial.h> 12 #include <linux/serial_sci.h> 13 #include <linux/uio_driver.h> 14 #include <linux/sh_timer.h> 15 #include <linux/sh_intc.h> 16 #include <linux/usb/r8a66597.h> 17 #include <asm/clock.h> 18 #include <asm/platform_early.h> 19 20 static struct plat_sci_port scif0_platform_data = { 21 .scscr = SCSCR_REIE, 22 .type = PORT_SCIF, 23 }; 24 25 static struct resource scif0_resources[] = { 26 DEFINE_RES_MEM(0xffe00000, 0x100), 27 DEFINE_RES_IRQ(evt2irq(0xc00)), 28 }; 29 30 static struct platform_device scif0_device = { 31 .name = "sh-sci", 32 .id = 0, 33 .resource = scif0_resources, 34 .num_resources = ARRAY_SIZE(scif0_resources), 35 .dev = { 36 .platform_data = &scif0_platform_data, 37 }, 38 }; 39 40 static struct resource iic_resources[] = { 41 [0] = { 42 .name = "IIC", 43 .start = 0x04470000, 44 .end = 0x04470017, 45 .flags = IORESOURCE_MEM, 46 }, 47 [1] = { 48 .start = evt2irq(0xe00), 49 .end = evt2irq(0xe60), 50 .flags = IORESOURCE_IRQ, 51 }, 52 }; 53 54 static struct platform_device iic_device = { 55 .name = "i2c-sh_mobile", 56 .id = 0, /* "i2c0" clock */ 57 .num_resources = ARRAY_SIZE(iic_resources), 58 .resource = iic_resources, 59 }; 60 61 static struct r8a66597_platdata r8a66597_data = { 62 .on_chip = 1, 63 }; 64 65 static struct resource usb_host_resources[] = { 66 [0] = { 67 .start = 0xa4d80000, 68 .end = 0xa4d800ff, 69 .flags = IORESOURCE_MEM, 70 }, 71 [1] = { 72 .start = evt2irq(0xa20), 73 .end = evt2irq(0xa20), 74 .flags = IORESOURCE_IRQ | IRQF_TRIGGER_LOW, 75 }, 76 }; 77 78 static struct platform_device usb_host_device = { 79 .name = "r8a66597_hcd", 80 .id = -1, 81 .dev = { 82 .dma_mask = NULL, 83 .coherent_dma_mask = 0xffffffff, 84 .platform_data = &r8a66597_data, 85 }, 86 .num_resources = ARRAY_SIZE(usb_host_resources), 87 .resource = usb_host_resources, 88 }; 89 90 static struct uio_info vpu_platform_data = { 91 .name = "VPU5", 92 .version = "0", 93 .irq = evt2irq(0x980), 94 }; 95 96 static struct resource vpu_resources[] = { 97 [0] = { 98 .name = "VPU", 99 .start = 0xfe900000, 100 .end = 0xfe902807, 101 .flags = IORESOURCE_MEM, 102 }, 103 [1] = { 104 /* place holder for contiguous memory */ 105 }, 106 }; 107 108 static struct platform_device vpu_device = { 109 .name = "uio_pdrv_genirq", 110 .id = 0, 111 .dev = { 112 .platform_data = &vpu_platform_data, 113 }, 114 .resource = vpu_resources, 115 .num_resources = ARRAY_SIZE(vpu_resources), 116 }; 117 118 static struct uio_info veu0_platform_data = { 119 .name = "VEU", 120 .version = "0", 121 .irq = evt2irq(0x8c0), 122 }; 123 124 static struct resource veu0_resources[] = { 125 [0] = { 126 .name = "VEU(1)", 127 .start = 0xfe920000, 128 .end = 0xfe9200b7, 129 .flags = IORESOURCE_MEM, 130 }, 131 [1] = { 132 /* place holder for contiguous memory */ 133 }, 134 }; 135 136 static struct platform_device veu0_device = { 137 .name = "uio_pdrv_genirq", 138 .id = 1, 139 .dev = { 140 .platform_data = &veu0_platform_data, 141 }, 142 .resource = veu0_resources, 143 .num_resources = ARRAY_SIZE(veu0_resources), 144 }; 145 146 static struct uio_info veu1_platform_data = { 147 .name = "VEU", 148 .version = "0", 149 .irq = evt2irq(0x560), 150 }; 151 152 static struct resource veu1_resources[] = { 153 [0] = { 154 .name = "VEU(2)", 155 .start = 0xfe924000, 156 .end = 0xfe9240b7, 157 .flags = IORESOURCE_MEM, 158 }, 159 [1] = { 160 /* place holder for contiguous memory */ 161 }, 162 }; 163 164 static struct platform_device veu1_device = { 165 .name = "uio_pdrv_genirq", 166 .id = 2, 167 .dev = { 168 .platform_data = &veu1_platform_data, 169 }, 170 .resource = veu1_resources, 171 .num_resources = ARRAY_SIZE(veu1_resources), 172 }; 173 174 static struct sh_timer_config cmt_platform_data = { 175 .channels_mask = 0x20, 176 }; 177 178 static struct resource cmt_resources[] = { 179 DEFINE_RES_MEM(0x044a0000, 0x70), 180 DEFINE_RES_IRQ(evt2irq(0xf00)), 181 }; 182 183 static struct platform_device cmt_device = { 184 .name = "sh-cmt-32", 185 .id = 0, 186 .dev = { 187 .platform_data = &cmt_platform_data, 188 }, 189 .resource = cmt_resources, 190 .num_resources = ARRAY_SIZE(cmt_resources), 191 }; 192 193 static struct sh_timer_config tmu0_platform_data = { 194 .channels_mask = 7, 195 }; 196 197 static struct resource tmu0_resources[] = { 198 DEFINE_RES_MEM(0xffd80000, 0x2c), 199 DEFINE_RES_IRQ(evt2irq(0x400)), 200 DEFINE_RES_IRQ(evt2irq(0x420)), 201 DEFINE_RES_IRQ(evt2irq(0x440)), 202 }; 203 204 static struct platform_device tmu0_device = { 205 .name = "sh-tmu", 206 .id = 0, 207 .dev = { 208 .platform_data = &tmu0_platform_data, 209 }, 210 .resource = tmu0_resources, 211 .num_resources = ARRAY_SIZE(tmu0_resources), 212 }; 213 214 static struct platform_device *sh7366_devices[] __initdata = { 215 &scif0_device, 216 &cmt_device, 217 &tmu0_device, 218 &iic_device, 219 &usb_host_device, 220 &vpu_device, 221 &veu0_device, 222 &veu1_device, 223 }; 224 225 static int __init sh7366_devices_setup(void) 226 { 227 platform_resource_setup_memory(&vpu_device, "vpu", 2 << 20); 228 platform_resource_setup_memory(&veu0_device, "veu0", 2 << 20); 229 platform_resource_setup_memory(&veu1_device, "veu1", 2 << 20); 230 231 return platform_add_devices(sh7366_devices, 232 ARRAY_SIZE(sh7366_devices)); 233 } 234 arch_initcall(sh7366_devices_setup); 235 236 static struct platform_device *sh7366_early_devices[] __initdata = { 237 &scif0_device, 238 &cmt_device, 239 &tmu0_device, 240 }; 241 242 void __init plat_early_device_setup(void) 243 { 244 sh_early_platform_add_devices(sh7366_early_devices, 245 ARRAY_SIZE(sh7366_early_devices)); 246 } 247 248 enum { 249 UNUSED=0, 250 ENABLED, 251 DISABLED, 252 253 /* interrupt sources */ 254 IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7, 255 ICB, 256 DMAC0, DMAC1, DMAC2, DMAC3, 257 VIO_CEUI, VIO_BEUI, VIO_VEUI, VOU, 258 MFI, VPU, USB, 259 MMC_MMC1I, MMC_MMC2I, MMC_MMC3I, 260 DMAC4, DMAC5, DMAC_DADERR, 261 SCIF, SCIFA1, SCIFA2, 262 DENC, MSIOF, 263 FLCTL_FLSTEI, FLCTL_FLENDI, FLCTL_FLTREQ0I, FLCTL_FLTREQ1I, 264 I2C_ALI, I2C_TACKI, I2C_WAITI, I2C_DTEI, 265 SDHI, CMT, TSIF, SIU, 266 TMU0, TMU1, TMU2, 267 VEU2, LCDC, 268 269 /* interrupt groups */ 270 271 DMAC0123, VIOVOU, MMC, DMAC45, FLCTL, I2C, 272 }; 273 274 static struct intc_vect vectors[] __initdata = { 275 INTC_VECT(IRQ0, 0x600), INTC_VECT(IRQ1, 0x620), 276 INTC_VECT(IRQ2, 0x640), INTC_VECT(IRQ3, 0x660), 277 INTC_VECT(IRQ4, 0x680), INTC_VECT(IRQ5, 0x6a0), 278 INTC_VECT(IRQ6, 0x6c0), INTC_VECT(IRQ7, 0x6e0), 279 INTC_VECT(ICB, 0x700), 280 INTC_VECT(DMAC0, 0x800), INTC_VECT(DMAC1, 0x820), 281 INTC_VECT(DMAC2, 0x840), INTC_VECT(DMAC3, 0x860), 282 INTC_VECT(VIO_CEUI, 0x880), INTC_VECT(VIO_BEUI, 0x8a0), 283 INTC_VECT(VIO_VEUI, 0x8c0), INTC_VECT(VOU, 0x8e0), 284 INTC_VECT(MFI, 0x900), INTC_VECT(VPU, 0x980), INTC_VECT(USB, 0xa20), 285 INTC_VECT(MMC_MMC1I, 0xb00), INTC_VECT(MMC_MMC2I, 0xb20), 286 INTC_VECT(MMC_MMC3I, 0xb40), 287 INTC_VECT(DMAC4, 0xb80), INTC_VECT(DMAC5, 0xba0), 288 INTC_VECT(DMAC_DADERR, 0xbc0), 289 INTC_VECT(SCIF, 0xc00), INTC_VECT(SCIFA1, 0xc20), 290 INTC_VECT(SCIFA2, 0xc40), 291 INTC_VECT(DENC, 0xc60), INTC_VECT(MSIOF, 0xc80), 292 INTC_VECT(FLCTL_FLSTEI, 0xd80), INTC_VECT(FLCTL_FLENDI, 0xda0), 293 INTC_VECT(FLCTL_FLTREQ0I, 0xdc0), INTC_VECT(FLCTL_FLTREQ1I, 0xde0), 294 INTC_VECT(I2C_ALI, 0xe00), INTC_VECT(I2C_TACKI, 0xe20), 295 INTC_VECT(I2C_WAITI, 0xe40), INTC_VECT(I2C_DTEI, 0xe60), 296 INTC_VECT(SDHI, 0xe80), INTC_VECT(SDHI, 0xea0), 297 INTC_VECT(SDHI, 0xec0), INTC_VECT(SDHI, 0xee0), 298 INTC_VECT(CMT, 0xf00), INTC_VECT(TSIF, 0xf20), 299 INTC_VECT(SIU, 0xf80), 300 INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420), 301 INTC_VECT(TMU2, 0x440), 302 INTC_VECT(VEU2, 0x560), INTC_VECT(LCDC, 0x580), 303 }; 304 305 static struct intc_group groups[] __initdata = { 306 INTC_GROUP(DMAC0123, DMAC0, DMAC1, DMAC2, DMAC3), 307 INTC_GROUP(VIOVOU, VIO_CEUI, VIO_BEUI, VIO_VEUI, VOU), 308 INTC_GROUP(MMC, MMC_MMC1I, MMC_MMC2I, MMC_MMC3I), 309 INTC_GROUP(DMAC45, DMAC4, DMAC5, DMAC_DADERR), 310 INTC_GROUP(FLCTL, FLCTL_FLSTEI, FLCTL_FLENDI, 311 FLCTL_FLTREQ0I, FLCTL_FLTREQ1I), 312 INTC_GROUP(I2C, I2C_ALI, I2C_TACKI, I2C_WAITI, I2C_DTEI), 313 }; 314 315 static struct intc_mask_reg mask_registers[] __initdata = { 316 { 0xa4080080, 0xa40800c0, 8, /* IMR0 / IMCR0 */ 317 { } }, 318 { 0xa4080084, 0xa40800c4, 8, /* IMR1 / IMCR1 */ 319 { VOU, VIO_VEUI, VIO_BEUI, VIO_CEUI, DMAC3, DMAC2, DMAC1, DMAC0 } }, 320 { 0xa4080088, 0xa40800c8, 8, /* IMR2 / IMCR2 */ 321 { 0, 0, 0, VPU, 0, 0, 0, MFI } }, 322 { 0xa408008c, 0xa40800cc, 8, /* IMR3 / IMCR3 */ 323 { 0, 0, 0, ICB } }, 324 { 0xa4080090, 0xa40800d0, 8, /* IMR4 / IMCR4 */ 325 { 0, TMU2, TMU1, TMU0, VEU2, 0, 0, LCDC } }, 326 { 0xa4080094, 0xa40800d4, 8, /* IMR5 / IMCR5 */ 327 { 0, DMAC_DADERR, DMAC5, DMAC4, DENC, SCIFA2, SCIFA1, SCIF } }, 328 { 0xa4080098, 0xa40800d8, 8, /* IMR6 / IMCR6 */ 329 { 0, 0, 0, 0, 0, 0, 0, MSIOF } }, 330 { 0xa408009c, 0xa40800dc, 8, /* IMR7 / IMCR7 */ 331 { I2C_DTEI, I2C_WAITI, I2C_TACKI, I2C_ALI, 332 FLCTL_FLTREQ1I, FLCTL_FLTREQ0I, FLCTL_FLENDI, FLCTL_FLSTEI } }, 333 { 0xa40800a0, 0xa40800e0, 8, /* IMR8 / IMCR8 */ 334 { DISABLED, ENABLED, ENABLED, ENABLED, 0, 0, 0, SIU } }, 335 { 0xa40800a4, 0xa40800e4, 8, /* IMR9 / IMCR9 */ 336 { 0, 0, 0, CMT, 0, USB, } }, 337 { 0xa40800a8, 0xa40800e8, 8, /* IMR10 / IMCR10 */ 338 { 0, MMC_MMC3I, MMC_MMC2I, MMC_MMC1I } }, 339 { 0xa40800ac, 0xa40800ec, 8, /* IMR11 / IMCR11 */ 340 { 0, 0, 0, 0, 0, 0, 0, TSIF } }, 341 { 0xa4140044, 0xa4140064, 8, /* INTMSK00 / INTMSKCLR00 */ 342 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } }, 343 }; 344 345 static struct intc_prio_reg prio_registers[] __initdata = { 346 { 0xa4080000, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2 } }, 347 { 0xa4080004, 0, 16, 4, /* IPRB */ { VEU2, LCDC, ICB } }, 348 { 0xa4080008, 0, 16, 4, /* IPRC */ { } }, 349 { 0xa408000c, 0, 16, 4, /* IPRD */ { } }, 350 { 0xa4080010, 0, 16, 4, /* IPRE */ { DMAC0123, VIOVOU, MFI, VPU } }, 351 { 0xa4080014, 0, 16, 4, /* IPRF */ { 0, DMAC45, USB, CMT } }, 352 { 0xa4080018, 0, 16, 4, /* IPRG */ { SCIF, SCIFA1, SCIFA2, DENC } }, 353 { 0xa408001c, 0, 16, 4, /* IPRH */ { MSIOF, 0, FLCTL, I2C } }, 354 { 0xa4080020, 0, 16, 4, /* IPRI */ { 0, 0, TSIF, } }, 355 { 0xa4080024, 0, 16, 4, /* IPRJ */ { 0, 0, SIU } }, 356 { 0xa4080028, 0, 16, 4, /* IPRK */ { 0, MMC, 0, SDHI } }, 357 { 0xa408002c, 0, 16, 4, /* IPRL */ { } }, 358 { 0xa4140010, 0, 32, 4, /* INTPRI00 */ 359 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } }, 360 }; 361 362 static struct intc_sense_reg sense_registers[] __initdata = { 363 { 0xa414001c, 16, 2, /* ICR1 */ 364 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } }, 365 }; 366 367 static struct intc_mask_reg ack_registers[] __initdata = { 368 { 0xa4140024, 0, 8, /* INTREQ00 */ 369 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } }, 370 }; 371 372 static struct intc_desc intc_desc __initdata = { 373 .name = "sh7366", 374 .force_enable = ENABLED, 375 .force_disable = DISABLED, 376 .hw = INTC_HW_DESC(vectors, groups, mask_registers, 377 prio_registers, sense_registers, ack_registers), 378 }; 379 380 void __init plat_irq_setup(void) 381 { 382 register_intc_controller(&intc_desc); 383 } 384 385 void __init plat_mem_setup(void) 386 { 387 /* TODO: Register Node 1 */ 388 } 389