1 /* 2 * SH7343 Setup 3 * 4 * Copyright (C) 2006 Paul Mundt 5 * 6 * This file is subject to the terms and conditions of the GNU General Public 7 * License. See the file "COPYING" in the main directory of this archive 8 * for more details. 9 */ 10 #include <linux/platform_device.h> 11 #include <linux/init.h> 12 #include <linux/serial.h> 13 #include <linux/serial_sci.h> 14 #include <linux/uio_driver.h> 15 #include <asm/clock.h> 16 17 static struct resource iic0_resources[] = { 18 [0] = { 19 .name = "IIC0", 20 .start = 0x04470000, 21 .end = 0x04470017, 22 .flags = IORESOURCE_MEM, 23 }, 24 [1] = { 25 .start = 96, 26 .end = 99, 27 .flags = IORESOURCE_IRQ, 28 }, 29 }; 30 31 static struct platform_device iic0_device = { 32 .name = "i2c-sh_mobile", 33 .id = 0, /* "i2c0" clock */ 34 .num_resources = ARRAY_SIZE(iic0_resources), 35 .resource = iic0_resources, 36 }; 37 38 static struct resource iic1_resources[] = { 39 [0] = { 40 .name = "IIC1", 41 .start = 0x04750000, 42 .end = 0x04750017, 43 .flags = IORESOURCE_MEM, 44 }, 45 [1] = { 46 .start = 44, 47 .end = 47, 48 .flags = IORESOURCE_IRQ, 49 }, 50 }; 51 52 static struct platform_device iic1_device = { 53 .name = "i2c-sh_mobile", 54 .id = 1, /* "i2c1" clock */ 55 .num_resources = ARRAY_SIZE(iic1_resources), 56 .resource = iic1_resources, 57 }; 58 59 static struct uio_info vpu_platform_data = { 60 .name = "VPU4", 61 .version = "0", 62 .irq = 60, 63 }; 64 65 static struct resource vpu_resources[] = { 66 [0] = { 67 .name = "VPU", 68 .start = 0xfe900000, 69 .end = 0xfe9022eb, 70 .flags = IORESOURCE_MEM, 71 }, 72 [1] = { 73 /* place holder for contiguous memory */ 74 }, 75 }; 76 77 static struct platform_device vpu_device = { 78 .name = "uio_pdrv_genirq", 79 .id = 0, 80 .dev = { 81 .platform_data = &vpu_platform_data, 82 }, 83 .resource = vpu_resources, 84 .num_resources = ARRAY_SIZE(vpu_resources), 85 }; 86 87 static struct uio_info veu_platform_data = { 88 .name = "VEU", 89 .version = "0", 90 .irq = 54, 91 }; 92 93 static struct resource veu_resources[] = { 94 [0] = { 95 .name = "VEU", 96 .start = 0xfe920000, 97 .end = 0xfe9200b7, 98 .flags = IORESOURCE_MEM, 99 }, 100 [1] = { 101 /* place holder for contiguous memory */ 102 }, 103 }; 104 105 static struct platform_device veu_device = { 106 .name = "uio_pdrv_genirq", 107 .id = 1, 108 .dev = { 109 .platform_data = &veu_platform_data, 110 }, 111 .resource = veu_resources, 112 .num_resources = ARRAY_SIZE(veu_resources), 113 }; 114 115 static struct plat_sci_port sci_platform_data[] = { 116 { 117 .mapbase = 0xffe00000, 118 .flags = UPF_BOOT_AUTOCONF, 119 .type = PORT_SCIF, 120 .irqs = { 80, 80, 80, 80 }, 121 }, { 122 .mapbase = 0xffe10000, 123 .flags = UPF_BOOT_AUTOCONF, 124 .type = PORT_SCIF, 125 .irqs = { 81, 81, 81, 81 }, 126 }, { 127 .mapbase = 0xffe20000, 128 .flags = UPF_BOOT_AUTOCONF, 129 .type = PORT_SCIF, 130 .irqs = { 82, 82, 82, 82 }, 131 }, { 132 .mapbase = 0xffe30000, 133 .flags = UPF_BOOT_AUTOCONF, 134 .type = PORT_SCIF, 135 .irqs = { 83, 83, 83, 83 }, 136 }, { 137 .flags = 0, 138 } 139 }; 140 141 static struct platform_device sci_device = { 142 .name = "sh-sci", 143 .id = -1, 144 .dev = { 145 .platform_data = sci_platform_data, 146 }, 147 }; 148 149 static struct platform_device *sh7343_devices[] __initdata = { 150 &iic0_device, 151 &iic1_device, 152 &sci_device, 153 &vpu_device, 154 &veu_device, 155 }; 156 157 static int __init sh7343_devices_setup(void) 158 { 159 clk_always_enable("uram0"); /* URAM */ 160 clk_always_enable("xymem0"); /* XYMEM */ 161 clk_always_enable("veu0"); /* VEU */ 162 clk_always_enable("vpu0"); /* VPU */ 163 164 platform_resource_setup_memory(&vpu_device, "vpu", 1 << 20); 165 platform_resource_setup_memory(&veu_device, "veu", 2 << 20); 166 167 return platform_add_devices(sh7343_devices, 168 ARRAY_SIZE(sh7343_devices)); 169 } 170 __initcall(sh7343_devices_setup); 171 172 enum { 173 UNUSED = 0, 174 175 /* interrupt sources */ 176 IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7, 177 DMAC0, DMAC1, DMAC2, DMAC3, 178 VIO_CEUI, VIO_BEUI, VIO_VEUI, VOU, 179 MFI, VPU, TPU, Z3D4, USBI0, USBI1, 180 MMC_ERR, MMC_TRAN, MMC_FSTAT, MMC_FRDY, 181 DMAC4, DMAC5, DMAC_DADERR, 182 KEYSC, 183 SCIF, SCIF1, SCIF2, SCIF3, 184 SIOF0, SIOF1, SIO, 185 FLCTL_FLSTEI, FLCTL_FLENDI, FLCTL_FLTREQ0I, FLCTL_FLTREQ1I, 186 I2C0_ALI, I2C0_TACKI, I2C0_WAITI, I2C0_DTEI, 187 I2C1_ALI, I2C1_TACKI, I2C1_WAITI, I2C1_DTEI, 188 SIM_TEI, SIM_TXI, SIM_RXI, SIM_ERI, 189 IRDA, 190 SDHI0, SDHI1, SDHI2, SDHI3, 191 CMT, TSIF, SIU, 192 TMU0, TMU1, TMU2, 193 JPU, LCDC, 194 195 /* interrupt groups */ 196 197 DMAC0123, VIOVOU, MMC, DMAC45, FLCTL, I2C0, I2C1, SIM, SDHI, USB, 198 }; 199 200 static struct intc_vect vectors[] __initdata = { 201 INTC_VECT(IRQ0, 0x600), INTC_VECT(IRQ1, 0x620), 202 INTC_VECT(IRQ2, 0x640), INTC_VECT(IRQ3, 0x660), 203 INTC_VECT(IRQ4, 0x680), INTC_VECT(IRQ5, 0x6a0), 204 INTC_VECT(IRQ6, 0x6c0), INTC_VECT(IRQ7, 0x6e0), 205 INTC_VECT(I2C1_ALI, 0x780), INTC_VECT(I2C1_TACKI, 0x7a0), 206 INTC_VECT(I2C1_WAITI, 0x7c0), INTC_VECT(I2C1_DTEI, 0x7e0), 207 INTC_VECT(DMAC0, 0x800), INTC_VECT(DMAC1, 0x820), 208 INTC_VECT(DMAC2, 0x840), INTC_VECT(DMAC3, 0x860), 209 INTC_VECT(VIO_CEUI, 0x880), INTC_VECT(VIO_BEUI, 0x8a0), 210 INTC_VECT(VIO_VEUI, 0x8c0), INTC_VECT(VOU, 0x8e0), 211 INTC_VECT(MFI, 0x900), INTC_VECT(VPU, 0x980), 212 INTC_VECT(TPU, 0x9a0), INTC_VECT(Z3D4, 0x9e0), 213 INTC_VECT(USBI0, 0xa20), INTC_VECT(USBI1, 0xa40), 214 INTC_VECT(MMC_ERR, 0xb00), INTC_VECT(MMC_TRAN, 0xb20), 215 INTC_VECT(MMC_FSTAT, 0xb40), INTC_VECT(MMC_FRDY, 0xb60), 216 INTC_VECT(DMAC4, 0xb80), INTC_VECT(DMAC5, 0xba0), 217 INTC_VECT(DMAC_DADERR, 0xbc0), INTC_VECT(KEYSC, 0xbe0), 218 INTC_VECT(SCIF, 0xc00), INTC_VECT(SCIF1, 0xc20), 219 INTC_VECT(SCIF2, 0xc40), INTC_VECT(SCIF3, 0xc60), 220 INTC_VECT(SIOF0, 0xc80), INTC_VECT(SIOF1, 0xca0), 221 INTC_VECT(SIO, 0xd00), 222 INTC_VECT(FLCTL_FLSTEI, 0xd80), INTC_VECT(FLCTL_FLENDI, 0xda0), 223 INTC_VECT(FLCTL_FLTREQ0I, 0xdc0), INTC_VECT(FLCTL_FLTREQ1I, 0xde0), 224 INTC_VECT(I2C0_ALI, 0xe00), INTC_VECT(I2C0_TACKI, 0xe20), 225 INTC_VECT(I2C0_WAITI, 0xe40), INTC_VECT(I2C0_DTEI, 0xe60), 226 INTC_VECT(SDHI0, 0xe80), INTC_VECT(SDHI1, 0xea0), 227 INTC_VECT(SDHI2, 0xec0), INTC_VECT(SDHI3, 0xee0), 228 INTC_VECT(CMT, 0xf00), INTC_VECT(TSIF, 0xf20), 229 INTC_VECT(SIU, 0xf80), 230 INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420), 231 INTC_VECT(TMU2, 0x440), 232 INTC_VECT(JPU, 0x560), INTC_VECT(LCDC, 0x580), 233 }; 234 235 static struct intc_group groups[] __initdata = { 236 INTC_GROUP(DMAC0123, DMAC0, DMAC1, DMAC2, DMAC3), 237 INTC_GROUP(VIOVOU, VIO_CEUI, VIO_BEUI, VIO_VEUI, VOU), 238 INTC_GROUP(MMC, MMC_FRDY, MMC_FSTAT, MMC_TRAN, MMC_ERR), 239 INTC_GROUP(DMAC45, DMAC4, DMAC5, DMAC_DADERR), 240 INTC_GROUP(FLCTL, FLCTL_FLSTEI, FLCTL_FLENDI, 241 FLCTL_FLTREQ0I, FLCTL_FLTREQ1I), 242 INTC_GROUP(I2C0, I2C0_ALI, I2C0_TACKI, I2C0_WAITI, I2C0_DTEI), 243 INTC_GROUP(I2C1, I2C1_ALI, I2C1_TACKI, I2C1_WAITI, I2C1_DTEI), 244 INTC_GROUP(SIM, SIM_TEI, SIM_TXI, SIM_RXI, SIM_ERI), 245 INTC_GROUP(SDHI, SDHI0, SDHI1, SDHI2, SDHI3), 246 INTC_GROUP(USB, USBI0, USBI1), 247 }; 248 249 static struct intc_mask_reg mask_registers[] __initdata = { 250 { 0xa4080084, 0xa40800c4, 8, /* IMR1 / IMCR1 */ 251 { VOU, VIO_VEUI, VIO_BEUI, VIO_CEUI, DMAC3, DMAC2, DMAC1, DMAC0 } }, 252 { 0xa4080088, 0xa40800c8, 8, /* IMR2 / IMCR2 */ 253 { 0, 0, 0, VPU, 0, 0, 0, MFI } }, 254 { 0xa408008c, 0xa40800cc, 8, /* IMR3 / IMCR3 */ 255 { SIM_TEI, SIM_TXI, SIM_RXI, SIM_ERI, 0, 0, 0, IRDA } }, 256 { 0xa4080090, 0xa40800d0, 8, /* IMR4 / IMCR4 */ 257 { 0, TMU2, TMU1, TMU0, JPU, 0, 0, LCDC } }, 258 { 0xa4080094, 0xa40800d4, 8, /* IMR5 / IMCR5 */ 259 { KEYSC, DMAC_DADERR, DMAC5, DMAC4, SCIF3, SCIF2, SCIF1, SCIF } }, 260 { 0xa4080098, 0xa40800d8, 8, /* IMR6 / IMCR6 */ 261 { 0, 0, 0, SIO, Z3D4, 0, SIOF1, SIOF0 } }, 262 { 0xa408009c, 0xa40800dc, 8, /* IMR7 / IMCR7 */ 263 { I2C0_DTEI, I2C0_WAITI, I2C0_TACKI, I2C0_ALI, 264 FLCTL_FLTREQ1I, FLCTL_FLTREQ0I, FLCTL_FLENDI, FLCTL_FLSTEI } }, 265 { 0xa40800a0, 0xa40800e0, 8, /* IMR8 / IMCR8 */ 266 { SDHI3, SDHI2, SDHI1, SDHI0, 0, 0, 0, SIU } }, 267 { 0xa40800a4, 0xa40800e4, 8, /* IMR9 / IMCR9 */ 268 { 0, 0, 0, CMT, 0, USBI1, USBI0 } }, 269 { 0xa40800a8, 0xa40800e8, 8, /* IMR10 / IMCR10 */ 270 { MMC_FRDY, MMC_FSTAT, MMC_TRAN, MMC_ERR } }, 271 { 0xa40800ac, 0xa40800ec, 8, /* IMR11 / IMCR11 */ 272 { I2C1_DTEI, I2C1_WAITI, I2C1_TACKI, I2C1_ALI, TPU, 0, 0, TSIF } }, 273 { 0xa4140044, 0xa4140064, 8, /* INTMSK00 / INTMSKCLR00 */ 274 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } }, 275 }; 276 277 static struct intc_prio_reg prio_registers[] __initdata = { 278 { 0xa4080000, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2 } }, 279 { 0xa4080004, 0, 16, 4, /* IPRB */ { JPU, LCDC, SIM } }, 280 { 0xa4080010, 0, 16, 4, /* IPRE */ { DMAC0123, VIOVOU, MFI, VPU } }, 281 { 0xa4080014, 0, 16, 4, /* IPRF */ { KEYSC, DMAC45, USB, CMT } }, 282 { 0xa4080018, 0, 16, 4, /* IPRG */ { SCIF, SCIF1, SCIF2, SCIF3 } }, 283 { 0xa408001c, 0, 16, 4, /* IPRH */ { SIOF0, SIOF1, FLCTL, I2C0 } }, 284 { 0xa4080020, 0, 16, 4, /* IPRI */ { SIO, 0, TSIF, I2C1 } }, 285 { 0xa4080024, 0, 16, 4, /* IPRJ */ { Z3D4, 0, SIU } }, 286 { 0xa4080028, 0, 16, 4, /* IPRK */ { 0, MMC, 0, SDHI } }, 287 { 0xa408002c, 0, 16, 4, /* IPRL */ { 0, 0, TPU } }, 288 { 0xa4140010, 0, 32, 4, /* INTPRI00 */ 289 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } }, 290 }; 291 292 static struct intc_sense_reg sense_registers[] __initdata = { 293 { 0xa414001c, 16, 2, /* ICR1 */ 294 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } }, 295 }; 296 297 static struct intc_mask_reg ack_registers[] __initdata = { 298 { 0xa4140024, 0, 8, /* INTREQ00 */ 299 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } }, 300 }; 301 302 static DECLARE_INTC_DESC_ACK(intc_desc, "sh7343", vectors, groups, 303 mask_registers, prio_registers, sense_registers, 304 ack_registers); 305 306 void __init plat_irq_setup(void) 307 { 308 register_intc_controller(&intc_desc); 309 } 310