1 /* 2 * arch/sh/kernel/cpu/sh4a/clock-sh7785.c 3 * 4 * SH7785 support for the clock framework 5 * 6 * Copyright (C) 2007 - 2010 Paul Mundt 7 * 8 * This file is subject to the terms and conditions of the GNU General Public 9 * License. See the file "COPYING" in the main directory of this archive 10 * for more details. 11 */ 12 #include <linux/init.h> 13 #include <linux/kernel.h> 14 #include <linux/clk.h> 15 #include <linux/io.h> 16 #include <linux/cpufreq.h> 17 #include <linux/clkdev.h> 18 #include <asm/clock.h> 19 #include <asm/freq.h> 20 #include <cpu/sh7785.h> 21 22 /* 23 * Default rate for the root input clock, reset this with clk_set_rate() 24 * from the platform code. 25 */ 26 static struct clk extal_clk = { 27 .rate = 33333333, 28 }; 29 30 static unsigned long pll_recalc(struct clk *clk) 31 { 32 int multiplier; 33 34 multiplier = test_mode_pin(MODE_PIN4) ? 36 : 72; 35 36 return clk->parent->rate * multiplier; 37 } 38 39 static struct sh_clk_ops pll_clk_ops = { 40 .recalc = pll_recalc, 41 }; 42 43 static struct clk pll_clk = { 44 .ops = &pll_clk_ops, 45 .parent = &extal_clk, 46 .flags = CLK_ENABLE_ON_INIT, 47 }; 48 49 static struct clk *clks[] = { 50 &extal_clk, 51 &pll_clk, 52 }; 53 54 static unsigned int div2[] = { 1, 2, 4, 6, 8, 12, 16, 18, 55 24, 32, 36, 48 }; 56 57 static struct clk_div_mult_table div4_div_mult_table = { 58 .divisors = div2, 59 .nr_divisors = ARRAY_SIZE(div2), 60 }; 61 62 static struct clk_div4_table div4_table = { 63 .div_mult_table = &div4_div_mult_table, 64 }; 65 66 enum { DIV4_I, DIV4_U, DIV4_SH, DIV4_B, DIV4_DDR, DIV4_GA, 67 DIV4_DU, DIV4_P, DIV4_NR }; 68 69 #define DIV4(_bit, _mask, _flags) \ 70 SH_CLK_DIV4(&pll_clk, FRQMR1, _bit, _mask, _flags) 71 72 struct clk div4_clks[DIV4_NR] = { 73 [DIV4_P] = DIV4(0, 0x0f80, 0), 74 [DIV4_DU] = DIV4(4, 0x0ff0, 0), 75 [DIV4_GA] = DIV4(8, 0x0030, 0), 76 [DIV4_DDR] = DIV4(12, 0x000c, CLK_ENABLE_ON_INIT), 77 [DIV4_B] = DIV4(16, 0x0fe0, CLK_ENABLE_ON_INIT), 78 [DIV4_SH] = DIV4(20, 0x000c, CLK_ENABLE_ON_INIT), 79 [DIV4_U] = DIV4(24, 0x000c, CLK_ENABLE_ON_INIT), 80 [DIV4_I] = DIV4(28, 0x000e, CLK_ENABLE_ON_INIT), 81 }; 82 83 #define MSTPCR0 0xffc80030 84 #define MSTPCR1 0xffc80034 85 86 enum { MSTP029, MSTP028, MSTP027, MSTP026, MSTP025, MSTP024, 87 MSTP021, MSTP020, MSTP017, MSTP016, 88 MSTP013, MSTP012, MSTP009, MSTP008, MSTP003, MSTP002, 89 MSTP119, MSTP117, MSTP105, MSTP104, MSTP100, 90 MSTP_NR }; 91 92 static struct clk mstp_clks[MSTP_NR] = { 93 /* MSTPCR0 */ 94 [MSTP029] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 29, 0), 95 [MSTP028] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 28, 0), 96 [MSTP027] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 27, 0), 97 [MSTP026] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 26, 0), 98 [MSTP025] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 25, 0), 99 [MSTP024] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 24, 0), 100 [MSTP021] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 21, 0), 101 [MSTP020] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 20, 0), 102 [MSTP017] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 17, 0), 103 [MSTP016] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 16, 0), 104 [MSTP013] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 13, 0), 105 [MSTP012] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 12, 0), 106 [MSTP009] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 9, 0), 107 [MSTP008] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 8, 0), 108 [MSTP003] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 3, 0), 109 [MSTP002] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 2, 0), 110 111 /* MSTPCR1 */ 112 [MSTP119] = SH_CLK_MSTP32(NULL, MSTPCR1, 19, 0), 113 [MSTP117] = SH_CLK_MSTP32(NULL, MSTPCR1, 17, 0), 114 [MSTP105] = SH_CLK_MSTP32(NULL, MSTPCR1, 5, 0), 115 [MSTP104] = SH_CLK_MSTP32(NULL, MSTPCR1, 4, 0), 116 [MSTP100] = SH_CLK_MSTP32(NULL, MSTPCR1, 0, 0), 117 }; 118 119 static struct clk_lookup lookups[] = { 120 /* main clocks */ 121 CLKDEV_CON_ID("extal", &extal_clk), 122 CLKDEV_CON_ID("pll_clk", &pll_clk), 123 124 /* DIV4 clocks */ 125 CLKDEV_CON_ID("peripheral_clk", &div4_clks[DIV4_P]), 126 CLKDEV_CON_ID("du_clk", &div4_clks[DIV4_DU]), 127 CLKDEV_CON_ID("ga_clk", &div4_clks[DIV4_GA]), 128 CLKDEV_CON_ID("ddr_clk", &div4_clks[DIV4_DDR]), 129 CLKDEV_CON_ID("bus_clk", &div4_clks[DIV4_B]), 130 CLKDEV_CON_ID("shyway_clk", &div4_clks[DIV4_SH]), 131 CLKDEV_CON_ID("umem_clk", &div4_clks[DIV4_U]), 132 CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]), 133 134 /* MSTP32 clocks */ 135 CLKDEV_ICK_ID("sci_fck", "sh-sci.5", &mstp_clks[MSTP029]), 136 CLKDEV_ICK_ID("sci_fck", "sh-sci.4", &mstp_clks[MSTP028]), 137 CLKDEV_ICK_ID("sci_fck", "sh-sci.3", &mstp_clks[MSTP027]), 138 CLKDEV_ICK_ID("sci_fck", "sh-sci.2", &mstp_clks[MSTP026]), 139 CLKDEV_ICK_ID("sci_fck", "sh-sci.1", &mstp_clks[MSTP025]), 140 CLKDEV_ICK_ID("sci_fck", "sh-sci.0", &mstp_clks[MSTP024]), 141 142 CLKDEV_CON_ID("ssi1_fck", &mstp_clks[MSTP021]), 143 CLKDEV_CON_ID("ssi0_fck", &mstp_clks[MSTP020]), 144 CLKDEV_CON_ID("hac1_fck", &mstp_clks[MSTP017]), 145 CLKDEV_CON_ID("hac0_fck", &mstp_clks[MSTP016]), 146 CLKDEV_CON_ID("mmcif_fck", &mstp_clks[MSTP013]), 147 CLKDEV_CON_ID("flctl_fck", &mstp_clks[MSTP012]), 148 149 CLKDEV_ICK_ID("fck", "sh-tmu.0", &mstp_clks[MSTP008]), 150 CLKDEV_ICK_ID("fck", "sh-tmu.1", &mstp_clks[MSTP009]), 151 152 CLKDEV_CON_ID("siof_fck", &mstp_clks[MSTP003]), 153 CLKDEV_CON_ID("hspi_fck", &mstp_clks[MSTP002]), 154 CLKDEV_CON_ID("hudi_fck", &mstp_clks[MSTP119]), 155 CLKDEV_CON_ID("ubc0", &mstp_clks[MSTP117]), 156 CLKDEV_CON_ID("dmac_11_6_fck", &mstp_clks[MSTP105]), 157 CLKDEV_CON_ID("dmac_5_0_fck", &mstp_clks[MSTP104]), 158 CLKDEV_CON_ID("gdta_fck", &mstp_clks[MSTP100]), 159 }; 160 161 int __init arch_clk_init(void) 162 { 163 int i, ret = 0; 164 165 for (i = 0; i < ARRAY_SIZE(clks); i++) 166 ret |= clk_register(clks[i]); 167 168 clkdev_add_table(lookups, ARRAY_SIZE(lookups)); 169 170 if (!ret) 171 ret = sh_clk_div4_register(div4_clks, ARRAY_SIZE(div4_clks), 172 &div4_table); 173 if (!ret) 174 ret = sh_clk_mstp_register(mstp_clks, MSTP_NR); 175 176 return ret; 177 } 178