1 /* 2 * arch/sh/kernel/cpu/sh4a/clock-sh7770.c 3 * 4 * SH7770 support for the clock framework 5 * 6 * Copyright (C) 2005 Paul Mundt 7 * 8 * This file is subject to the terms and conditions of the GNU General Public 9 * License. See the file "COPYING" in the main directory of this archive 10 * for more details. 11 */ 12 #include <linux/init.h> 13 #include <linux/kernel.h> 14 #include <asm/clock.h> 15 #include <asm/freq.h> 16 #include <asm/io.h> 17 18 static int ifc_divisors[] = { 1, 1, 1, 1, 1, 1, 1, 1 }; 19 static int bfc_divisors[] = { 1, 1, 1, 1, 1, 8,12, 1 }; 20 static int pfc_divisors[] = { 1, 8, 1,10,12,16, 1, 1 }; 21 22 static void master_clk_init(struct clk *clk) 23 { 24 clk->rate *= pfc_divisors[(__raw_readl(FRQCR) >> 28) & 0x000f]; 25 } 26 27 static struct sh_clk_ops sh7770_master_clk_ops = { 28 .init = master_clk_init, 29 }; 30 31 static unsigned long module_clk_recalc(struct clk *clk) 32 { 33 int idx = ((__raw_readl(FRQCR) >> 28) & 0x000f); 34 return clk->parent->rate / pfc_divisors[idx]; 35 } 36 37 static struct sh_clk_ops sh7770_module_clk_ops = { 38 .recalc = module_clk_recalc, 39 }; 40 41 static unsigned long bus_clk_recalc(struct clk *clk) 42 { 43 int idx = (__raw_readl(FRQCR) & 0x000f); 44 return clk->parent->rate / bfc_divisors[idx]; 45 } 46 47 static struct sh_clk_ops sh7770_bus_clk_ops = { 48 .recalc = bus_clk_recalc, 49 }; 50 51 static unsigned long cpu_clk_recalc(struct clk *clk) 52 { 53 int idx = ((__raw_readl(FRQCR) >> 24) & 0x000f); 54 return clk->parent->rate / ifc_divisors[idx]; 55 } 56 57 static struct sh_clk_ops sh7770_cpu_clk_ops = { 58 .recalc = cpu_clk_recalc, 59 }; 60 61 static struct sh_clk_ops *sh7770_clk_ops[] = { 62 &sh7770_master_clk_ops, 63 &sh7770_module_clk_ops, 64 &sh7770_bus_clk_ops, 65 &sh7770_cpu_clk_ops, 66 }; 67 68 void __init arch_init_clk_ops(struct sh_clk_ops **ops, int idx) 69 { 70 if (idx < ARRAY_SIZE(sh7770_clk_ops)) 71 *ops = sh7770_clk_ops[idx]; 72 } 73 74