1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * arch/sh/kernel/cpu/sh4a/clock-sh7723.c 4 * 5 * SH7723 clock framework support 6 * 7 * Copyright (C) 2009 Magnus Damm 8 */ 9 #include <linux/init.h> 10 #include <linux/kernel.h> 11 #include <linux/io.h> 12 #include <linux/clk.h> 13 #include <linux/clkdev.h> 14 #include <linux/sh_clk.h> 15 #include <asm/clock.h> 16 #include <cpu/sh7723.h> 17 18 /* SH7723 registers */ 19 #define FRQCR 0xa4150000 20 #define VCLKCR 0xa4150004 21 #define SCLKACR 0xa4150008 22 #define SCLKBCR 0xa415000c 23 #define IRDACLKCR 0xa4150018 24 #define PLLCR 0xa4150024 25 #define MSTPCR0 0xa4150030 26 #define MSTPCR1 0xa4150034 27 #define MSTPCR2 0xa4150038 28 #define DLLFRQ 0xa4150050 29 30 /* Fixed 32 KHz root clock for RTC and Power Management purposes */ 31 static struct clk r_clk = { 32 .rate = 32768, 33 }; 34 35 /* 36 * Default rate for the root input clock, reset this with clk_set_rate() 37 * from the platform code. 38 */ 39 struct clk extal_clk = { 40 .rate = 33333333, 41 }; 42 43 /* The dll multiplies the 32khz r_clk, may be used instead of extal */ 44 static unsigned long dll_recalc(struct clk *clk) 45 { 46 unsigned long mult; 47 48 if (__raw_readl(PLLCR) & 0x1000) 49 mult = __raw_readl(DLLFRQ); 50 else 51 mult = 0; 52 53 return clk->parent->rate * mult; 54 } 55 56 static struct sh_clk_ops dll_clk_ops = { 57 .recalc = dll_recalc, 58 }; 59 60 static struct clk dll_clk = { 61 .ops = &dll_clk_ops, 62 .parent = &r_clk, 63 .flags = CLK_ENABLE_ON_INIT, 64 }; 65 66 static unsigned long pll_recalc(struct clk *clk) 67 { 68 unsigned long mult = 1; 69 unsigned long div = 1; 70 71 if (__raw_readl(PLLCR) & 0x4000) 72 mult = (((__raw_readl(FRQCR) >> 24) & 0x1f) + 1); 73 else 74 div = 2; 75 76 return (clk->parent->rate * mult) / div; 77 } 78 79 static struct sh_clk_ops pll_clk_ops = { 80 .recalc = pll_recalc, 81 }; 82 83 static struct clk pll_clk = { 84 .ops = &pll_clk_ops, 85 .flags = CLK_ENABLE_ON_INIT, 86 }; 87 88 struct clk *main_clks[] = { 89 &r_clk, 90 &extal_clk, 91 &dll_clk, 92 &pll_clk, 93 }; 94 95 static int multipliers[] = { 1, 2, 1, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1 }; 96 static int divisors[] = { 1, 3, 2, 5, 3, 4, 5, 6, 8, 10, 12, 16, 20 }; 97 98 static struct clk_div_mult_table div4_div_mult_table = { 99 .divisors = divisors, 100 .nr_divisors = ARRAY_SIZE(divisors), 101 .multipliers = multipliers, 102 .nr_multipliers = ARRAY_SIZE(multipliers), 103 }; 104 105 static struct clk_div4_table div4_table = { 106 .div_mult_table = &div4_div_mult_table, 107 }; 108 109 enum { DIV4_I, DIV4_U, DIV4_SH, DIV4_B, DIV4_B3, DIV4_P, DIV4_NR }; 110 111 #define DIV4(_reg, _bit, _mask, _flags) \ 112 SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags) 113 114 struct clk div4_clks[DIV4_NR] = { 115 [DIV4_I] = DIV4(FRQCR, 20, 0x0dbf, CLK_ENABLE_ON_INIT), 116 [DIV4_U] = DIV4(FRQCR, 16, 0x0dbf, CLK_ENABLE_ON_INIT), 117 [DIV4_SH] = DIV4(FRQCR, 12, 0x0dbf, CLK_ENABLE_ON_INIT), 118 [DIV4_B] = DIV4(FRQCR, 8, 0x0dbf, CLK_ENABLE_ON_INIT), 119 [DIV4_B3] = DIV4(FRQCR, 4, 0x0db4, CLK_ENABLE_ON_INIT), 120 [DIV4_P] = DIV4(FRQCR, 0, 0x0dbf, 0), 121 }; 122 123 enum { DIV4_IRDA, DIV4_ENABLE_NR }; 124 125 struct clk div4_enable_clks[DIV4_ENABLE_NR] = { 126 [DIV4_IRDA] = DIV4(IRDACLKCR, 0, 0x0dbf, 0), 127 }; 128 129 enum { DIV4_SIUA, DIV4_SIUB, DIV4_REPARENT_NR }; 130 131 struct clk div4_reparent_clks[DIV4_REPARENT_NR] = { 132 [DIV4_SIUA] = DIV4(SCLKACR, 0, 0x0dbf, 0), 133 [DIV4_SIUB] = DIV4(SCLKBCR, 0, 0x0dbf, 0), 134 }; 135 enum { DIV6_V, DIV6_NR }; 136 137 struct clk div6_clks[DIV6_NR] = { 138 [DIV6_V] = SH_CLK_DIV6(&pll_clk, VCLKCR, 0), 139 }; 140 141 static struct clk mstp_clks[] = { 142 /* See page 60 of Datasheet V1.0: Overview -> Block Diagram */ 143 [HWBLK_TLB] = SH_CLK_MSTP32(&div4_clks[DIV4_I], MSTPCR0, 31, CLK_ENABLE_ON_INIT), 144 [HWBLK_IC] = SH_CLK_MSTP32(&div4_clks[DIV4_I], MSTPCR0, 30, CLK_ENABLE_ON_INIT), 145 [HWBLK_OC] = SH_CLK_MSTP32(&div4_clks[DIV4_I], MSTPCR0, 29, CLK_ENABLE_ON_INIT), 146 [HWBLK_L2C] = SH_CLK_MSTP32(&div4_clks[DIV4_SH], MSTPCR0, 28, CLK_ENABLE_ON_INIT), 147 [HWBLK_ILMEM] = SH_CLK_MSTP32(&div4_clks[DIV4_I], MSTPCR0, 27, CLK_ENABLE_ON_INIT), 148 [HWBLK_FPU] = SH_CLK_MSTP32(&div4_clks[DIV4_I], MSTPCR0, 24, CLK_ENABLE_ON_INIT), 149 [HWBLK_INTC] = SH_CLK_MSTP32(&div4_clks[DIV4_I], MSTPCR0, 22, CLK_ENABLE_ON_INIT), 150 [HWBLK_DMAC0] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR0, 21, 0), 151 [HWBLK_SHYWAY] = SH_CLK_MSTP32(&div4_clks[DIV4_SH], MSTPCR0, 20, CLK_ENABLE_ON_INIT), 152 [HWBLK_HUDI] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 19, 0), 153 [HWBLK_UBC] = SH_CLK_MSTP32(&div4_clks[DIV4_I], MSTPCR0, 17, 0), 154 [HWBLK_TMU0] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 15, 0), 155 [HWBLK_CMT] = SH_CLK_MSTP32(&r_clk, MSTPCR0, 14, 0), 156 [HWBLK_RWDT] = SH_CLK_MSTP32(&r_clk, MSTPCR0, 13, 0), 157 [HWBLK_DMAC1] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR0, 12, 0), 158 [HWBLK_TMU1] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 11, 0), 159 [HWBLK_FLCTL] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 10, 0), 160 [HWBLK_SCIF0] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 9, 0), 161 [HWBLK_SCIF1] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 8, 0), 162 [HWBLK_SCIF2] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 7, 0), 163 [HWBLK_SCIF3] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR0, 6, 0), 164 [HWBLK_SCIF4] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR0, 5, 0), 165 [HWBLK_SCIF5] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR0, 4, 0), 166 [HWBLK_MSIOF0] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR0, 2, 0), 167 [HWBLK_MSIOF1] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR0, 1, 0), 168 [HWBLK_MERAM] = SH_CLK_MSTP32(&div4_clks[DIV4_SH], MSTPCR0, 0, 0), 169 170 [HWBLK_IIC] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 9, 0), 171 [HWBLK_RTC] = SH_CLK_MSTP32(&r_clk, MSTPCR1, 8, 0), 172 173 [HWBLK_ATAPI] = SH_CLK_MSTP32(&div4_clks[DIV4_SH], MSTPCR2, 28, 0), 174 [HWBLK_ADC] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR2, 27, 0), 175 [HWBLK_TPU] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 25, 0), 176 [HWBLK_IRDA] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR2, 24, 0), 177 [HWBLK_TSIF] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 22, 0), 178 [HWBLK_ICB] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 21, CLK_ENABLE_ON_INIT), 179 [HWBLK_SDHI0] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 18, 0), 180 [HWBLK_SDHI1] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 17, 0), 181 [HWBLK_KEYSC] = SH_CLK_MSTP32(&r_clk, MSTPCR2, 14, 0), 182 [HWBLK_USB] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 11, 0), 183 [HWBLK_2DG] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 10, 0), 184 [HWBLK_SIU] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 8, 0), 185 [HWBLK_VEU2H1] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 6, 0), 186 [HWBLK_VOU] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 5, 0), 187 [HWBLK_BEU] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 4, 0), 188 [HWBLK_CEU] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 3, 0), 189 [HWBLK_VEU2H0] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 2, 0), 190 [HWBLK_VPU] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 1, 0), 191 [HWBLK_LCDC] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 0, 0), 192 }; 193 194 static struct clk_lookup lookups[] = { 195 /* main clocks */ 196 CLKDEV_CON_ID("rclk", &r_clk), 197 CLKDEV_CON_ID("extal", &extal_clk), 198 CLKDEV_CON_ID("dll_clk", &dll_clk), 199 CLKDEV_CON_ID("pll_clk", &pll_clk), 200 201 /* DIV4 clocks */ 202 CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]), 203 CLKDEV_CON_ID("umem_clk", &div4_clks[DIV4_U]), 204 CLKDEV_CON_ID("shyway_clk", &div4_clks[DIV4_SH]), 205 CLKDEV_CON_ID("bus_clk", &div4_clks[DIV4_B]), 206 CLKDEV_CON_ID("b3_clk", &div4_clks[DIV4_B3]), 207 CLKDEV_CON_ID("peripheral_clk", &div4_clks[DIV4_P]), 208 CLKDEV_CON_ID("irda_clk", &div4_enable_clks[DIV4_IRDA]), 209 CLKDEV_CON_ID("siua_clk", &div4_reparent_clks[DIV4_SIUA]), 210 CLKDEV_CON_ID("siub_clk", &div4_reparent_clks[DIV4_SIUB]), 211 212 /* DIV6 clocks */ 213 CLKDEV_CON_ID("video_clk", &div6_clks[DIV6_V]), 214 215 /* MSTP clocks */ 216 CLKDEV_CON_ID("tlb0", &mstp_clks[HWBLK_TLB]), 217 CLKDEV_CON_ID("ic0", &mstp_clks[HWBLK_IC]), 218 CLKDEV_CON_ID("oc0", &mstp_clks[HWBLK_OC]), 219 CLKDEV_CON_ID("l2c0", &mstp_clks[HWBLK_L2C]), 220 CLKDEV_CON_ID("ilmem0", &mstp_clks[HWBLK_ILMEM]), 221 CLKDEV_CON_ID("fpu0", &mstp_clks[HWBLK_FPU]), 222 CLKDEV_CON_ID("intc0", &mstp_clks[HWBLK_INTC]), 223 CLKDEV_DEV_ID("sh-dma-engine.0", &mstp_clks[HWBLK_DMAC0]), 224 CLKDEV_CON_ID("sh0", &mstp_clks[HWBLK_SHYWAY]), 225 CLKDEV_CON_ID("hudi0", &mstp_clks[HWBLK_HUDI]), 226 CLKDEV_CON_ID("ubc0", &mstp_clks[HWBLK_UBC]), 227 CLKDEV_ICK_ID("fck", "sh-cmt-32.0", &mstp_clks[HWBLK_CMT]), 228 CLKDEV_DEV_ID("sh-wdt.0", &mstp_clks[HWBLK_RWDT]), 229 CLKDEV_DEV_ID("sh-dma-engine.1", &mstp_clks[HWBLK_DMAC1]), 230 CLKDEV_CON_ID("flctl0", &mstp_clks[HWBLK_FLCTL]), 231 CLKDEV_DEV_ID("spi_sh_msiof.0", &mstp_clks[HWBLK_MSIOF0]), 232 CLKDEV_DEV_ID("spi_sh_msiof.1", &mstp_clks[HWBLK_MSIOF1]), 233 CLKDEV_DEV_ID("sh_mobile_meram.0", &mstp_clks[HWBLK_MERAM]), 234 CLKDEV_DEV_ID("i2c-sh_mobile.0", &mstp_clks[HWBLK_IIC]), 235 CLKDEV_CON_ID("rtc0", &mstp_clks[HWBLK_RTC]), 236 CLKDEV_CON_ID("atapi0", &mstp_clks[HWBLK_ATAPI]), 237 CLKDEV_CON_ID("adc0", &mstp_clks[HWBLK_ADC]), 238 CLKDEV_CON_ID("tpu0", &mstp_clks[HWBLK_TPU]), 239 CLKDEV_CON_ID("irda0", &mstp_clks[HWBLK_IRDA]), 240 CLKDEV_CON_ID("tsif0", &mstp_clks[HWBLK_TSIF]), 241 CLKDEV_CON_ID("icb0", &mstp_clks[HWBLK_ICB]), 242 CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[HWBLK_SDHI0]), 243 CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[HWBLK_SDHI1]), 244 CLKDEV_DEV_ID("sh_keysc.0", &mstp_clks[HWBLK_KEYSC]), 245 CLKDEV_CON_ID("usb0", &mstp_clks[HWBLK_USB]), 246 CLKDEV_CON_ID("2dg0", &mstp_clks[HWBLK_2DG]), 247 CLKDEV_DEV_ID("siu-pcm-audio", &mstp_clks[HWBLK_SIU]), 248 CLKDEV_CON_ID("veu1", &mstp_clks[HWBLK_VEU2H1]), 249 CLKDEV_DEV_ID("sh-vou.0", &mstp_clks[HWBLK_VOU]), 250 CLKDEV_CON_ID("beu0", &mstp_clks[HWBLK_BEU]), 251 CLKDEV_DEV_ID("ceu.0", &mstp_clks[HWBLK_CEU]), 252 CLKDEV_CON_ID("veu0", &mstp_clks[HWBLK_VEU2H0]), 253 CLKDEV_CON_ID("vpu0", &mstp_clks[HWBLK_VPU]), 254 255 CLKDEV_ICK_ID("fck", "sh-tmu.0", &mstp_clks[HWBLK_TMU0]), 256 CLKDEV_ICK_ID("fck", "sh-tmu.1", &mstp_clks[HWBLK_TMU1]), 257 258 CLKDEV_ICK_ID("fck", "sh-sci.0", &mstp_clks[HWBLK_SCIF0]), 259 CLKDEV_ICK_ID("fck", "sh-sci.1", &mstp_clks[HWBLK_SCIF1]), 260 CLKDEV_ICK_ID("fck", "sh-sci.2", &mstp_clks[HWBLK_SCIF2]), 261 CLKDEV_ICK_ID("fck", "sh-sci.3", &mstp_clks[HWBLK_SCIF3]), 262 CLKDEV_ICK_ID("fck", "sh-sci.4", &mstp_clks[HWBLK_SCIF4]), 263 CLKDEV_ICK_ID("fck", "sh-sci.5", &mstp_clks[HWBLK_SCIF5]), 264 265 CLKDEV_DEV_ID("sh_mobile_lcdc_fb.0", &mstp_clks[HWBLK_LCDC]), 266 }; 267 268 int __init arch_clk_init(void) 269 { 270 int k, ret = 0; 271 272 /* autodetect extal or dll configuration */ 273 if (__raw_readl(PLLCR) & 0x1000) 274 pll_clk.parent = &dll_clk; 275 else 276 pll_clk.parent = &extal_clk; 277 278 for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++) 279 ret |= clk_register(main_clks[k]); 280 281 clkdev_add_table(lookups, ARRAY_SIZE(lookups)); 282 283 if (!ret) 284 ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table); 285 286 if (!ret) 287 ret = sh_clk_div4_enable_register(div4_enable_clks, 288 DIV4_ENABLE_NR, &div4_table); 289 290 if (!ret) 291 ret = sh_clk_div4_reparent_register(div4_reparent_clks, 292 DIV4_REPARENT_NR, &div4_table); 293 294 if (!ret) 295 ret = sh_clk_div6_register(div6_clks, DIV6_NR); 296 297 if (!ret) 298 ret = sh_clk_mstp_register(mstp_clks, HWBLK_NR); 299 300 return ret; 301 } 302