1 /* 2 * SH7091/SH7750/SH7750S/SH7750R/SH7751/SH7751R Setup 3 * 4 * Copyright (C) 2006 Paul Mundt 5 * Copyright (C) 2006 Jamie Lenehan 6 * 7 * This file is subject to the terms and conditions of the GNU General Public 8 * License. See the file "COPYING" in the main directory of this archive 9 * for more details. 10 */ 11 #include <linux/platform_device.h> 12 #include <linux/init.h> 13 #include <linux/serial.h> 14 #include <linux/io.h> 15 #include <linux/sh_timer.h> 16 #include <linux/sh_intc.h> 17 #include <linux/serial_sci.h> 18 #include <generated/machtypes.h> 19 20 static struct resource rtc_resources[] = { 21 [0] = { 22 .start = 0xffc80000, 23 .end = 0xffc80000 + 0x58 - 1, 24 .flags = IORESOURCE_IO, 25 }, 26 [1] = { 27 /* Shared Period/Carry/Alarm IRQ */ 28 .start = evt2irq(0x480), 29 .flags = IORESOURCE_IRQ, 30 }, 31 }; 32 33 static struct platform_device rtc_device = { 34 .name = "sh-rtc", 35 .id = -1, 36 .num_resources = ARRAY_SIZE(rtc_resources), 37 .resource = rtc_resources, 38 }; 39 40 static struct plat_sci_port sci_platform_data = { 41 .port_reg = 0xffe0001C, 42 .flags = UPF_BOOT_AUTOCONF, 43 .scscr = SCSCR_TE | SCSCR_RE, 44 .type = PORT_SCI, 45 .regshift = 2, 46 }; 47 48 static struct resource sci_resources[] = { 49 DEFINE_RES_MEM(0xffe00000, 0x100), 50 DEFINE_RES_IRQ(evt2irq(0x4e0)), 51 }; 52 53 static struct platform_device sci_device = { 54 .name = "sh-sci", 55 .id = 0, 56 .resource = sci_resources, 57 .num_resources = ARRAY_SIZE(sci_resources), 58 .dev = { 59 .platform_data = &sci_platform_data, 60 }, 61 }; 62 63 static struct plat_sci_port scif_platform_data = { 64 .flags = UPF_BOOT_AUTOCONF, 65 .scscr = SCSCR_TE | SCSCR_RE | SCSCR_REIE, 66 .type = PORT_SCIF, 67 }; 68 69 static struct resource scif_resources[] = { 70 DEFINE_RES_MEM(0xffe80000, 0x100), 71 DEFINE_RES_IRQ(evt2irq(0x700)), 72 }; 73 74 static struct platform_device scif_device = { 75 .name = "sh-sci", 76 .id = 1, 77 .resource = scif_resources, 78 .num_resources = ARRAY_SIZE(scif_resources), 79 .dev = { 80 .platform_data = &scif_platform_data, 81 }, 82 }; 83 84 static struct sh_timer_config tmu0_platform_data = { 85 .channels_mask = 7, 86 }; 87 88 static struct resource tmu0_resources[] = { 89 DEFINE_RES_MEM(0xffd80000, 0x30), 90 DEFINE_RES_IRQ(evt2irq(0x400)), 91 DEFINE_RES_IRQ(evt2irq(0x420)), 92 DEFINE_RES_IRQ(evt2irq(0x440)), 93 }; 94 95 static struct platform_device tmu0_device = { 96 .name = "sh-tmu", 97 .id = 0, 98 .dev = { 99 .platform_data = &tmu0_platform_data, 100 }, 101 .resource = tmu0_resources, 102 .num_resources = ARRAY_SIZE(tmu0_resources), 103 }; 104 105 /* SH7750R, SH7751 and SH7751R all have two extra timer channels */ 106 #if defined(CONFIG_CPU_SUBTYPE_SH7750R) || \ 107 defined(CONFIG_CPU_SUBTYPE_SH7751) || \ 108 defined(CONFIG_CPU_SUBTYPE_SH7751R) 109 110 static struct sh_timer_config tmu1_platform_data = { 111 .channels_mask = 3, 112 }; 113 114 static struct resource tmu1_resources[] = { 115 DEFINE_RES_MEM(0xfe100000, 0x20), 116 DEFINE_RES_IRQ(evt2irq(0xb00)), 117 DEFINE_RES_IRQ(evt2irq(0xb80)), 118 }; 119 120 static struct platform_device tmu1_device = { 121 .name = "sh-tmu", 122 .id = 1, 123 .dev = { 124 .platform_data = &tmu1_platform_data, 125 }, 126 .resource = tmu1_resources, 127 .num_resources = ARRAY_SIZE(tmu1_resources), 128 }; 129 130 #endif 131 132 static struct platform_device *sh7750_devices[] __initdata = { 133 &rtc_device, 134 &tmu0_device, 135 #if defined(CONFIG_CPU_SUBTYPE_SH7750R) || \ 136 defined(CONFIG_CPU_SUBTYPE_SH7751) || \ 137 defined(CONFIG_CPU_SUBTYPE_SH7751R) 138 &tmu1_device, 139 #endif 140 }; 141 142 static int __init sh7750_devices_setup(void) 143 { 144 if (mach_is_rts7751r2d()) { 145 platform_device_register(&scif_device); 146 } else { 147 platform_device_register(&sci_device); 148 platform_device_register(&scif_device); 149 } 150 151 return platform_add_devices(sh7750_devices, 152 ARRAY_SIZE(sh7750_devices)); 153 } 154 arch_initcall(sh7750_devices_setup); 155 156 static struct platform_device *sh7750_early_devices[] __initdata = { 157 &tmu0_device, 158 #if defined(CONFIG_CPU_SUBTYPE_SH7750R) || \ 159 defined(CONFIG_CPU_SUBTYPE_SH7751) || \ 160 defined(CONFIG_CPU_SUBTYPE_SH7751R) 161 &tmu1_device, 162 #endif 163 }; 164 165 void __init plat_early_device_setup(void) 166 { 167 struct platform_device *dev[1]; 168 169 if (mach_is_rts7751r2d()) { 170 scif_platform_data.scscr |= SCSCR_CKE1; 171 dev[0] = &scif_device; 172 early_platform_add_devices(dev, 1); 173 } else { 174 dev[0] = &sci_device; 175 early_platform_add_devices(dev, 1); 176 dev[0] = &scif_device; 177 early_platform_add_devices(dev, 1); 178 } 179 180 early_platform_add_devices(sh7750_early_devices, 181 ARRAY_SIZE(sh7750_early_devices)); 182 } 183 184 enum { 185 UNUSED = 0, 186 187 /* interrupt sources */ 188 IRL0, IRL1, IRL2, IRL3, /* only IRLM mode supported */ 189 HUDI, GPIOI, DMAC, 190 PCIC0_PCISERR, PCIC1_PCIERR, PCIC1_PCIPWDWN, PCIC1_PCIPWON, 191 PCIC1_PCIDMA0, PCIC1_PCIDMA1, PCIC1_PCIDMA2, PCIC1_PCIDMA3, 192 TMU3, TMU4, TMU0, TMU1, TMU2, RTC, SCI1, SCIF, WDT, REF, 193 194 /* interrupt groups */ 195 PCIC1, 196 }; 197 198 static struct intc_vect vectors[] __initdata = { 199 INTC_VECT(HUDI, 0x600), INTC_VECT(GPIOI, 0x620), 200 INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420), 201 INTC_VECT(TMU2, 0x440), INTC_VECT(TMU2, 0x460), 202 INTC_VECT(RTC, 0x480), INTC_VECT(RTC, 0x4a0), 203 INTC_VECT(RTC, 0x4c0), 204 INTC_VECT(SCI1, 0x4e0), INTC_VECT(SCI1, 0x500), 205 INTC_VECT(SCI1, 0x520), INTC_VECT(SCI1, 0x540), 206 INTC_VECT(SCIF, 0x700), INTC_VECT(SCIF, 0x720), 207 INTC_VECT(SCIF, 0x740), INTC_VECT(SCIF, 0x760), 208 INTC_VECT(WDT, 0x560), 209 INTC_VECT(REF, 0x580), INTC_VECT(REF, 0x5a0), 210 }; 211 212 static struct intc_prio_reg prio_registers[] __initdata = { 213 { 0xffd00004, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, RTC } }, 214 { 0xffd00008, 0, 16, 4, /* IPRB */ { WDT, REF, SCI1, 0 } }, 215 { 0xffd0000c, 0, 16, 4, /* IPRC */ { GPIOI, DMAC, SCIF, HUDI } }, 216 { 0xffd00010, 0, 16, 4, /* IPRD */ { IRL0, IRL1, IRL2, IRL3 } }, 217 { 0xfe080000, 0, 32, 4, /* INTPRI00 */ { 0, 0, 0, 0, 218 TMU4, TMU3, 219 PCIC1, PCIC0_PCISERR } }, 220 }; 221 222 static DECLARE_INTC_DESC(intc_desc, "sh7750", vectors, NULL, 223 NULL, prio_registers, NULL); 224 225 /* SH7750, SH7750S, SH7751 and SH7091 all have 4-channel DMA controllers */ 226 #if defined(CONFIG_CPU_SUBTYPE_SH7750) || \ 227 defined(CONFIG_CPU_SUBTYPE_SH7750S) || \ 228 defined(CONFIG_CPU_SUBTYPE_SH7751) || \ 229 defined(CONFIG_CPU_SUBTYPE_SH7091) 230 static struct intc_vect vectors_dma4[] __initdata = { 231 INTC_VECT(DMAC, 0x640), INTC_VECT(DMAC, 0x660), 232 INTC_VECT(DMAC, 0x680), INTC_VECT(DMAC, 0x6a0), 233 INTC_VECT(DMAC, 0x6c0), 234 }; 235 236 static DECLARE_INTC_DESC(intc_desc_dma4, "sh7750_dma4", 237 vectors_dma4, NULL, 238 NULL, prio_registers, NULL); 239 #endif 240 241 /* SH7750R and SH7751R both have 8-channel DMA controllers */ 242 #if defined(CONFIG_CPU_SUBTYPE_SH7750R) || defined(CONFIG_CPU_SUBTYPE_SH7751R) 243 static struct intc_vect vectors_dma8[] __initdata = { 244 INTC_VECT(DMAC, 0x640), INTC_VECT(DMAC, 0x660), 245 INTC_VECT(DMAC, 0x680), INTC_VECT(DMAC, 0x6a0), 246 INTC_VECT(DMAC, 0x780), INTC_VECT(DMAC, 0x7a0), 247 INTC_VECT(DMAC, 0x7c0), INTC_VECT(DMAC, 0x7e0), 248 INTC_VECT(DMAC, 0x6c0), 249 }; 250 251 static DECLARE_INTC_DESC(intc_desc_dma8, "sh7750_dma8", 252 vectors_dma8, NULL, 253 NULL, prio_registers, NULL); 254 #endif 255 256 /* SH7750R, SH7751 and SH7751R all have two extra timer channels */ 257 #if defined(CONFIG_CPU_SUBTYPE_SH7750R) || \ 258 defined(CONFIG_CPU_SUBTYPE_SH7751) || \ 259 defined(CONFIG_CPU_SUBTYPE_SH7751R) 260 static struct intc_vect vectors_tmu34[] __initdata = { 261 INTC_VECT(TMU3, 0xb00), INTC_VECT(TMU4, 0xb80), 262 }; 263 264 static struct intc_mask_reg mask_registers[] __initdata = { 265 { 0xfe080040, 0xfe080060, 32, /* INTMSK00 / INTMSKCLR00 */ 266 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 267 0, 0, 0, 0, 0, 0, TMU4, TMU3, 268 PCIC1_PCIERR, PCIC1_PCIPWDWN, PCIC1_PCIPWON, 269 PCIC1_PCIDMA0, PCIC1_PCIDMA1, PCIC1_PCIDMA2, 270 PCIC1_PCIDMA3, PCIC0_PCISERR } }, 271 }; 272 273 static DECLARE_INTC_DESC(intc_desc_tmu34, "sh7750_tmu34", 274 vectors_tmu34, NULL, 275 mask_registers, prio_registers, NULL); 276 #endif 277 278 /* SH7750S, SH7750R, SH7751 and SH7751R all have IRLM priority registers */ 279 static struct intc_vect vectors_irlm[] __initdata = { 280 INTC_VECT(IRL0, 0x240), INTC_VECT(IRL1, 0x2a0), 281 INTC_VECT(IRL2, 0x300), INTC_VECT(IRL3, 0x360), 282 }; 283 284 static DECLARE_INTC_DESC(intc_desc_irlm, "sh7750_irlm", vectors_irlm, NULL, 285 NULL, prio_registers, NULL); 286 287 /* SH7751 and SH7751R both have PCI */ 288 #if defined(CONFIG_CPU_SUBTYPE_SH7751) || defined(CONFIG_CPU_SUBTYPE_SH7751R) 289 static struct intc_vect vectors_pci[] __initdata = { 290 INTC_VECT(PCIC0_PCISERR, 0xa00), INTC_VECT(PCIC1_PCIERR, 0xae0), 291 INTC_VECT(PCIC1_PCIPWDWN, 0xac0), INTC_VECT(PCIC1_PCIPWON, 0xaa0), 292 INTC_VECT(PCIC1_PCIDMA0, 0xa80), INTC_VECT(PCIC1_PCIDMA1, 0xa60), 293 INTC_VECT(PCIC1_PCIDMA2, 0xa40), INTC_VECT(PCIC1_PCIDMA3, 0xa20), 294 }; 295 296 static struct intc_group groups_pci[] __initdata = { 297 INTC_GROUP(PCIC1, PCIC1_PCIERR, PCIC1_PCIPWDWN, PCIC1_PCIPWON, 298 PCIC1_PCIDMA0, PCIC1_PCIDMA1, PCIC1_PCIDMA2, PCIC1_PCIDMA3), 299 }; 300 301 static DECLARE_INTC_DESC(intc_desc_pci, "sh7750_pci", vectors_pci, groups_pci, 302 mask_registers, prio_registers, NULL); 303 #endif 304 305 #if defined(CONFIG_CPU_SUBTYPE_SH7750) || \ 306 defined(CONFIG_CPU_SUBTYPE_SH7750S) || \ 307 defined(CONFIG_CPU_SUBTYPE_SH7091) 308 void __init plat_irq_setup(void) 309 { 310 /* 311 * same vectors for SH7750, SH7750S and SH7091 except for IRLM, 312 * see below.. 313 */ 314 register_intc_controller(&intc_desc); 315 register_intc_controller(&intc_desc_dma4); 316 } 317 #endif 318 319 #if defined(CONFIG_CPU_SUBTYPE_SH7750R) 320 void __init plat_irq_setup(void) 321 { 322 register_intc_controller(&intc_desc); 323 register_intc_controller(&intc_desc_dma8); 324 register_intc_controller(&intc_desc_tmu34); 325 } 326 #endif 327 328 #if defined(CONFIG_CPU_SUBTYPE_SH7751) 329 void __init plat_irq_setup(void) 330 { 331 register_intc_controller(&intc_desc); 332 register_intc_controller(&intc_desc_dma4); 333 register_intc_controller(&intc_desc_tmu34); 334 register_intc_controller(&intc_desc_pci); 335 } 336 #endif 337 338 #if defined(CONFIG_CPU_SUBTYPE_SH7751R) 339 void __init plat_irq_setup(void) 340 { 341 register_intc_controller(&intc_desc); 342 register_intc_controller(&intc_desc_dma8); 343 register_intc_controller(&intc_desc_tmu34); 344 register_intc_controller(&intc_desc_pci); 345 } 346 #endif 347 348 #define INTC_ICR 0xffd00000UL 349 #define INTC_ICR_IRLM (1<<7) 350 351 void __init plat_irq_setup_pins(int mode) 352 { 353 #if defined(CONFIG_CPU_SUBTYPE_SH7750) || defined(CONFIG_CPU_SUBTYPE_SH7091) 354 BUG(); /* impossible to mask interrupts on SH7750 and SH7091 */ 355 return; 356 #endif 357 358 switch (mode) { 359 case IRQ_MODE_IRQ: /* individual interrupt mode for IRL3-0 */ 360 __raw_writew(__raw_readw(INTC_ICR) | INTC_ICR_IRLM, INTC_ICR); 361 register_intc_controller(&intc_desc_irlm); 362 break; 363 default: 364 BUG(); 365 } 366 } 367