1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * SH7091/SH7750/SH7750S/SH7750R/SH7751/SH7751R Setup 4 * 5 * Copyright (C) 2006 Paul Mundt 6 * Copyright (C) 2006 Jamie Lenehan 7 */ 8 #include <linux/platform_device.h> 9 #include <linux/init.h> 10 #include <linux/serial.h> 11 #include <linux/io.h> 12 #include <linux/sh_timer.h> 13 #include <linux/sh_intc.h> 14 #include <linux/serial_sci.h> 15 #include <generated/machtypes.h> 16 17 static struct resource rtc_resources[] = { 18 [0] = { 19 .start = 0xffc80000, 20 .end = 0xffc80000 + 0x58 - 1, 21 .flags = IORESOURCE_IO, 22 }, 23 [1] = { 24 /* Shared Period/Carry/Alarm IRQ */ 25 .start = evt2irq(0x480), 26 .flags = IORESOURCE_IRQ, 27 }, 28 }; 29 30 static struct platform_device rtc_device = { 31 .name = "sh-rtc", 32 .id = -1, 33 .num_resources = ARRAY_SIZE(rtc_resources), 34 .resource = rtc_resources, 35 }; 36 37 static struct plat_sci_port sci_platform_data = { 38 .type = PORT_SCI, 39 }; 40 41 static struct resource sci_resources[] = { 42 DEFINE_RES_MEM(0xffe00000, 0x20), 43 DEFINE_RES_IRQ(evt2irq(0x4e0)), 44 }; 45 46 static struct platform_device sci_device = { 47 .name = "sh-sci", 48 .id = 0, 49 .resource = sci_resources, 50 .num_resources = ARRAY_SIZE(sci_resources), 51 .dev = { 52 .platform_data = &sci_platform_data, 53 }, 54 }; 55 56 static struct plat_sci_port scif_platform_data = { 57 .scscr = SCSCR_REIE, 58 .type = PORT_SCIF, 59 }; 60 61 static struct resource scif_resources[] = { 62 DEFINE_RES_MEM(0xffe80000, 0x100), 63 DEFINE_RES_IRQ(evt2irq(0x700)), 64 }; 65 66 static struct platform_device scif_device = { 67 .name = "sh-sci", 68 .id = 1, 69 .resource = scif_resources, 70 .num_resources = ARRAY_SIZE(scif_resources), 71 .dev = { 72 .platform_data = &scif_platform_data, 73 }, 74 }; 75 76 static struct sh_timer_config tmu0_platform_data = { 77 .channels_mask = 7, 78 }; 79 80 static struct resource tmu0_resources[] = { 81 DEFINE_RES_MEM(0xffd80000, 0x30), 82 DEFINE_RES_IRQ(evt2irq(0x400)), 83 DEFINE_RES_IRQ(evt2irq(0x420)), 84 DEFINE_RES_IRQ(evt2irq(0x440)), 85 }; 86 87 static struct platform_device tmu0_device = { 88 .name = "sh-tmu", 89 .id = 0, 90 .dev = { 91 .platform_data = &tmu0_platform_data, 92 }, 93 .resource = tmu0_resources, 94 .num_resources = ARRAY_SIZE(tmu0_resources), 95 }; 96 97 /* SH7750R, SH7751 and SH7751R all have two extra timer channels */ 98 #if defined(CONFIG_CPU_SUBTYPE_SH7750R) || \ 99 defined(CONFIG_CPU_SUBTYPE_SH7751) || \ 100 defined(CONFIG_CPU_SUBTYPE_SH7751R) 101 102 static struct sh_timer_config tmu1_platform_data = { 103 .channels_mask = 3, 104 }; 105 106 static struct resource tmu1_resources[] = { 107 DEFINE_RES_MEM(0xfe100000, 0x20), 108 DEFINE_RES_IRQ(evt2irq(0xb00)), 109 DEFINE_RES_IRQ(evt2irq(0xb80)), 110 }; 111 112 static struct platform_device tmu1_device = { 113 .name = "sh-tmu", 114 .id = 1, 115 .dev = { 116 .platform_data = &tmu1_platform_data, 117 }, 118 .resource = tmu1_resources, 119 .num_resources = ARRAY_SIZE(tmu1_resources), 120 }; 121 122 #endif 123 124 static struct platform_device *sh7750_devices[] __initdata = { 125 &rtc_device, 126 &tmu0_device, 127 #if defined(CONFIG_CPU_SUBTYPE_SH7750R) || \ 128 defined(CONFIG_CPU_SUBTYPE_SH7751) || \ 129 defined(CONFIG_CPU_SUBTYPE_SH7751R) 130 &tmu1_device, 131 #endif 132 }; 133 134 static int __init sh7750_devices_setup(void) 135 { 136 if (mach_is_rts7751r2d()) { 137 platform_device_register(&scif_device); 138 } else { 139 platform_device_register(&sci_device); 140 platform_device_register(&scif_device); 141 } 142 143 return platform_add_devices(sh7750_devices, 144 ARRAY_SIZE(sh7750_devices)); 145 } 146 arch_initcall(sh7750_devices_setup); 147 148 static struct platform_device *sh7750_early_devices[] __initdata = { 149 &tmu0_device, 150 #if defined(CONFIG_CPU_SUBTYPE_SH7750R) || \ 151 defined(CONFIG_CPU_SUBTYPE_SH7751) || \ 152 defined(CONFIG_CPU_SUBTYPE_SH7751R) 153 &tmu1_device, 154 #endif 155 }; 156 157 void __init plat_early_device_setup(void) 158 { 159 struct platform_device *dev[1]; 160 161 if (mach_is_rts7751r2d()) { 162 scif_platform_data.scscr |= SCSCR_CKE1; 163 dev[0] = &scif_device; 164 early_platform_add_devices(dev, 1); 165 } else { 166 dev[0] = &sci_device; 167 early_platform_add_devices(dev, 1); 168 dev[0] = &scif_device; 169 early_platform_add_devices(dev, 1); 170 } 171 172 early_platform_add_devices(sh7750_early_devices, 173 ARRAY_SIZE(sh7750_early_devices)); 174 } 175 176 enum { 177 UNUSED = 0, 178 179 /* interrupt sources */ 180 IRL0, IRL1, IRL2, IRL3, /* only IRLM mode supported */ 181 HUDI, GPIOI, DMAC, 182 PCIC0_PCISERR, PCIC1_PCIERR, PCIC1_PCIPWDWN, PCIC1_PCIPWON, 183 PCIC1_PCIDMA0, PCIC1_PCIDMA1, PCIC1_PCIDMA2, PCIC1_PCIDMA3, 184 TMU3, TMU4, TMU0, TMU1, TMU2, RTC, SCI1, SCIF, WDT, REF, 185 186 /* interrupt groups */ 187 PCIC1, 188 }; 189 190 static struct intc_vect vectors[] __initdata = { 191 INTC_VECT(HUDI, 0x600), INTC_VECT(GPIOI, 0x620), 192 INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420), 193 INTC_VECT(TMU2, 0x440), INTC_VECT(TMU2, 0x460), 194 INTC_VECT(RTC, 0x480), INTC_VECT(RTC, 0x4a0), 195 INTC_VECT(RTC, 0x4c0), 196 INTC_VECT(SCI1, 0x4e0), INTC_VECT(SCI1, 0x500), 197 INTC_VECT(SCI1, 0x520), INTC_VECT(SCI1, 0x540), 198 INTC_VECT(SCIF, 0x700), INTC_VECT(SCIF, 0x720), 199 INTC_VECT(SCIF, 0x740), INTC_VECT(SCIF, 0x760), 200 INTC_VECT(WDT, 0x560), 201 INTC_VECT(REF, 0x580), INTC_VECT(REF, 0x5a0), 202 }; 203 204 static struct intc_prio_reg prio_registers[] __initdata = { 205 { 0xffd00004, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, RTC } }, 206 { 0xffd00008, 0, 16, 4, /* IPRB */ { WDT, REF, SCI1, 0 } }, 207 { 0xffd0000c, 0, 16, 4, /* IPRC */ { GPIOI, DMAC, SCIF, HUDI } }, 208 { 0xffd00010, 0, 16, 4, /* IPRD */ { IRL0, IRL1, IRL2, IRL3 } }, 209 { 0xfe080000, 0, 32, 4, /* INTPRI00 */ { 0, 0, 0, 0, 210 TMU4, TMU3, 211 PCIC1, PCIC0_PCISERR } }, 212 }; 213 214 static DECLARE_INTC_DESC(intc_desc, "sh7750", vectors, NULL, 215 NULL, prio_registers, NULL); 216 217 /* SH7750, SH7750S, SH7751 and SH7091 all have 4-channel DMA controllers */ 218 #if defined(CONFIG_CPU_SUBTYPE_SH7750) || \ 219 defined(CONFIG_CPU_SUBTYPE_SH7750S) || \ 220 defined(CONFIG_CPU_SUBTYPE_SH7751) || \ 221 defined(CONFIG_CPU_SUBTYPE_SH7091) 222 static struct intc_vect vectors_dma4[] __initdata = { 223 INTC_VECT(DMAC, 0x640), INTC_VECT(DMAC, 0x660), 224 INTC_VECT(DMAC, 0x680), INTC_VECT(DMAC, 0x6a0), 225 INTC_VECT(DMAC, 0x6c0), 226 }; 227 228 static DECLARE_INTC_DESC(intc_desc_dma4, "sh7750_dma4", 229 vectors_dma4, NULL, 230 NULL, prio_registers, NULL); 231 #endif 232 233 /* SH7750R and SH7751R both have 8-channel DMA controllers */ 234 #if defined(CONFIG_CPU_SUBTYPE_SH7750R) || defined(CONFIG_CPU_SUBTYPE_SH7751R) 235 static struct intc_vect vectors_dma8[] __initdata = { 236 INTC_VECT(DMAC, 0x640), INTC_VECT(DMAC, 0x660), 237 INTC_VECT(DMAC, 0x680), INTC_VECT(DMAC, 0x6a0), 238 INTC_VECT(DMAC, 0x780), INTC_VECT(DMAC, 0x7a0), 239 INTC_VECT(DMAC, 0x7c0), INTC_VECT(DMAC, 0x7e0), 240 INTC_VECT(DMAC, 0x6c0), 241 }; 242 243 static DECLARE_INTC_DESC(intc_desc_dma8, "sh7750_dma8", 244 vectors_dma8, NULL, 245 NULL, prio_registers, NULL); 246 #endif 247 248 /* SH7750R, SH7751 and SH7751R all have two extra timer channels */ 249 #if defined(CONFIG_CPU_SUBTYPE_SH7750R) || \ 250 defined(CONFIG_CPU_SUBTYPE_SH7751) || \ 251 defined(CONFIG_CPU_SUBTYPE_SH7751R) 252 static struct intc_vect vectors_tmu34[] __initdata = { 253 INTC_VECT(TMU3, 0xb00), INTC_VECT(TMU4, 0xb80), 254 }; 255 256 static struct intc_mask_reg mask_registers[] __initdata = { 257 { 0xfe080040, 0xfe080060, 32, /* INTMSK00 / INTMSKCLR00 */ 258 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 259 0, 0, 0, 0, 0, 0, TMU4, TMU3, 260 PCIC1_PCIERR, PCIC1_PCIPWDWN, PCIC1_PCIPWON, 261 PCIC1_PCIDMA0, PCIC1_PCIDMA1, PCIC1_PCIDMA2, 262 PCIC1_PCIDMA3, PCIC0_PCISERR } }, 263 }; 264 265 static DECLARE_INTC_DESC(intc_desc_tmu34, "sh7750_tmu34", 266 vectors_tmu34, NULL, 267 mask_registers, prio_registers, NULL); 268 #endif 269 270 /* SH7750S, SH7750R, SH7751 and SH7751R all have IRLM priority registers */ 271 static struct intc_vect vectors_irlm[] __initdata = { 272 INTC_VECT(IRL0, 0x240), INTC_VECT(IRL1, 0x2a0), 273 INTC_VECT(IRL2, 0x300), INTC_VECT(IRL3, 0x360), 274 }; 275 276 static DECLARE_INTC_DESC(intc_desc_irlm, "sh7750_irlm", vectors_irlm, NULL, 277 NULL, prio_registers, NULL); 278 279 /* SH7751 and SH7751R both have PCI */ 280 #if defined(CONFIG_CPU_SUBTYPE_SH7751) || defined(CONFIG_CPU_SUBTYPE_SH7751R) 281 static struct intc_vect vectors_pci[] __initdata = { 282 INTC_VECT(PCIC0_PCISERR, 0xa00), INTC_VECT(PCIC1_PCIERR, 0xae0), 283 INTC_VECT(PCIC1_PCIPWDWN, 0xac0), INTC_VECT(PCIC1_PCIPWON, 0xaa0), 284 INTC_VECT(PCIC1_PCIDMA0, 0xa80), INTC_VECT(PCIC1_PCIDMA1, 0xa60), 285 INTC_VECT(PCIC1_PCIDMA2, 0xa40), INTC_VECT(PCIC1_PCIDMA3, 0xa20), 286 }; 287 288 static struct intc_group groups_pci[] __initdata = { 289 INTC_GROUP(PCIC1, PCIC1_PCIERR, PCIC1_PCIPWDWN, PCIC1_PCIPWON, 290 PCIC1_PCIDMA0, PCIC1_PCIDMA1, PCIC1_PCIDMA2, PCIC1_PCIDMA3), 291 }; 292 293 static DECLARE_INTC_DESC(intc_desc_pci, "sh7750_pci", vectors_pci, groups_pci, 294 mask_registers, prio_registers, NULL); 295 #endif 296 297 #if defined(CONFIG_CPU_SUBTYPE_SH7750) || \ 298 defined(CONFIG_CPU_SUBTYPE_SH7750S) || \ 299 defined(CONFIG_CPU_SUBTYPE_SH7091) 300 void __init plat_irq_setup(void) 301 { 302 /* 303 * same vectors for SH7750, SH7750S and SH7091 except for IRLM, 304 * see below.. 305 */ 306 register_intc_controller(&intc_desc); 307 register_intc_controller(&intc_desc_dma4); 308 } 309 #endif 310 311 #if defined(CONFIG_CPU_SUBTYPE_SH7750R) 312 void __init plat_irq_setup(void) 313 { 314 register_intc_controller(&intc_desc); 315 register_intc_controller(&intc_desc_dma8); 316 register_intc_controller(&intc_desc_tmu34); 317 } 318 #endif 319 320 #if defined(CONFIG_CPU_SUBTYPE_SH7751) 321 void __init plat_irq_setup(void) 322 { 323 register_intc_controller(&intc_desc); 324 register_intc_controller(&intc_desc_dma4); 325 register_intc_controller(&intc_desc_tmu34); 326 register_intc_controller(&intc_desc_pci); 327 } 328 #endif 329 330 #if defined(CONFIG_CPU_SUBTYPE_SH7751R) 331 void __init plat_irq_setup(void) 332 { 333 register_intc_controller(&intc_desc); 334 register_intc_controller(&intc_desc_dma8); 335 register_intc_controller(&intc_desc_tmu34); 336 register_intc_controller(&intc_desc_pci); 337 } 338 #endif 339 340 #define INTC_ICR 0xffd00000UL 341 #define INTC_ICR_IRLM (1<<7) 342 343 void __init plat_irq_setup_pins(int mode) 344 { 345 #if defined(CONFIG_CPU_SUBTYPE_SH7750) || defined(CONFIG_CPU_SUBTYPE_SH7091) 346 BUG(); /* impossible to mask interrupts on SH7750 and SH7091 */ 347 return; 348 #endif 349 350 switch (mode) { 351 case IRQ_MODE_IRQ: /* individual interrupt mode for IRL3-0 */ 352 __raw_writew(__raw_readw(INTC_ICR) | INTC_ICR_IRLM, INTC_ICR); 353 register_intc_controller(&intc_desc_irlm); 354 break; 355 default: 356 BUG(); 357 } 358 } 359