1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Setup code for SH7720, SH7721. 4 * 5 * Copyright (C) 2007 Markus Brunner, Mark Jonas 6 * Copyright (C) 2009 Paul Mundt 7 * 8 * Based on arch/sh/kernel/cpu/sh4/setup-sh7750.c: 9 * 10 * Copyright (C) 2006 Paul Mundt 11 * Copyright (C) 2006 Jamie Lenehan 12 */ 13 #include <linux/platform_device.h> 14 #include <linux/init.h> 15 #include <linux/serial.h> 16 #include <linux/io.h> 17 #include <linux/serial_sci.h> 18 #include <linux/sh_timer.h> 19 #include <linux/sh_intc.h> 20 #include <linux/usb/ohci_pdriver.h> 21 #include <asm/rtc.h> 22 #include <cpu/serial.h> 23 24 static struct resource rtc_resources[] = { 25 [0] = { 26 .start = 0xa413fec0, 27 .end = 0xa413fec0 + 0x28 - 1, 28 .flags = IORESOURCE_IO, 29 }, 30 [1] = { 31 /* Shared Period/Carry/Alarm IRQ */ 32 .start = evt2irq(0x480), 33 .flags = IORESOURCE_IRQ, 34 }, 35 }; 36 37 static struct sh_rtc_platform_info rtc_info = { 38 .capabilities = RTC_CAP_4_DIGIT_YEAR, 39 }; 40 41 static struct platform_device rtc_device = { 42 .name = "sh-rtc", 43 .id = -1, 44 .num_resources = ARRAY_SIZE(rtc_resources), 45 .resource = rtc_resources, 46 .dev = { 47 .platform_data = &rtc_info, 48 }, 49 }; 50 51 static struct plat_sci_port scif0_platform_data = { 52 .type = PORT_SCIF, 53 .ops = &sh7720_sci_port_ops, 54 .regtype = SCIx_SH7705_SCIF_REGTYPE, 55 }; 56 57 static struct resource scif0_resources[] = { 58 DEFINE_RES_MEM(0xa4430000, 0x100), 59 DEFINE_RES_IRQ(evt2irq(0xc00)), 60 }; 61 62 static struct platform_device scif0_device = { 63 .name = "sh-sci", 64 .id = 0, 65 .resource = scif0_resources, 66 .num_resources = ARRAY_SIZE(scif0_resources), 67 .dev = { 68 .platform_data = &scif0_platform_data, 69 }, 70 }; 71 72 static struct plat_sci_port scif1_platform_data = { 73 .type = PORT_SCIF, 74 .ops = &sh7720_sci_port_ops, 75 .regtype = SCIx_SH7705_SCIF_REGTYPE, 76 }; 77 78 static struct resource scif1_resources[] = { 79 DEFINE_RES_MEM(0xa4438000, 0x100), 80 DEFINE_RES_IRQ(evt2irq(0xc20)), 81 }; 82 83 static struct platform_device scif1_device = { 84 .name = "sh-sci", 85 .id = 1, 86 .resource = scif1_resources, 87 .num_resources = ARRAY_SIZE(scif1_resources), 88 .dev = { 89 .platform_data = &scif1_platform_data, 90 }, 91 }; 92 93 static struct resource usb_ohci_resources[] = { 94 [0] = { 95 .start = 0xA4428000, 96 .end = 0xA44280FF, 97 .flags = IORESOURCE_MEM, 98 }, 99 [1] = { 100 .start = evt2irq(0xa60), 101 .end = evt2irq(0xa60), 102 .flags = IORESOURCE_IRQ, 103 }, 104 }; 105 106 static u64 usb_ohci_dma_mask = 0xffffffffUL; 107 108 static struct usb_ohci_pdata usb_ohci_pdata; 109 110 static struct platform_device usb_ohci_device = { 111 .name = "ohci-platform", 112 .id = -1, 113 .dev = { 114 .dma_mask = &usb_ohci_dma_mask, 115 .coherent_dma_mask = 0xffffffff, 116 .platform_data = &usb_ohci_pdata, 117 }, 118 .num_resources = ARRAY_SIZE(usb_ohci_resources), 119 .resource = usb_ohci_resources, 120 }; 121 122 static struct resource usbf_resources[] = { 123 [0] = { 124 .name = "sh_udc", 125 .start = 0xA4420000, 126 .end = 0xA44200FF, 127 .flags = IORESOURCE_MEM, 128 }, 129 [1] = { 130 .name = "sh_udc", 131 .start = evt2irq(0xa20), 132 .end = evt2irq(0xa20), 133 .flags = IORESOURCE_IRQ, 134 }, 135 }; 136 137 static struct platform_device usbf_device = { 138 .name = "sh_udc", 139 .id = -1, 140 .dev = { 141 .dma_mask = NULL, 142 .coherent_dma_mask = 0xffffffff, 143 }, 144 .num_resources = ARRAY_SIZE(usbf_resources), 145 .resource = usbf_resources, 146 }; 147 148 static struct sh_timer_config cmt_platform_data = { 149 .channels_mask = 0x1f, 150 }; 151 152 static struct resource cmt_resources[] = { 153 DEFINE_RES_MEM(0x044a0000, 0x60), 154 DEFINE_RES_IRQ(evt2irq(0xf00)), 155 }; 156 157 static struct platform_device cmt_device = { 158 .name = "sh-cmt-32", 159 .id = 0, 160 .dev = { 161 .platform_data = &cmt_platform_data, 162 }, 163 .resource = cmt_resources, 164 .num_resources = ARRAY_SIZE(cmt_resources), 165 }; 166 167 static struct sh_timer_config tmu0_platform_data = { 168 .channels_mask = 7, 169 }; 170 171 static struct resource tmu0_resources[] = { 172 DEFINE_RES_MEM(0xa412fe90, 0x28), 173 DEFINE_RES_IRQ(evt2irq(0x400)), 174 DEFINE_RES_IRQ(evt2irq(0x420)), 175 DEFINE_RES_IRQ(evt2irq(0x440)), 176 }; 177 178 static struct platform_device tmu0_device = { 179 .name = "sh-tmu-sh3", 180 .id = 0, 181 .dev = { 182 .platform_data = &tmu0_platform_data, 183 }, 184 .resource = tmu0_resources, 185 .num_resources = ARRAY_SIZE(tmu0_resources), 186 }; 187 188 static struct platform_device *sh7720_devices[] __initdata = { 189 &scif0_device, 190 &scif1_device, 191 &cmt_device, 192 &tmu0_device, 193 &rtc_device, 194 &usb_ohci_device, 195 &usbf_device, 196 }; 197 198 static int __init sh7720_devices_setup(void) 199 { 200 return platform_add_devices(sh7720_devices, 201 ARRAY_SIZE(sh7720_devices)); 202 } 203 arch_initcall(sh7720_devices_setup); 204 205 static struct platform_device *sh7720_early_devices[] __initdata = { 206 &scif0_device, 207 &scif1_device, 208 &cmt_device, 209 &tmu0_device, 210 }; 211 212 void __init plat_early_device_setup(void) 213 { 214 early_platform_add_devices(sh7720_early_devices, 215 ARRAY_SIZE(sh7720_early_devices)); 216 } 217 218 enum { 219 UNUSED = 0, 220 221 /* interrupt sources */ 222 TMU0, TMU1, TMU2, RTC, 223 WDT, REF_RCMI, SIM, 224 IRQ0, IRQ1, IRQ2, IRQ3, 225 USBF_SPD, TMU_SUNI, IRQ5, IRQ4, 226 DMAC1, LCDC, SSL, 227 ADC, DMAC2, USBFI, CMT, 228 SCIF0, SCIF1, 229 PINT07, PINT815, TPU, IIC, 230 SIOF0, SIOF1, MMC, PCC, 231 USBHI, AFEIF, 232 H_UDI, 233 }; 234 235 static struct intc_vect vectors[] __initdata = { 236 /* IRQ0->5 are handled in setup-sh3.c */ 237 INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420), 238 INTC_VECT(TMU2, 0x440), INTC_VECT(RTC, 0x480), 239 INTC_VECT(RTC, 0x4a0), INTC_VECT(RTC, 0x4c0), 240 INTC_VECT(SIM, 0x4e0), INTC_VECT(SIM, 0x500), 241 INTC_VECT(SIM, 0x520), INTC_VECT(SIM, 0x540), 242 INTC_VECT(WDT, 0x560), INTC_VECT(REF_RCMI, 0x580), 243 /* H_UDI cannot be masked */ INTC_VECT(TMU_SUNI, 0x6c0), 244 INTC_VECT(USBF_SPD, 0x6e0), INTC_VECT(DMAC1, 0x800), 245 INTC_VECT(DMAC1, 0x820), INTC_VECT(DMAC1, 0x840), 246 INTC_VECT(DMAC1, 0x860), INTC_VECT(LCDC, 0x900), 247 #if defined(CONFIG_CPU_SUBTYPE_SH7720) 248 INTC_VECT(SSL, 0x980), 249 #endif 250 INTC_VECT(USBFI, 0xa20), INTC_VECT(USBFI, 0xa40), 251 INTC_VECT(USBHI, 0xa60), 252 INTC_VECT(DMAC2, 0xb80), INTC_VECT(DMAC2, 0xba0), 253 INTC_VECT(ADC, 0xbe0), INTC_VECT(SCIF0, 0xc00), 254 INTC_VECT(SCIF1, 0xc20), INTC_VECT(PINT07, 0xc80), 255 INTC_VECT(PINT815, 0xca0), INTC_VECT(SIOF0, 0xd00), 256 INTC_VECT(SIOF1, 0xd20), INTC_VECT(TPU, 0xd80), 257 INTC_VECT(TPU, 0xda0), INTC_VECT(TPU, 0xdc0), 258 INTC_VECT(TPU, 0xde0), INTC_VECT(IIC, 0xe00), 259 INTC_VECT(MMC, 0xe80), INTC_VECT(MMC, 0xea0), 260 INTC_VECT(MMC, 0xec0), INTC_VECT(MMC, 0xee0), 261 INTC_VECT(CMT, 0xf00), INTC_VECT(PCC, 0xf60), 262 INTC_VECT(AFEIF, 0xfe0), 263 }; 264 265 static struct intc_prio_reg prio_registers[] __initdata = { 266 { 0xA414FEE2UL, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, RTC } }, 267 { 0xA414FEE4UL, 0, 16, 4, /* IPRB */ { WDT, REF_RCMI, SIM, 0 } }, 268 { 0xA4140016UL, 0, 16, 4, /* IPRC */ { IRQ3, IRQ2, IRQ1, IRQ0 } }, 269 { 0xA4140018UL, 0, 16, 4, /* IPRD */ { USBF_SPD, TMU_SUNI, IRQ5, IRQ4 } }, 270 { 0xA414001AUL, 0, 16, 4, /* IPRE */ { DMAC1, 0, LCDC, SSL } }, 271 { 0xA4080000UL, 0, 16, 4, /* IPRF */ { ADC, DMAC2, USBFI, CMT } }, 272 { 0xA4080002UL, 0, 16, 4, /* IPRG */ { SCIF0, SCIF1, 0, 0 } }, 273 { 0xA4080004UL, 0, 16, 4, /* IPRH */ { PINT07, PINT815, TPU, IIC } }, 274 { 0xA4080006UL, 0, 16, 4, /* IPRI */ { SIOF0, SIOF1, MMC, PCC } }, 275 { 0xA4080008UL, 0, 16, 4, /* IPRJ */ { 0, USBHI, 0, AFEIF } }, 276 }; 277 278 static DECLARE_INTC_DESC(intc_desc, "sh7720", vectors, NULL, 279 NULL, prio_registers, NULL); 280 281 void __init plat_irq_setup(void) 282 { 283 register_intc_controller(&intc_desc); 284 plat_irq_setup_sh3(); 285 } 286