1 /* 2 * Setup code for SH7720, SH7721. 3 * 4 * Copyright (C) 2007 Markus Brunner, Mark Jonas 5 * Copyright (C) 2009 Paul Mundt 6 * 7 * Based on arch/sh/kernel/cpu/sh4/setup-sh7750.c: 8 * 9 * Copyright (C) 2006 Paul Mundt 10 * Copyright (C) 2006 Jamie Lenehan 11 * 12 * This file is subject to the terms and conditions of the GNU General Public 13 * License. See the file "COPYING" in the main directory of this archive 14 * for more details. 15 */ 16 #include <linux/platform_device.h> 17 #include <linux/init.h> 18 #include <linux/serial.h> 19 #include <linux/io.h> 20 #include <linux/serial_sci.h> 21 #include <linux/sh_timer.h> 22 #include <linux/sh_intc.h> 23 #include <asm/rtc.h> 24 #include <cpu/serial.h> 25 26 static struct resource rtc_resources[] = { 27 [0] = { 28 .start = 0xa413fec0, 29 .end = 0xa413fec0 + 0x28 - 1, 30 .flags = IORESOURCE_IO, 31 }, 32 [1] = { 33 /* Shared Period/Carry/Alarm IRQ */ 34 .start = evt2irq(0x480), 35 .flags = IORESOURCE_IRQ, 36 }, 37 }; 38 39 static struct sh_rtc_platform_info rtc_info = { 40 .capabilities = RTC_CAP_4_DIGIT_YEAR, 41 }; 42 43 static struct platform_device rtc_device = { 44 .name = "sh-rtc", 45 .id = -1, 46 .num_resources = ARRAY_SIZE(rtc_resources), 47 .resource = rtc_resources, 48 .dev = { 49 .platform_data = &rtc_info, 50 }, 51 }; 52 53 static struct plat_sci_port scif0_platform_data = { 54 .mapbase = 0xa4430000, 55 .flags = UPF_BOOT_AUTOCONF, 56 .scscr = SCSCR_RE | SCSCR_TE, 57 .scbrr_algo_id = SCBRR_ALGO_4, 58 .type = PORT_SCIF, 59 .irqs = SCIx_IRQ_MUXED(evt2irq(0xc00)), 60 .ops = &sh7720_sci_port_ops, 61 .regtype = SCIx_SH7705_SCIF_REGTYPE, 62 }; 63 64 static struct platform_device scif0_device = { 65 .name = "sh-sci", 66 .id = 0, 67 .dev = { 68 .platform_data = &scif0_platform_data, 69 }, 70 }; 71 72 static struct plat_sci_port scif1_platform_data = { 73 .mapbase = 0xa4438000, 74 .flags = UPF_BOOT_AUTOCONF, 75 .scscr = SCSCR_RE | SCSCR_TE, 76 .scbrr_algo_id = SCBRR_ALGO_4, 77 .type = PORT_SCIF, 78 .irqs = SCIx_IRQ_MUXED(evt2irq(0xc20)), 79 .ops = &sh7720_sci_port_ops, 80 .regtype = SCIx_SH7705_SCIF_REGTYPE, 81 }; 82 83 static struct platform_device scif1_device = { 84 .name = "sh-sci", 85 .id = 1, 86 .dev = { 87 .platform_data = &scif1_platform_data, 88 }, 89 }; 90 91 static struct resource usb_ohci_resources[] = { 92 [0] = { 93 .start = 0xA4428000, 94 .end = 0xA44280FF, 95 .flags = IORESOURCE_MEM, 96 }, 97 [1] = { 98 .start = evt2irq(0xa60), 99 .end = evt2irq(0xa60), 100 .flags = IORESOURCE_IRQ, 101 }, 102 }; 103 104 static u64 usb_ohci_dma_mask = 0xffffffffUL; 105 106 static struct platform_device usb_ohci_device = { 107 .name = "sh_ohci", 108 .id = -1, 109 .dev = { 110 .dma_mask = &usb_ohci_dma_mask, 111 .coherent_dma_mask = 0xffffffff, 112 }, 113 .num_resources = ARRAY_SIZE(usb_ohci_resources), 114 .resource = usb_ohci_resources, 115 }; 116 117 static struct resource usbf_resources[] = { 118 [0] = { 119 .name = "sh_udc", 120 .start = 0xA4420000, 121 .end = 0xA44200FF, 122 .flags = IORESOURCE_MEM, 123 }, 124 [1] = { 125 .name = "sh_udc", 126 .start = evt2irq(0xa20), 127 .end = evt2irq(0xa20), 128 .flags = IORESOURCE_IRQ, 129 }, 130 }; 131 132 static struct platform_device usbf_device = { 133 .name = "sh_udc", 134 .id = -1, 135 .dev = { 136 .dma_mask = NULL, 137 .coherent_dma_mask = 0xffffffff, 138 }, 139 .num_resources = ARRAY_SIZE(usbf_resources), 140 .resource = usbf_resources, 141 }; 142 143 static struct sh_timer_config cmt0_platform_data = { 144 .channel_offset = 0x10, 145 .timer_bit = 0, 146 .clockevent_rating = 125, 147 .clocksource_rating = 125, 148 }; 149 150 static struct resource cmt0_resources[] = { 151 [0] = { 152 .start = 0x044a0010, 153 .end = 0x044a001b, 154 .flags = IORESOURCE_MEM, 155 }, 156 [1] = { 157 .start = evt2irq(0xf00), 158 .flags = IORESOURCE_IRQ, 159 }, 160 }; 161 162 static struct platform_device cmt0_device = { 163 .name = "sh_cmt", 164 .id = 0, 165 .dev = { 166 .platform_data = &cmt0_platform_data, 167 }, 168 .resource = cmt0_resources, 169 .num_resources = ARRAY_SIZE(cmt0_resources), 170 }; 171 172 static struct sh_timer_config cmt1_platform_data = { 173 .channel_offset = 0x20, 174 .timer_bit = 1, 175 }; 176 177 static struct resource cmt1_resources[] = { 178 [0] = { 179 .start = 0x044a0020, 180 .end = 0x044a002b, 181 .flags = IORESOURCE_MEM, 182 }, 183 [1] = { 184 .start = evt2irq(0xf00), 185 .flags = IORESOURCE_IRQ, 186 }, 187 }; 188 189 static struct platform_device cmt1_device = { 190 .name = "sh_cmt", 191 .id = 1, 192 .dev = { 193 .platform_data = &cmt1_platform_data, 194 }, 195 .resource = cmt1_resources, 196 .num_resources = ARRAY_SIZE(cmt1_resources), 197 }; 198 199 static struct sh_timer_config cmt2_platform_data = { 200 .channel_offset = 0x30, 201 .timer_bit = 2, 202 }; 203 204 static struct resource cmt2_resources[] = { 205 [0] = { 206 .start = 0x044a0030, 207 .end = 0x044a003b, 208 .flags = IORESOURCE_MEM, 209 }, 210 [1] = { 211 .start = evt2irq(0xf00), 212 .flags = IORESOURCE_IRQ, 213 }, 214 }; 215 216 static struct platform_device cmt2_device = { 217 .name = "sh_cmt", 218 .id = 2, 219 .dev = { 220 .platform_data = &cmt2_platform_data, 221 }, 222 .resource = cmt2_resources, 223 .num_resources = ARRAY_SIZE(cmt2_resources), 224 }; 225 226 static struct sh_timer_config cmt3_platform_data = { 227 .channel_offset = 0x40, 228 .timer_bit = 3, 229 }; 230 231 static struct resource cmt3_resources[] = { 232 [0] = { 233 .start = 0x044a0040, 234 .end = 0x044a004b, 235 .flags = IORESOURCE_MEM, 236 }, 237 [1] = { 238 .start = evt2irq(0xf00), 239 .flags = IORESOURCE_IRQ, 240 }, 241 }; 242 243 static struct platform_device cmt3_device = { 244 .name = "sh_cmt", 245 .id = 3, 246 .dev = { 247 .platform_data = &cmt3_platform_data, 248 }, 249 .resource = cmt3_resources, 250 .num_resources = ARRAY_SIZE(cmt3_resources), 251 }; 252 253 static struct sh_timer_config cmt4_platform_data = { 254 .channel_offset = 0x50, 255 .timer_bit = 4, 256 }; 257 258 static struct resource cmt4_resources[] = { 259 [0] = { 260 .start = 0x044a0050, 261 .end = 0x044a005b, 262 .flags = IORESOURCE_MEM, 263 }, 264 [1] = { 265 .start = evt2irq(0xf00), 266 .flags = IORESOURCE_IRQ, 267 }, 268 }; 269 270 static struct platform_device cmt4_device = { 271 .name = "sh_cmt", 272 .id = 4, 273 .dev = { 274 .platform_data = &cmt4_platform_data, 275 }, 276 .resource = cmt4_resources, 277 .num_resources = ARRAY_SIZE(cmt4_resources), 278 }; 279 280 static struct sh_timer_config tmu0_platform_data = { 281 .channel_offset = 0x02, 282 .timer_bit = 0, 283 .clockevent_rating = 200, 284 }; 285 286 static struct resource tmu0_resources[] = { 287 [0] = { 288 .start = 0xa412fe94, 289 .end = 0xa412fe9f, 290 .flags = IORESOURCE_MEM, 291 }, 292 [1] = { 293 .start = evt2irq(0x400), 294 .flags = IORESOURCE_IRQ, 295 }, 296 }; 297 298 static struct platform_device tmu0_device = { 299 .name = "sh_tmu", 300 .id = 0, 301 .dev = { 302 .platform_data = &tmu0_platform_data, 303 }, 304 .resource = tmu0_resources, 305 .num_resources = ARRAY_SIZE(tmu0_resources), 306 }; 307 308 static struct sh_timer_config tmu1_platform_data = { 309 .channel_offset = 0xe, 310 .timer_bit = 1, 311 .clocksource_rating = 200, 312 }; 313 314 static struct resource tmu1_resources[] = { 315 [0] = { 316 .start = 0xa412fea0, 317 .end = 0xa412feab, 318 .flags = IORESOURCE_MEM, 319 }, 320 [1] = { 321 .start = evt2irq(0x420), 322 .flags = IORESOURCE_IRQ, 323 }, 324 }; 325 326 static struct platform_device tmu1_device = { 327 .name = "sh_tmu", 328 .id = 1, 329 .dev = { 330 .platform_data = &tmu1_platform_data, 331 }, 332 .resource = tmu1_resources, 333 .num_resources = ARRAY_SIZE(tmu1_resources), 334 }; 335 336 static struct sh_timer_config tmu2_platform_data = { 337 .channel_offset = 0x1a, 338 .timer_bit = 2, 339 }; 340 341 static struct resource tmu2_resources[] = { 342 [0] = { 343 .start = 0xa412feac, 344 .end = 0xa412feb5, 345 .flags = IORESOURCE_MEM, 346 }, 347 [1] = { 348 .start = evt2irq(0x440), 349 .flags = IORESOURCE_IRQ, 350 }, 351 }; 352 353 static struct platform_device tmu2_device = { 354 .name = "sh_tmu", 355 .id = 2, 356 .dev = { 357 .platform_data = &tmu2_platform_data, 358 }, 359 .resource = tmu2_resources, 360 .num_resources = ARRAY_SIZE(tmu2_resources), 361 }; 362 363 static struct platform_device *sh7720_devices[] __initdata = { 364 &scif0_device, 365 &scif1_device, 366 &cmt0_device, 367 &cmt1_device, 368 &cmt2_device, 369 &cmt3_device, 370 &cmt4_device, 371 &tmu0_device, 372 &tmu1_device, 373 &tmu2_device, 374 &rtc_device, 375 &usb_ohci_device, 376 &usbf_device, 377 }; 378 379 static int __init sh7720_devices_setup(void) 380 { 381 return platform_add_devices(sh7720_devices, 382 ARRAY_SIZE(sh7720_devices)); 383 } 384 arch_initcall(sh7720_devices_setup); 385 386 static struct platform_device *sh7720_early_devices[] __initdata = { 387 &scif0_device, 388 &scif1_device, 389 &cmt0_device, 390 &cmt1_device, 391 &cmt2_device, 392 &cmt3_device, 393 &cmt4_device, 394 &tmu0_device, 395 &tmu1_device, 396 &tmu2_device, 397 }; 398 399 void __init plat_early_device_setup(void) 400 { 401 early_platform_add_devices(sh7720_early_devices, 402 ARRAY_SIZE(sh7720_early_devices)); 403 } 404 405 enum { 406 UNUSED = 0, 407 408 /* interrupt sources */ 409 TMU0, TMU1, TMU2, RTC, 410 WDT, REF_RCMI, SIM, 411 IRQ0, IRQ1, IRQ2, IRQ3, 412 USBF_SPD, TMU_SUNI, IRQ5, IRQ4, 413 DMAC1, LCDC, SSL, 414 ADC, DMAC2, USBFI, CMT, 415 SCIF0, SCIF1, 416 PINT07, PINT815, TPU, IIC, 417 SIOF0, SIOF1, MMC, PCC, 418 USBHI, AFEIF, 419 H_UDI, 420 }; 421 422 static struct intc_vect vectors[] __initdata = { 423 /* IRQ0->5 are handled in setup-sh3.c */ 424 INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420), 425 INTC_VECT(TMU2, 0x440), INTC_VECT(RTC, 0x480), 426 INTC_VECT(RTC, 0x4a0), INTC_VECT(RTC, 0x4c0), 427 INTC_VECT(SIM, 0x4e0), INTC_VECT(SIM, 0x500), 428 INTC_VECT(SIM, 0x520), INTC_VECT(SIM, 0x540), 429 INTC_VECT(WDT, 0x560), INTC_VECT(REF_RCMI, 0x580), 430 /* H_UDI cannot be masked */ INTC_VECT(TMU_SUNI, 0x6c0), 431 INTC_VECT(USBF_SPD, 0x6e0), INTC_VECT(DMAC1, 0x800), 432 INTC_VECT(DMAC1, 0x820), INTC_VECT(DMAC1, 0x840), 433 INTC_VECT(DMAC1, 0x860), INTC_VECT(LCDC, 0x900), 434 #if defined(CONFIG_CPU_SUBTYPE_SH7720) 435 INTC_VECT(SSL, 0x980), 436 #endif 437 INTC_VECT(USBFI, 0xa20), INTC_VECT(USBFI, 0xa40), 438 INTC_VECT(USBHI, 0xa60), 439 INTC_VECT(DMAC2, 0xb80), INTC_VECT(DMAC2, 0xba0), 440 INTC_VECT(ADC, 0xbe0), INTC_VECT(SCIF0, 0xc00), 441 INTC_VECT(SCIF1, 0xc20), INTC_VECT(PINT07, 0xc80), 442 INTC_VECT(PINT815, 0xca0), INTC_VECT(SIOF0, 0xd00), 443 INTC_VECT(SIOF1, 0xd20), INTC_VECT(TPU, 0xd80), 444 INTC_VECT(TPU, 0xda0), INTC_VECT(TPU, 0xdc0), 445 INTC_VECT(TPU, 0xde0), INTC_VECT(IIC, 0xe00), 446 INTC_VECT(MMC, 0xe80), INTC_VECT(MMC, 0xea0), 447 INTC_VECT(MMC, 0xec0), INTC_VECT(MMC, 0xee0), 448 INTC_VECT(CMT, 0xf00), INTC_VECT(PCC, 0xf60), 449 INTC_VECT(AFEIF, 0xfe0), 450 }; 451 452 static struct intc_prio_reg prio_registers[] __initdata = { 453 { 0xA414FEE2UL, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, RTC } }, 454 { 0xA414FEE4UL, 0, 16, 4, /* IPRB */ { WDT, REF_RCMI, SIM, 0 } }, 455 { 0xA4140016UL, 0, 16, 4, /* IPRC */ { IRQ3, IRQ2, IRQ1, IRQ0 } }, 456 { 0xA4140018UL, 0, 16, 4, /* IPRD */ { USBF_SPD, TMU_SUNI, IRQ5, IRQ4 } }, 457 { 0xA414001AUL, 0, 16, 4, /* IPRE */ { DMAC1, 0, LCDC, SSL } }, 458 { 0xA4080000UL, 0, 16, 4, /* IPRF */ { ADC, DMAC2, USBFI, CMT } }, 459 { 0xA4080002UL, 0, 16, 4, /* IPRG */ { SCIF0, SCIF1, 0, 0 } }, 460 { 0xA4080004UL, 0, 16, 4, /* IPRH */ { PINT07, PINT815, TPU, IIC } }, 461 { 0xA4080006UL, 0, 16, 4, /* IPRI */ { SIOF0, SIOF1, MMC, PCC } }, 462 { 0xA4080008UL, 0, 16, 4, /* IPRJ */ { 0, USBHI, 0, AFEIF } }, 463 }; 464 465 static DECLARE_INTC_DESC(intc_desc, "sh7720", vectors, NULL, 466 NULL, prio_registers, NULL); 467 468 void __init plat_irq_setup(void) 469 { 470 register_intc_controller(&intc_desc); 471 plat_irq_setup_sh3(); 472 } 473