1 /* 2 * SH3 Setup code for SH7710, SH7712 3 * 4 * Copyright (C) 2006 - 2009 Paul Mundt 5 * Copyright (C) 2007 Nobuhiro Iwamatsu 6 * 7 * This file is subject to the terms and conditions of the GNU General Public 8 * License. See the file "COPYING" in the main directory of this archive 9 * for more details. 10 */ 11 #include <linux/platform_device.h> 12 #include <linux/init.h> 13 #include <linux/irq.h> 14 #include <linux/serial.h> 15 #include <linux/serial_sci.h> 16 #include <linux/sh_timer.h> 17 #include <linux/sh_intc.h> 18 #include <asm/rtc.h> 19 20 enum { 21 UNUSED = 0, 22 23 /* interrupt sources */ 24 IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, 25 DMAC1, SCIF0, SCIF1, DMAC2, IPSEC, 26 EDMAC0, EDMAC1, EDMAC2, 27 SIOF0, SIOF1, 28 29 TMU0, TMU1, TMU2, 30 RTC, WDT, REF, 31 }; 32 33 static struct intc_vect vectors[] __initdata = { 34 /* IRQ0->5 are handled in setup-sh3.c */ 35 INTC_VECT(DMAC1, 0x800), INTC_VECT(DMAC1, 0x820), 36 INTC_VECT(DMAC1, 0x840), INTC_VECT(DMAC1, 0x860), 37 INTC_VECT(SCIF0, 0x880), INTC_VECT(SCIF0, 0x8a0), 38 INTC_VECT(SCIF0, 0x8c0), INTC_VECT(SCIF0, 0x8e0), 39 INTC_VECT(SCIF1, 0x900), INTC_VECT(SCIF1, 0x920), 40 INTC_VECT(SCIF1, 0x940), INTC_VECT(SCIF1, 0x960), 41 INTC_VECT(DMAC2, 0xb80), INTC_VECT(DMAC2, 0xba0), 42 #ifdef CONFIG_CPU_SUBTYPE_SH7710 43 INTC_VECT(IPSEC, 0xbe0), 44 #endif 45 INTC_VECT(EDMAC0, 0xc00), INTC_VECT(EDMAC1, 0xc20), 46 INTC_VECT(EDMAC2, 0xc40), 47 INTC_VECT(SIOF0, 0xe00), INTC_VECT(SIOF0, 0xe20), 48 INTC_VECT(SIOF0, 0xe40), INTC_VECT(SIOF0, 0xe60), 49 INTC_VECT(SIOF1, 0xe80), INTC_VECT(SIOF1, 0xea0), 50 INTC_VECT(SIOF1, 0xec0), INTC_VECT(SIOF1, 0xee0), 51 INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420), 52 INTC_VECT(TMU2, 0x440), 53 INTC_VECT(RTC, 0x480), INTC_VECT(RTC, 0x4a0), 54 INTC_VECT(RTC, 0x4c0), 55 INTC_VECT(WDT, 0x560), 56 INTC_VECT(REF, 0x580), 57 }; 58 59 static struct intc_prio_reg prio_registers[] __initdata = { 60 { 0xfffffee2, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, RTC } }, 61 { 0xfffffee4, 0, 16, 4, /* IPRB */ { WDT, REF, 0, 0 } }, 62 { 0xa4000016, 0, 16, 4, /* IPRC */ { IRQ3, IRQ2, IRQ1, IRQ0 } }, 63 { 0xa4000018, 0, 16, 4, /* IPRD */ { 0, 0, IRQ5, IRQ4 } }, 64 { 0xa400001a, 0, 16, 4, /* IPRE */ { DMAC1, SCIF0, SCIF1 } }, 65 { 0xa4080000, 0, 16, 4, /* IPRF */ { IPSEC, DMAC2 } }, 66 { 0xa4080002, 0, 16, 4, /* IPRG */ { EDMAC0, EDMAC1, EDMAC2 } }, 67 { 0xa4080004, 0, 16, 4, /* IPRH */ { 0, 0, 0, SIOF0 } }, 68 { 0xa4080006, 0, 16, 4, /* IPRI */ { 0, 0, SIOF1 } }, 69 }; 70 71 static DECLARE_INTC_DESC(intc_desc, "sh7710", vectors, NULL, 72 NULL, prio_registers, NULL); 73 74 static struct resource rtc_resources[] = { 75 [0] = { 76 .start = 0xa413fec0, 77 .end = 0xa413fec0 + 0x1e, 78 .flags = IORESOURCE_IO, 79 }, 80 [1] = { 81 .start = evt2irq(0x480), 82 .flags = IORESOURCE_IRQ, 83 }, 84 }; 85 86 static struct sh_rtc_platform_info rtc_info = { 87 .capabilities = RTC_CAP_4_DIGIT_YEAR, 88 }; 89 90 static struct platform_device rtc_device = { 91 .name = "sh-rtc", 92 .id = -1, 93 .num_resources = ARRAY_SIZE(rtc_resources), 94 .resource = rtc_resources, 95 .dev = { 96 .platform_data = &rtc_info, 97 }, 98 }; 99 100 static struct plat_sci_port scif0_platform_data = { 101 .mapbase = 0xa4400000, 102 .flags = UPF_BOOT_AUTOCONF, 103 .scscr = SCSCR_TE | SCSCR_RE | SCSCR_REIE | 104 SCSCR_CKE1 | SCSCR_CKE0, 105 .scbrr_algo_id = SCBRR_ALGO_2, 106 .type = PORT_SCIF, 107 .irqs = SCIx_IRQ_MUXED(evt2irq(0x880)), 108 }; 109 110 static struct platform_device scif0_device = { 111 .name = "sh-sci", 112 .id = 0, 113 .dev = { 114 .platform_data = &scif0_platform_data, 115 }, 116 }; 117 118 static struct plat_sci_port scif1_platform_data = { 119 .mapbase = 0xa4410000, 120 .flags = UPF_BOOT_AUTOCONF, 121 .scscr = SCSCR_TE | SCSCR_RE | SCSCR_REIE | 122 SCSCR_CKE1 | SCSCR_CKE0, 123 .scbrr_algo_id = SCBRR_ALGO_2, 124 .type = PORT_SCIF, 125 .irqs = SCIx_IRQ_MUXED(evt2irq(0x900)), 126 }; 127 128 static struct platform_device scif1_device = { 129 .name = "sh-sci", 130 .id = 1, 131 .dev = { 132 .platform_data = &scif1_platform_data, 133 }, 134 }; 135 136 static struct sh_timer_config tmu0_platform_data = { 137 .channel_offset = 0x02, 138 .timer_bit = 0, 139 .clockevent_rating = 200, 140 }; 141 142 static struct resource tmu0_resources[] = { 143 [0] = { 144 .start = 0xa412fe94, 145 .end = 0xa412fe9f, 146 .flags = IORESOURCE_MEM, 147 }, 148 [1] = { 149 .start = evt2irq(0x400), 150 .flags = IORESOURCE_IRQ, 151 }, 152 }; 153 154 static struct platform_device tmu0_device = { 155 .name = "sh_tmu", 156 .id = 0, 157 .dev = { 158 .platform_data = &tmu0_platform_data, 159 }, 160 .resource = tmu0_resources, 161 .num_resources = ARRAY_SIZE(tmu0_resources), 162 }; 163 164 static struct sh_timer_config tmu1_platform_data = { 165 .channel_offset = 0xe, 166 .timer_bit = 1, 167 .clocksource_rating = 200, 168 }; 169 170 static struct resource tmu1_resources[] = { 171 [0] = { 172 .start = 0xa412fea0, 173 .end = 0xa412feab, 174 .flags = IORESOURCE_MEM, 175 }, 176 [1] = { 177 .start = evt2irq(0x420), 178 .flags = IORESOURCE_IRQ, 179 }, 180 }; 181 182 static struct platform_device tmu1_device = { 183 .name = "sh_tmu", 184 .id = 1, 185 .dev = { 186 .platform_data = &tmu1_platform_data, 187 }, 188 .resource = tmu1_resources, 189 .num_resources = ARRAY_SIZE(tmu1_resources), 190 }; 191 192 static struct sh_timer_config tmu2_platform_data = { 193 .channel_offset = 0x1a, 194 .timer_bit = 2, 195 }; 196 197 static struct resource tmu2_resources[] = { 198 [0] = { 199 .start = 0xa412feac, 200 .end = 0xa412feb5, 201 .flags = IORESOURCE_MEM, 202 }, 203 [1] = { 204 .start = evt2irq(0x440), 205 .flags = IORESOURCE_IRQ, 206 }, 207 }; 208 209 static struct platform_device tmu2_device = { 210 .name = "sh_tmu", 211 .id = 2, 212 .dev = { 213 .platform_data = &tmu2_platform_data, 214 }, 215 .resource = tmu2_resources, 216 .num_resources = ARRAY_SIZE(tmu2_resources), 217 }; 218 219 static struct platform_device *sh7710_devices[] __initdata = { 220 &scif0_device, 221 &scif1_device, 222 &tmu0_device, 223 &tmu1_device, 224 &tmu2_device, 225 &rtc_device, 226 }; 227 228 static int __init sh7710_devices_setup(void) 229 { 230 return platform_add_devices(sh7710_devices, 231 ARRAY_SIZE(sh7710_devices)); 232 } 233 arch_initcall(sh7710_devices_setup); 234 235 static struct platform_device *sh7710_early_devices[] __initdata = { 236 &scif0_device, 237 &scif1_device, 238 &tmu0_device, 239 &tmu1_device, 240 &tmu2_device, 241 }; 242 243 void __init plat_early_device_setup(void) 244 { 245 early_platform_add_devices(sh7710_early_devices, 246 ARRAY_SIZE(sh7710_early_devices)); 247 } 248 249 void __init plat_irq_setup(void) 250 { 251 register_intc_controller(&intc_desc); 252 plat_irq_setup_sh3(); 253 } 254