1 /* 2 * SH7201 setup 3 * 4 * Copyright (C) 2008 Peter Griffin pgriffin@mpc-data.co.uk 5 * 6 * This file is subject to the terms and conditions of the GNU General Public 7 * License. See the file "COPYING" in the main directory of this archive 8 * for more details. 9 */ 10 #include <linux/platform_device.h> 11 #include <linux/init.h> 12 #include <linux/serial.h> 13 #include <linux/serial_sci.h> 14 15 enum { 16 UNUSED = 0, 17 18 /* interrupt sources */ 19 IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7, 20 PINT0, PINT1, PINT2, PINT3, PINT4, PINT5, PINT6, PINT7, 21 ADC_ADI, 22 MTU2_TGI0A, MTU2_TGI0B, MTU2_TGI0C, MTU2_TGI0D, 23 MTU2_TCI0V, MTU2_TGI0E, MTU2_TGI0F, 24 MTU2_TGI1A, MTU2_TGI1B, MTU2_TCI1V, MTU2_TCI1U, 25 MTU2_TGI2A, MTU2_TGI2B, MTU2_TCI2V, MTU2_TCI2U, 26 MTU2_TGI3A, MTU2_TGI3B, MTU2_TGI3C, MTU2_TGI3D, MTU2_TCI3V, 27 MTU2_TGI4A, MTU2_TGI4B, MTU2_TGI4C, MTU2_TGI4D, MTU2_TCI4V, 28 MTU2_TGI5U, MTU2_TGI5V, MTU2_TGI5W, 29 RTC_ARM, RTC_PRD, RTC_CUP, 30 WDT, 31 IIC30_STPI, IIC30_NAKI, IIC30_RXI, IIC30_TXI, IIC30_TEI, 32 IIC31_STPI, IIC31_NAKI, IIC31_RXI, IIC31_TXI, IIC31_TEI, 33 IIC32_STPI, IIC32_NAKI, IIC32_RXI, IIC32_TXI, IIC32_TEI, 34 35 DMAC0_DMINT0, DMAC1_DMINT1, 36 DMAC2_DMINT2, DMAC3_DMINT3, 37 38 SCIF0_BRI, SCIF0_ERI, SCIF0_RXI, SCIF0_TXI, 39 SCIF1_BRI, SCIF1_ERI, SCIF1_RXI, SCIF1_TXI, 40 SCIF2_BRI, SCIF2_ERI, SCIF2_RXI, SCIF2_TXI, 41 SCIF3_BRI, SCIF3_ERI, SCIF3_RXI, SCIF3_TXI, 42 SCIF4_BRI, SCIF4_ERI, SCIF4_RXI, SCIF4_TXI, 43 SCIF5_BRI, SCIF5_ERI, SCIF5_RXI, SCIF5_TXI, 44 SCIF6_BRI, SCIF6_ERI, SCIF6_RXI, SCIF6_TXI, 45 SCIF7_BRI, SCIF7_ERI, SCIF7_RXI, SCIF7_TXI, 46 47 DMAC0_DMINTA, DMAC4_DMINT4, DMAC5_DMINT5, DMAC6_DMINT6, 48 DMAC7_DMINT7, 49 50 RCAN0_ERS, RCAN0_OVR, 51 RCAN0_SLE, 52 RCAN0_RM0, RCAN0_RM1, 53 54 RCAN1_ERS, RCAN1_OVR, 55 RCAN1_SLE, 56 RCAN1_RM0, RCAN1_RM1, 57 58 SSI0_SSII, SSI1_SSII, 59 60 TMR0_CMIA0, TMR0_CMIB0, TMR0_OVI0, 61 TMR1_CMIA1, TMR1_CMIB1, TMR1_OVI1, 62 63 /* interrupt groups */ 64 65 IRQ, PINT, ADC, 66 MTU20_ABCD, MTU20_VEF, MTU21_AB, MTU21_VU, MTU22_AB, MTU22_VU, 67 MTU23_ABCD, MTU24_ABCD, MTU25_UVW, 68 RTC, IIC30, IIC31, IIC32, 69 SCIF0, SCIF1, SCIF2, SCIF3, SCIF4, SCIF5, SCIF6, SCIF7, 70 RCAN0, RCAN1, TMR0, TMR1 71 72 }; 73 74 static struct intc_vect vectors[] __initdata = { 75 INTC_IRQ(IRQ0, 64), INTC_IRQ(IRQ1, 65), 76 INTC_IRQ(IRQ2, 66), INTC_IRQ(IRQ3, 67), 77 INTC_IRQ(IRQ4, 68), INTC_IRQ(IRQ5, 69), 78 INTC_IRQ(IRQ6, 70), INTC_IRQ(IRQ7, 71), 79 INTC_IRQ(PINT0, 80), INTC_IRQ(PINT1, 81), 80 INTC_IRQ(PINT2, 82), INTC_IRQ(PINT3, 83), 81 INTC_IRQ(PINT4, 84), INTC_IRQ(PINT5, 85), 82 INTC_IRQ(PINT6, 86), INTC_IRQ(PINT7, 87), 83 84 INTC_IRQ(ADC_ADI, 92), 85 86 INTC_IRQ(MTU2_TGI0A, 108), INTC_IRQ(MTU2_TGI0B, 109), 87 INTC_IRQ(MTU2_TGI0C, 110), INTC_IRQ(MTU2_TGI0D, 111), 88 INTC_IRQ(MTU2_TCI0V, 112), 89 INTC_IRQ(MTU2_TGI0E, 113), INTC_IRQ(MTU2_TGI0F, 114), 90 91 INTC_IRQ(MTU2_TGI1A, 116), INTC_IRQ(MTU2_TGI1B, 117), 92 INTC_IRQ(MTU2_TCI1V, 120), INTC_IRQ(MTU2_TCI1U, 121), 93 94 INTC_IRQ(MTU2_TGI2A, 124), INTC_IRQ(MTU2_TGI2B, 125), 95 INTC_IRQ(MTU2_TCI2V, 128), INTC_IRQ(MTU2_TCI2U, 129), 96 97 INTC_IRQ(MTU2_TGI3A, 132), INTC_IRQ(MTU2_TGI3B, 133), 98 INTC_IRQ(MTU2_TGI3C, 134), INTC_IRQ(MTU2_TGI3D, 135), 99 INTC_IRQ(MTU2_TCI3V, 136), 100 101 INTC_IRQ(MTU2_TGI4A, 140), INTC_IRQ(MTU2_TGI4B, 141), 102 INTC_IRQ(MTU2_TGI4C, 142), INTC_IRQ(MTU2_TGI4D, 143), 103 INTC_IRQ(MTU2_TCI4V, 144), 104 105 INTC_IRQ(MTU2_TGI5U, 148), INTC_IRQ(MTU2_TGI5V, 149), 106 INTC_IRQ(MTU2_TGI5W, 150), 107 108 INTC_IRQ(RTC_ARM, 152), INTC_IRQ(RTC_PRD, 153), 109 INTC_IRQ(RTC_CUP, 154), INTC_IRQ(WDT, 156), 110 111 INTC_IRQ(IIC30_STPI, 157), INTC_IRQ(IIC30_NAKI, 158), 112 INTC_IRQ(IIC30_RXI, 159), INTC_IRQ(IIC30_TXI, 160), 113 INTC_IRQ(IIC30_TEI, 161), 114 115 INTC_IRQ(IIC31_STPI, 164), INTC_IRQ(IIC31_NAKI, 165), 116 INTC_IRQ(IIC31_RXI, 166), INTC_IRQ(IIC31_TXI, 167), 117 INTC_IRQ(IIC31_TEI, 168), 118 119 INTC_IRQ(IIC32_STPI, 170), INTC_IRQ(IIC32_NAKI, 171), 120 INTC_IRQ(IIC32_RXI, 172), INTC_IRQ(IIC32_TXI, 173), 121 INTC_IRQ(IIC32_TEI, 174), 122 123 INTC_IRQ(DMAC0_DMINT0, 176), INTC_IRQ(DMAC1_DMINT1, 177), 124 INTC_IRQ(DMAC2_DMINT2, 178), INTC_IRQ(DMAC3_DMINT3, 179), 125 126 INTC_IRQ(SCIF0_BRI, 180), INTC_IRQ(SCIF0_ERI, 181), 127 INTC_IRQ(SCIF0_RXI, 182), INTC_IRQ(SCIF0_TXI, 183), 128 INTC_IRQ(SCIF1_BRI, 184), INTC_IRQ(SCIF1_ERI, 185), 129 INTC_IRQ(SCIF1_RXI, 186), INTC_IRQ(SCIF1_TXI, 187), 130 INTC_IRQ(SCIF2_BRI, 188), INTC_IRQ(SCIF2_ERI, 189), 131 INTC_IRQ(SCIF2_RXI, 190), INTC_IRQ(SCIF2_TXI, 191), 132 INTC_IRQ(SCIF3_BRI, 192), INTC_IRQ(SCIF3_ERI, 193), 133 INTC_IRQ(SCIF3_RXI, 194), INTC_IRQ(SCIF3_TXI, 195), 134 INTC_IRQ(SCIF4_BRI, 196), INTC_IRQ(SCIF4_ERI, 197), 135 INTC_IRQ(SCIF4_RXI, 198), INTC_IRQ(SCIF4_TXI, 199), 136 INTC_IRQ(SCIF5_BRI, 200), INTC_IRQ(SCIF5_ERI, 201), 137 INTC_IRQ(SCIF5_RXI, 202), INTC_IRQ(SCIF5_TXI, 203), 138 INTC_IRQ(SCIF6_BRI, 204), INTC_IRQ(SCIF6_ERI, 205), 139 INTC_IRQ(SCIF6_RXI, 206), INTC_IRQ(SCIF6_TXI, 207), 140 INTC_IRQ(SCIF7_BRI, 208), INTC_IRQ(SCIF7_ERI, 209), 141 INTC_IRQ(SCIF7_RXI, 210), INTC_IRQ(SCIF7_TXI, 211), 142 143 INTC_IRQ(DMAC0_DMINTA, 212), INTC_IRQ(DMAC4_DMINT4, 216), 144 INTC_IRQ(DMAC5_DMINT5, 217), INTC_IRQ(DMAC6_DMINT6, 218), 145 INTC_IRQ(DMAC7_DMINT7, 219), 146 147 INTC_IRQ(RCAN0_ERS, 228), INTC_IRQ(RCAN0_OVR, 229), 148 INTC_IRQ(RCAN0_SLE, 230), 149 INTC_IRQ(RCAN0_RM0, 231), INTC_IRQ(RCAN0_RM1, 232), 150 151 INTC_IRQ(RCAN1_ERS, 234), INTC_IRQ(RCAN1_OVR, 235), 152 INTC_IRQ(RCAN1_SLE, 236), 153 INTC_IRQ(RCAN1_RM0, 237), INTC_IRQ(RCAN1_RM1, 238), 154 155 INTC_IRQ(SSI0_SSII, 244), INTC_IRQ(SSI1_SSII, 245), 156 157 INTC_IRQ(TMR0_CMIA0, 246), INTC_IRQ(TMR0_CMIB0, 247), 158 INTC_IRQ(TMR0_OVI0, 248), 159 160 INTC_IRQ(TMR1_CMIA1, 252), INTC_IRQ(TMR1_CMIB1, 253), 161 INTC_IRQ(TMR1_OVI1, 254), 162 163 }; 164 165 static struct intc_group groups[] __initdata = { 166 INTC_GROUP(PINT, PINT0, PINT1, PINT2, PINT3, 167 PINT4, PINT5, PINT6, PINT7), 168 INTC_GROUP(MTU20_ABCD, MTU2_TGI0A, MTU2_TGI0B, MTU2_TGI0C, MTU2_TGI0D), 169 INTC_GROUP(MTU20_VEF, MTU2_TCI0V, MTU2_TGI0E, MTU2_TGI0F), 170 171 INTC_GROUP(MTU21_AB, MTU2_TGI1A, MTU2_TGI1B), 172 INTC_GROUP(MTU21_VU, MTU2_TCI1V, MTU2_TCI1U), 173 INTC_GROUP(MTU22_AB, MTU2_TGI2A, MTU2_TGI2B), 174 INTC_GROUP(MTU22_VU, MTU2_TCI2V, MTU2_TCI2U), 175 INTC_GROUP(MTU23_ABCD, MTU2_TGI3A, MTU2_TGI3B, MTU2_TGI3C, MTU2_TGI3D), 176 INTC_GROUP(MTU24_ABCD, MTU2_TGI4A, MTU2_TGI4B, MTU2_TGI4C, MTU2_TGI4D), 177 INTC_GROUP(MTU25_UVW, MTU2_TGI5U, MTU2_TGI5V, MTU2_TGI5W), 178 INTC_GROUP(RTC, RTC_ARM, RTC_PRD, RTC_CUP ), 179 180 INTC_GROUP(IIC30, IIC30_STPI, IIC30_NAKI, IIC30_RXI, IIC30_TXI, 181 IIC30_TEI), 182 INTC_GROUP(IIC31, IIC31_STPI, IIC31_NAKI, IIC31_RXI, IIC31_TXI, 183 IIC31_TEI), 184 INTC_GROUP(IIC32, IIC32_STPI, IIC32_NAKI, IIC32_RXI, IIC32_TXI, 185 IIC32_TEI), 186 187 INTC_GROUP(SCIF0, SCIF0_BRI, SCIF0_ERI, SCIF0_RXI, SCIF0_TXI), 188 INTC_GROUP(SCIF1, SCIF1_BRI, SCIF1_ERI, SCIF1_RXI, SCIF1_TXI), 189 INTC_GROUP(SCIF2, SCIF2_BRI, SCIF2_ERI, SCIF2_RXI, SCIF2_TXI), 190 INTC_GROUP(SCIF3, SCIF3_BRI, SCIF3_ERI, SCIF3_RXI, SCIF3_TXI), 191 INTC_GROUP(SCIF4, SCIF4_BRI, SCIF4_ERI, SCIF4_RXI, SCIF4_TXI), 192 INTC_GROUP(SCIF5, SCIF5_BRI, SCIF5_ERI, SCIF5_RXI, SCIF5_TXI), 193 INTC_GROUP(SCIF6, SCIF6_BRI, SCIF6_ERI, SCIF6_RXI, SCIF6_TXI), 194 INTC_GROUP(SCIF7, SCIF7_BRI, SCIF7_ERI, SCIF7_RXI, SCIF7_TXI), 195 196 INTC_GROUP(RCAN0, RCAN0_ERS, RCAN0_OVR, RCAN0_RM0, RCAN0_RM1, 197 RCAN0_SLE), 198 INTC_GROUP(RCAN1, RCAN1_ERS, RCAN1_OVR, RCAN1_RM0, RCAN1_RM1, 199 RCAN1_SLE), 200 201 INTC_GROUP(TMR0, TMR0_CMIA0, TMR0_CMIB0, TMR0_OVI0), 202 INTC_GROUP(TMR1, TMR1_CMIA1, TMR1_CMIB1, TMR1_OVI1), 203 }; 204 205 static struct intc_prio_reg prio_registers[] __initdata = { 206 { 0xfffe9418, 0, 16, 4, /* IPR01 */ { IRQ0, IRQ1, IRQ2, IRQ3 } }, 207 { 0xfffe941a, 0, 16, 4, /* IPR02 */ { IRQ4, IRQ5, IRQ6, IRQ7 } }, 208 { 0xfffe9420, 0, 16, 4, /* IPR05 */ { PINT, 0, ADC_ADI, 0 } }, 209 { 0xfffe9800, 0, 16, 4, /* IPR06 */ { 0, MTU20_ABCD, MTU20_VEF, MTU21_AB } }, 210 { 0xfffe9802, 0, 16, 4, /* IPR07 */ { MTU21_VU, MTU22_AB, MTU22_VU, MTU23_ABCD } }, 211 { 0xfffe9804, 0, 16, 4, /* IPR08 */ { MTU2_TCI3V, MTU24_ABCD, MTU2_TCI4V, MTU25_UVW } }, 212 213 { 0xfffe9806, 0, 16, 4, /* IPR09 */ { RTC, WDT, IIC30, 0 } }, 214 { 0xfffe9808, 0, 16, 4, /* IPR10 */ { IIC31, IIC32, DMAC0_DMINT0, DMAC1_DMINT1 } }, 215 { 0xfffe980a, 0, 16, 4, /* IPR11 */ { DMAC2_DMINT2, DMAC3_DMINT3, SCIF0 , SCIF1 } }, 216 { 0xfffe980c, 0, 16, 4, /* IPR12 */ { SCIF2, SCIF3, SCIF4, SCIF5 } }, 217 { 0xfffe980e, 0, 16, 4, /* IPR13 */ { SCIF6, SCIF7, DMAC0_DMINTA, DMAC4_DMINT4 } }, 218 { 0xfffe9810, 0, 16, 4, /* IPR14 */ { DMAC5_DMINT5, DMAC6_DMINT6, DMAC7_DMINT7, 0 } }, 219 { 0xfffe9812, 0, 16, 4, /* IPR15 */ { 0, RCAN0, RCAN1, 0 } }, 220 { 0xfffe9814, 0, 16, 4, /* IPR16 */ { SSI0_SSII, SSI1_SSII, TMR0, TMR1 } }, 221 }; 222 223 static struct intc_mask_reg mask_registers[] __initdata = { 224 { 0xfffe9408, 0, 16, /* PINTER */ 225 { 0, 0, 0, 0, 0, 0, 0, 0, 226 PINT7, PINT6, PINT5, PINT4, PINT3, PINT2, PINT1, PINT0 } }, 227 }; 228 229 static DECLARE_INTC_DESC(intc_desc, "sh7201", vectors, groups, 230 mask_registers, prio_registers, NULL); 231 232 static struct plat_sci_port sci_platform_data[] = { 233 { 234 .mapbase = 0xfffe8000, 235 .flags = UPF_BOOT_AUTOCONF, 236 .type = PORT_SCIF, 237 .irqs = { 181, 182, 183, 180} 238 }, { 239 .mapbase = 0xfffe8800, 240 .flags = UPF_BOOT_AUTOCONF, 241 .type = PORT_SCIF, 242 .irqs = { 185, 186, 187, 184} 243 }, { 244 .mapbase = 0xfffe9000, 245 .flags = UPF_BOOT_AUTOCONF, 246 .type = PORT_SCIF, 247 .irqs = { 189, 186, 187, 188} 248 }, { 249 .mapbase = 0xfffe9800, 250 .flags = UPF_BOOT_AUTOCONF, 251 .type = PORT_SCIF, 252 .irqs = { 193, 194, 195, 192} 253 }, { 254 .mapbase = 0xfffea000, 255 .flags = UPF_BOOT_AUTOCONF, 256 .type = PORT_SCIF, 257 .irqs = { 196, 198, 199, 196} 258 }, { 259 .mapbase = 0xfffea800, 260 .flags = UPF_BOOT_AUTOCONF, 261 .type = PORT_SCIF, 262 .irqs = { 201, 202, 203, 200} 263 }, { 264 .mapbase = 0xfffeb000, 265 .flags = UPF_BOOT_AUTOCONF, 266 .type = PORT_SCIF, 267 .irqs = { 205, 206, 207, 204} 268 }, { 269 .mapbase = 0xfffeb800, 270 .flags = UPF_BOOT_AUTOCONF, 271 .type = PORT_SCIF, 272 .irqs = { 209, 210, 211, 208} 273 }, { 274 .flags = 0, 275 } 276 }; 277 278 static struct platform_device sci_device = { 279 .name = "sh-sci", 280 .id = -1, 281 .dev = { 282 .platform_data = sci_platform_data, 283 }, 284 }; 285 286 static struct resource rtc_resources[] = { 287 [0] = { 288 .start = 0xffff0800, 289 .end = 0xffff2000 + 0x58 - 1, 290 .flags = IORESOURCE_IO, 291 }, 292 [1] = { 293 /* Period IRQ */ 294 .start = 153, 295 .flags = IORESOURCE_IRQ, 296 }, 297 [2] = { 298 /* Carry IRQ */ 299 .start = 154, 300 .flags = IORESOURCE_IRQ, 301 }, 302 [3] = { 303 /* Alarm IRQ */ 304 .start = 152, 305 .flags = IORESOURCE_IRQ, 306 }, 307 }; 308 309 static struct platform_device rtc_device = { 310 .name = "sh-rtc", 311 .id = -1, 312 .num_resources = ARRAY_SIZE(rtc_resources), 313 .resource = rtc_resources, 314 }; 315 316 static struct platform_device *sh7201_devices[] __initdata = { 317 &sci_device, 318 &rtc_device, 319 }; 320 321 static int __init sh7201_devices_setup(void) 322 { 323 return platform_add_devices(sh7201_devices, 324 ARRAY_SIZE(sh7201_devices)); 325 } 326 __initcall(sh7201_devices_setup); 327 328 void __init plat_irq_setup(void) 329 { 330 register_intc_controller(&intc_desc); 331 } 332