1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * arch/sh/kernel/cpu/sh2a/clock-sh7206.c 4 * 5 * SH7206 support for the clock framework 6 * 7 * Copyright (C) 2006 Yoshinori Sato 8 * 9 * Based on clock-sh4.c 10 * Copyright (C) 2005 Paul Mundt 11 */ 12 #include <linux/init.h> 13 #include <linux/kernel.h> 14 #include <asm/clock.h> 15 #include <asm/freq.h> 16 #include <asm/io.h> 17 18 static const int pll1rate[]={1,2,3,4,6,8}; 19 static const int pfc_divisors[]={1,2,3,4,6,8,12}; 20 #define ifc_divisors pfc_divisors 21 22 static unsigned int pll2_mult; 23 24 static void master_clk_init(struct clk *clk) 25 { 26 clk->rate *= pll2_mult * pll1rate[(__raw_readw(FREQCR) >> 8) & 0x0007]; 27 } 28 29 static struct sh_clk_ops sh7206_master_clk_ops = { 30 .init = master_clk_init, 31 }; 32 33 static unsigned long module_clk_recalc(struct clk *clk) 34 { 35 int idx = (__raw_readw(FREQCR) & 0x0007); 36 return clk->parent->rate / pfc_divisors[idx]; 37 } 38 39 static struct sh_clk_ops sh7206_module_clk_ops = { 40 .recalc = module_clk_recalc, 41 }; 42 43 static unsigned long bus_clk_recalc(struct clk *clk) 44 { 45 return clk->parent->rate / pll1rate[(__raw_readw(FREQCR) >> 8) & 0x0007]; 46 } 47 48 static struct sh_clk_ops sh7206_bus_clk_ops = { 49 .recalc = bus_clk_recalc, 50 }; 51 52 static unsigned long cpu_clk_recalc(struct clk *clk) 53 { 54 int idx = (__raw_readw(FREQCR) & 0x0007); 55 return clk->parent->rate / ifc_divisors[idx]; 56 } 57 58 static struct sh_clk_ops sh7206_cpu_clk_ops = { 59 .recalc = cpu_clk_recalc, 60 }; 61 62 static struct sh_clk_ops *sh7206_clk_ops[] = { 63 &sh7206_master_clk_ops, 64 &sh7206_module_clk_ops, 65 &sh7206_bus_clk_ops, 66 &sh7206_cpu_clk_ops, 67 }; 68 69 void __init arch_init_clk_ops(struct sh_clk_ops **ops, int idx) 70 { 71 if (test_mode_pin(MODE_PIN2 | MODE_PIN1 | MODE_PIN0)) 72 pll2_mult = 1; 73 else if (test_mode_pin(MODE_PIN2 | MODE_PIN1)) 74 pll2_mult = 2; 75 else if (test_mode_pin(MODE_PIN1)) 76 pll2_mult = 4; 77 78 if (idx < ARRAY_SIZE(sh7206_clk_ops)) 79 *ops = sh7206_clk_ops[idx]; 80 } 81