1 /* 2 * SH7619 Setup 3 * 4 * Copyright (C) 2006 Yoshinori Sato 5 * Copyright (C) 2009 Paul Mundt 6 * 7 * This file is subject to the terms and conditions of the GNU General Public 8 * License. See the file "COPYING" in the main directory of this archive 9 * for more details. 10 */ 11 #include <linux/platform_device.h> 12 #include <linux/init.h> 13 #include <linux/serial.h> 14 #include <linux/serial_sci.h> 15 #include <linux/sh_eth.h> 16 #include <linux/sh_timer.h> 17 #include <linux/io.h> 18 19 enum { 20 UNUSED = 0, 21 22 /* interrupt sources */ 23 IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7, 24 WDT, EDMAC, CMT0, CMT1, 25 SCIF0, SCIF1, SCIF2, 26 HIF_HIFI, HIF_HIFBI, 27 DMAC0, DMAC1, DMAC2, DMAC3, 28 SIOF, 29 }; 30 31 static struct intc_vect vectors[] __initdata = { 32 INTC_IRQ(IRQ0, 64), INTC_IRQ(IRQ1, 65), 33 INTC_IRQ(IRQ2, 66), INTC_IRQ(IRQ3, 67), 34 INTC_IRQ(IRQ4, 80), INTC_IRQ(IRQ5, 81), 35 INTC_IRQ(IRQ6, 82), INTC_IRQ(IRQ7, 83), 36 INTC_IRQ(WDT, 84), INTC_IRQ(EDMAC, 85), 37 INTC_IRQ(CMT0, 86), INTC_IRQ(CMT1, 87), 38 INTC_IRQ(SCIF0, 88), INTC_IRQ(SCIF0, 89), 39 INTC_IRQ(SCIF0, 90), INTC_IRQ(SCIF0, 91), 40 INTC_IRQ(SCIF1, 92), INTC_IRQ(SCIF1, 93), 41 INTC_IRQ(SCIF1, 94), INTC_IRQ(SCIF1, 95), 42 INTC_IRQ(SCIF2, 96), INTC_IRQ(SCIF2, 97), 43 INTC_IRQ(SCIF2, 98), INTC_IRQ(SCIF2, 99), 44 INTC_IRQ(HIF_HIFI, 100), INTC_IRQ(HIF_HIFBI, 101), 45 INTC_IRQ(DMAC0, 104), INTC_IRQ(DMAC1, 105), 46 INTC_IRQ(DMAC2, 106), INTC_IRQ(DMAC3, 107), 47 INTC_IRQ(SIOF, 108), 48 }; 49 50 static struct intc_prio_reg prio_registers[] __initdata = { 51 { 0xf8140006, 0, 16, 4, /* IPRA */ { IRQ0, IRQ1, IRQ2, IRQ3 } }, 52 { 0xf8140008, 0, 16, 4, /* IPRB */ { IRQ4, IRQ5, IRQ6, IRQ7 } }, 53 { 0xf8080000, 0, 16, 4, /* IPRC */ { WDT, EDMAC, CMT0, CMT1 } }, 54 { 0xf8080002, 0, 16, 4, /* IPRD */ { SCIF0, SCIF1, SCIF2 } }, 55 { 0xf8080004, 0, 16, 4, /* IPRE */ { HIF_HIFI, HIF_HIFBI } }, 56 { 0xf8080006, 0, 16, 4, /* IPRF */ { DMAC0, DMAC1, DMAC2, DMAC3 } }, 57 { 0xf8080008, 0, 16, 4, /* IPRG */ { SIOF } }, 58 }; 59 60 static DECLARE_INTC_DESC(intc_desc, "sh7619", vectors, NULL, 61 NULL, prio_registers, NULL); 62 63 static struct plat_sci_port scif0_platform_data = { 64 .scscr = SCSCR_REIE, 65 .type = PORT_SCIF, 66 }; 67 68 static struct resource scif0_resources[] = { 69 DEFINE_RES_MEM(0xf8400000, 0x100), 70 DEFINE_RES_IRQ(88), 71 }; 72 73 static struct platform_device scif0_device = { 74 .name = "sh-sci", 75 .id = 0, 76 .resource = scif0_resources, 77 .num_resources = ARRAY_SIZE(scif0_resources), 78 .dev = { 79 .platform_data = &scif0_platform_data, 80 }, 81 }; 82 83 static struct plat_sci_port scif1_platform_data = { 84 .scscr = SCSCR_REIE, 85 .type = PORT_SCIF, 86 }; 87 88 static struct resource scif1_resources[] = { 89 DEFINE_RES_MEM(0xf8410000, 0x100), 90 DEFINE_RES_IRQ(92), 91 }; 92 93 static struct platform_device scif1_device = { 94 .name = "sh-sci", 95 .id = 1, 96 .resource = scif1_resources, 97 .num_resources = ARRAY_SIZE(scif1_resources), 98 .dev = { 99 .platform_data = &scif1_platform_data, 100 }, 101 }; 102 103 static struct plat_sci_port scif2_platform_data = { 104 .scscr = SCSCR_REIE, 105 .type = PORT_SCIF, 106 }; 107 108 static struct resource scif2_resources[] = { 109 DEFINE_RES_MEM(0xf8420000, 0x100), 110 DEFINE_RES_IRQ(96), 111 }; 112 113 static struct platform_device scif2_device = { 114 .name = "sh-sci", 115 .id = 2, 116 .resource = scif2_resources, 117 .num_resources = ARRAY_SIZE(scif2_resources), 118 .dev = { 119 .platform_data = &scif2_platform_data, 120 }, 121 }; 122 123 static struct sh_eth_plat_data eth_platform_data = { 124 .phy = 1, 125 .edmac_endian = EDMAC_LITTLE_ENDIAN, 126 .phy_interface = PHY_INTERFACE_MODE_MII, 127 }; 128 129 static struct resource eth_resources[] = { 130 [0] = { 131 .start = 0xfb000000, 132 .end = 0xfb0001c7, 133 .flags = IORESOURCE_MEM, 134 }, 135 [1] = { 136 .start = 85, 137 .end = 85, 138 .flags = IORESOURCE_IRQ, 139 }, 140 }; 141 142 static struct platform_device eth_device = { 143 .name = "sh7619-ether", 144 .id = -1, 145 .dev = { 146 .platform_data = ð_platform_data, 147 }, 148 .num_resources = ARRAY_SIZE(eth_resources), 149 .resource = eth_resources, 150 }; 151 152 static struct sh_timer_config cmt_platform_data = { 153 .channels_mask = 3, 154 }; 155 156 static struct resource cmt_resources[] = { 157 DEFINE_RES_MEM(0xf84a0070, 0x10), 158 DEFINE_RES_IRQ(86), 159 DEFINE_RES_IRQ(87), 160 }; 161 162 static struct platform_device cmt_device = { 163 .name = "sh-cmt-16", 164 .id = 0, 165 .dev = { 166 .platform_data = &cmt_platform_data, 167 }, 168 .resource = cmt_resources, 169 .num_resources = ARRAY_SIZE(cmt_resources), 170 }; 171 172 static struct platform_device *sh7619_devices[] __initdata = { 173 &scif0_device, 174 &scif1_device, 175 &scif2_device, 176 ð_device, 177 &cmt_device, 178 }; 179 180 static int __init sh7619_devices_setup(void) 181 { 182 return platform_add_devices(sh7619_devices, 183 ARRAY_SIZE(sh7619_devices)); 184 } 185 arch_initcall(sh7619_devices_setup); 186 187 void __init plat_irq_setup(void) 188 { 189 register_intc_controller(&intc_desc); 190 } 191 192 static struct platform_device *sh7619_early_devices[] __initdata = { 193 &scif0_device, 194 &scif1_device, 195 &scif2_device, 196 &cmt_device, 197 }; 198 199 #define STBCR3 0xf80a0000 200 201 void __init plat_early_device_setup(void) 202 { 203 /* enable CMT clock */ 204 __raw_writeb(__raw_readb(STBCR3) & ~0x10, STBCR3); 205 206 early_platform_add_devices(sh7619_early_devices, 207 ARRAY_SIZE(sh7619_early_devices)); 208 } 209