1 /* 2 * arch/sh/kernel/cpu/irq/ipr.c 3 * 4 * Copyright (C) 1999 Niibe Yutaka & Takeshi Yaegashi 5 * Copyright (C) 2000 Kazumoto Kojima 6 * Copyright (C) 2003 Takashi Kusuda <kusuda-takashi@hitachi-ul.co.jp> 7 * 8 * Interrupt handling for IPR-based IRQ. 9 * 10 * Supported system: 11 * On-chip supporting modules (TMU, RTC, etc.). 12 * On-chip supporting modules for SH7709/SH7709A/SH7729/SH7300. 13 * Hitachi SolutionEngine external I/O: 14 * MS7709SE01, MS7709ASE01, and MS7750SE01 15 * 16 */ 17 18 #include <linux/config.h> 19 #include <linux/init.h> 20 #include <linux/irq.h> 21 #include <linux/module.h> 22 23 #include <asm/system.h> 24 #include <asm/io.h> 25 #include <asm/machvec.h> 26 27 struct ipr_data { 28 unsigned int addr; /* Address of Interrupt Priority Register */ 29 int shift; /* Shifts of the 16-bit data */ 30 int priority; /* The priority */ 31 }; 32 static struct ipr_data ipr_data[NR_IRQS]; 33 34 static void enable_ipr_irq(unsigned int irq); 35 static void disable_ipr_irq(unsigned int irq); 36 37 /* shutdown is same as "disable" */ 38 #define shutdown_ipr_irq disable_ipr_irq 39 40 static void mask_and_ack_ipr(unsigned int); 41 static void end_ipr_irq(unsigned int irq); 42 43 static unsigned int startup_ipr_irq(unsigned int irq) 44 { 45 enable_ipr_irq(irq); 46 return 0; /* never anything pending */ 47 } 48 49 static struct hw_interrupt_type ipr_irq_type = { 50 .typename = "IPR-IRQ", 51 .startup = startup_ipr_irq, 52 .shutdown = shutdown_ipr_irq, 53 .enable = enable_ipr_irq, 54 .disable = disable_ipr_irq, 55 .ack = mask_and_ack_ipr, 56 .end = end_ipr_irq 57 }; 58 59 static void disable_ipr_irq(unsigned int irq) 60 { 61 unsigned long val, flags; 62 unsigned int addr = ipr_data[irq].addr; 63 unsigned short mask = 0xffff ^ (0x0f << ipr_data[irq].shift); 64 65 /* Set the priority in IPR to 0 */ 66 local_irq_save(flags); 67 val = ctrl_inw(addr); 68 val &= mask; 69 ctrl_outw(val, addr); 70 local_irq_restore(flags); 71 } 72 73 static void enable_ipr_irq(unsigned int irq) 74 { 75 unsigned long val, flags; 76 unsigned int addr = ipr_data[irq].addr; 77 int priority = ipr_data[irq].priority; 78 unsigned short value = (priority << ipr_data[irq].shift); 79 80 /* Set priority in IPR back to original value */ 81 local_irq_save(flags); 82 val = ctrl_inw(addr); 83 val |= value; 84 ctrl_outw(val, addr); 85 local_irq_restore(flags); 86 } 87 88 static void mask_and_ack_ipr(unsigned int irq) 89 { 90 disable_ipr_irq(irq); 91 92 #if defined(CONFIG_CPU_SUBTYPE_SH7707) || defined(CONFIG_CPU_SUBTYPE_SH7709) || \ 93 defined(CONFIG_CPU_SUBTYPE_SH7300) || defined(CONFIG_CPU_SUBTYPE_SH7705) 94 /* This is needed when we use edge triggered setting */ 95 /* XXX: Is it really needed? */ 96 if (IRQ0_IRQ <= irq && irq <= IRQ5_IRQ) { 97 /* Clear external interrupt request */ 98 int a = ctrl_inb(INTC_IRR0); 99 a &= ~(1 << (irq - IRQ0_IRQ)); 100 ctrl_outb(a, INTC_IRR0); 101 } 102 #endif 103 } 104 105 static void end_ipr_irq(unsigned int irq) 106 { 107 if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))) 108 enable_ipr_irq(irq); 109 } 110 111 void make_ipr_irq(unsigned int irq, unsigned int addr, int pos, int priority) 112 { 113 disable_irq_nosync(irq); 114 ipr_data[irq].addr = addr; 115 ipr_data[irq].shift = pos*4; /* POSition (0-3) x 4 means shift */ 116 ipr_data[irq].priority = priority; 117 118 irq_desc[irq].handler = &ipr_irq_type; 119 disable_ipr_irq(irq); 120 } 121 122 void __init init_IRQ(void) 123 { 124 #ifndef CONFIG_CPU_SUBTYPE_SH7780 125 make_ipr_irq(TIMER_IRQ, TIMER_IPR_ADDR, TIMER_IPR_POS, TIMER_PRIORITY); 126 make_ipr_irq(TIMER1_IRQ, TIMER1_IPR_ADDR, TIMER1_IPR_POS, TIMER1_PRIORITY); 127 #if defined(CONFIG_SH_RTC) 128 make_ipr_irq(RTC_IRQ, RTC_IPR_ADDR, RTC_IPR_POS, RTC_PRIORITY); 129 #endif 130 131 #ifdef SCI_ERI_IRQ 132 make_ipr_irq(SCI_ERI_IRQ, SCI_IPR_ADDR, SCI_IPR_POS, SCI_PRIORITY); 133 make_ipr_irq(SCI_RXI_IRQ, SCI_IPR_ADDR, SCI_IPR_POS, SCI_PRIORITY); 134 make_ipr_irq(SCI_TXI_IRQ, SCI_IPR_ADDR, SCI_IPR_POS, SCI_PRIORITY); 135 #endif 136 137 #ifdef SCIF1_ERI_IRQ 138 make_ipr_irq(SCIF1_ERI_IRQ, SCIF1_IPR_ADDR, SCIF1_IPR_POS, SCIF1_PRIORITY); 139 make_ipr_irq(SCIF1_RXI_IRQ, SCIF1_IPR_ADDR, SCIF1_IPR_POS, SCIF1_PRIORITY); 140 make_ipr_irq(SCIF1_BRI_IRQ, SCIF1_IPR_ADDR, SCIF1_IPR_POS, SCIF1_PRIORITY); 141 make_ipr_irq(SCIF1_TXI_IRQ, SCIF1_IPR_ADDR, SCIF1_IPR_POS, SCIF1_PRIORITY); 142 #endif 143 144 #if defined(CONFIG_CPU_SUBTYPE_SH7300) 145 make_ipr_irq(SCIF0_IRQ, SCIF0_IPR_ADDR, SCIF0_IPR_POS, SCIF0_PRIORITY); 146 make_ipr_irq(DMTE2_IRQ, DMA1_IPR_ADDR, DMA1_IPR_POS, DMA1_PRIORITY); 147 make_ipr_irq(DMTE3_IRQ, DMA1_IPR_ADDR, DMA1_IPR_POS, DMA1_PRIORITY); 148 make_ipr_irq(VIO_IRQ, VIO_IPR_ADDR, VIO_IPR_POS, VIO_PRIORITY); 149 #endif 150 151 #ifdef SCIF_ERI_IRQ 152 make_ipr_irq(SCIF_ERI_IRQ, SCIF_IPR_ADDR, SCIF_IPR_POS, SCIF_PRIORITY); 153 make_ipr_irq(SCIF_RXI_IRQ, SCIF_IPR_ADDR, SCIF_IPR_POS, SCIF_PRIORITY); 154 make_ipr_irq(SCIF_BRI_IRQ, SCIF_IPR_ADDR, SCIF_IPR_POS, SCIF_PRIORITY); 155 make_ipr_irq(SCIF_TXI_IRQ, SCIF_IPR_ADDR, SCIF_IPR_POS, SCIF_PRIORITY); 156 #endif 157 158 #ifdef IRDA_ERI_IRQ 159 make_ipr_irq(IRDA_ERI_IRQ, IRDA_IPR_ADDR, IRDA_IPR_POS, IRDA_PRIORITY); 160 make_ipr_irq(IRDA_RXI_IRQ, IRDA_IPR_ADDR, IRDA_IPR_POS, IRDA_PRIORITY); 161 make_ipr_irq(IRDA_BRI_IRQ, IRDA_IPR_ADDR, IRDA_IPR_POS, IRDA_PRIORITY); 162 make_ipr_irq(IRDA_TXI_IRQ, IRDA_IPR_ADDR, IRDA_IPR_POS, IRDA_PRIORITY); 163 #endif 164 165 #if defined(CONFIG_CPU_SUBTYPE_SH7707) || defined(CONFIG_CPU_SUBTYPE_SH7709) || \ 166 defined(CONFIG_CPU_SUBTYPE_SH7300) || defined(CONFIG_CPU_SUBTYPE_SH7705) 167 /* 168 * Initialize the Interrupt Controller (INTC) 169 * registers to their power on values 170 */ 171 172 /* 173 * Enable external irq (INTC IRQ mode). 174 * You should set corresponding bits of PFC to "00" 175 * to enable these interrupts. 176 */ 177 make_ipr_irq(IRQ0_IRQ, IRQ0_IPR_ADDR, IRQ0_IPR_POS, IRQ0_PRIORITY); 178 make_ipr_irq(IRQ1_IRQ, IRQ1_IPR_ADDR, IRQ1_IPR_POS, IRQ1_PRIORITY); 179 make_ipr_irq(IRQ2_IRQ, IRQ2_IPR_ADDR, IRQ2_IPR_POS, IRQ2_PRIORITY); 180 make_ipr_irq(IRQ3_IRQ, IRQ3_IPR_ADDR, IRQ3_IPR_POS, IRQ3_PRIORITY); 181 make_ipr_irq(IRQ4_IRQ, IRQ4_IPR_ADDR, IRQ4_IPR_POS, IRQ4_PRIORITY); 182 make_ipr_irq(IRQ5_IRQ, IRQ5_IPR_ADDR, IRQ5_IPR_POS, IRQ5_PRIORITY); 183 #endif 184 #endif 185 186 #ifdef CONFIG_CPU_HAS_PINT_IRQ 187 init_IRQ_pint(); 188 #endif 189 190 #ifdef CONFIG_CPU_HAS_INTC2_IRQ 191 init_IRQ_intc2(); 192 #endif 193 /* Perform the machine specific initialisation */ 194 if (sh_mv.mv_init_irq != NULL) 195 sh_mv.mv_init_irq(); 196 } 197 198 #if !defined(CONFIG_CPU_HAS_PINT_IRQ) 199 int ipr_irq_demux(int irq) 200 { 201 return irq; 202 } 203 #endif 204 205 EXPORT_SYMBOL(make_ipr_irq); 206