1 /* 2 * arch/sh/kernel/cpu/init.c 3 * 4 * CPU init code 5 * 6 * Copyright (C) 2002 - 2006 Paul Mundt 7 * Copyright (C) 2003 Richard Curnow 8 * 9 * This file is subject to the terms and conditions of the GNU General Public 10 * License. See the file "COPYING" in the main directory of this archive 11 * for more details. 12 */ 13 #include <linux/init.h> 14 #include <linux/kernel.h> 15 #include <linux/mm.h> 16 #include <asm/mmu_context.h> 17 #include <asm/processor.h> 18 #include <asm/uaccess.h> 19 #include <asm/page.h> 20 #include <asm/system.h> 21 #include <asm/cacheflush.h> 22 #include <asm/cache.h> 23 #include <asm/io.h> 24 25 extern void detect_cpu_and_cache_system(void); 26 27 /* 28 * Generic wrapper for command line arguments to disable on-chip 29 * peripherals (nofpu, nodsp, and so forth). 30 */ 31 #define onchip_setup(x) \ 32 static int x##_disabled __initdata = 0; \ 33 \ 34 static int __init x##_setup(char *opts) \ 35 { \ 36 x##_disabled = 1; \ 37 return 1; \ 38 } \ 39 __setup("no" __stringify(x), x##_setup); 40 41 onchip_setup(fpu); 42 onchip_setup(dsp); 43 44 /* 45 * Generic first-level cache init 46 */ 47 static void __init cache_init(void) 48 { 49 unsigned long ccr, flags; 50 51 if (current_cpu_data.type == CPU_SH_NONE) 52 panic("Unknown CPU"); 53 54 jump_to_P2(); 55 ccr = ctrl_inl(CCR); 56 57 /* 58 * At this point we don't know whether the cache is enabled or not - a 59 * bootloader may have enabled it. There are at least 2 things that 60 * could be dirty in the cache at this point: 61 * 1. kernel command line set up by boot loader 62 * 2. spilled registers from the prolog of this function 63 * => before re-initialising the cache, we must do a purge of the whole 64 * cache out to memory for safety. As long as nothing is spilled 65 * during the loop to lines that have already been done, this is safe. 66 * - RPC 67 */ 68 if (ccr & CCR_CACHE_ENABLE) { 69 unsigned long ways, waysize, addrstart; 70 71 waysize = current_cpu_data.dcache.sets; 72 73 #ifdef CCR_CACHE_ORA 74 /* 75 * If the OC is already in RAM mode, we only have 76 * half of the entries to flush.. 77 */ 78 if (ccr & CCR_CACHE_ORA) 79 waysize >>= 1; 80 #endif 81 82 waysize <<= current_cpu_data.dcache.entry_shift; 83 84 #ifdef CCR_CACHE_EMODE 85 /* If EMODE is not set, we only have 1 way to flush. */ 86 if (!(ccr & CCR_CACHE_EMODE)) 87 ways = 1; 88 else 89 #endif 90 ways = current_cpu_data.dcache.ways; 91 92 addrstart = CACHE_OC_ADDRESS_ARRAY; 93 do { 94 unsigned long addr; 95 96 for (addr = addrstart; 97 addr < addrstart + waysize; 98 addr += current_cpu_data.dcache.linesz) 99 ctrl_outl(0, addr); 100 101 addrstart += current_cpu_data.dcache.way_incr; 102 } while (--ways); 103 } 104 105 /* 106 * Default CCR values .. enable the caches 107 * and invalidate them immediately.. 108 */ 109 flags = CCR_CACHE_ENABLE | CCR_CACHE_INVALIDATE; 110 111 #ifdef CCR_CACHE_EMODE 112 /* Force EMODE if possible */ 113 if (current_cpu_data.dcache.ways > 1) 114 flags |= CCR_CACHE_EMODE; 115 else 116 flags &= ~CCR_CACHE_EMODE; 117 #endif 118 119 #ifdef CONFIG_SH_WRITETHROUGH 120 /* Turn on Write-through caching */ 121 flags |= CCR_CACHE_WT; 122 #else 123 /* .. or default to Write-back */ 124 flags |= CCR_CACHE_CB; 125 #endif 126 127 #ifdef CONFIG_SH_OCRAM 128 /* Turn on OCRAM -- halve the OC */ 129 flags |= CCR_CACHE_ORA; 130 current_cpu_data.dcache.sets >>= 1; 131 132 current_cpu_data.dcache.way_size = current_cpu_data.dcache.sets * 133 current_cpu_data.dcache.linesz; 134 #endif 135 136 ctrl_outl(flags, CCR); 137 back_to_P1(); 138 } 139 140 #ifdef CONFIG_SH_DSP 141 static void __init release_dsp(void) 142 { 143 unsigned long sr; 144 145 /* Clear SR.DSP bit */ 146 __asm__ __volatile__ ( 147 "stc\tsr, %0\n\t" 148 "and\t%1, %0\n\t" 149 "ldc\t%0, sr\n\t" 150 : "=&r" (sr) 151 : "r" (~SR_DSP) 152 ); 153 } 154 155 static void __init dsp_init(void) 156 { 157 unsigned long sr; 158 159 /* 160 * Set the SR.DSP bit, wait for one instruction, and then read 161 * back the SR value. 162 */ 163 __asm__ __volatile__ ( 164 "stc\tsr, %0\n\t" 165 "or\t%1, %0\n\t" 166 "ldc\t%0, sr\n\t" 167 "nop\n\t" 168 "stc\tsr, %0\n\t" 169 : "=&r" (sr) 170 : "r" (SR_DSP) 171 ); 172 173 /* If the DSP bit is still set, this CPU has a DSP */ 174 if (sr & SR_DSP) 175 current_cpu_data.flags |= CPU_HAS_DSP; 176 177 /* Now that we've determined the DSP status, clear the DSP bit. */ 178 release_dsp(); 179 } 180 #endif /* CONFIG_SH_DSP */ 181 182 /** 183 * sh_cpu_init 184 * 185 * This is our initial entry point for each CPU, and is invoked on the boot 186 * CPU prior to calling start_kernel(). For SMP, a combination of this and 187 * start_secondary() will bring up each processor to a ready state prior 188 * to hand forking the idle loop. 189 * 190 * We do all of the basic processor init here, including setting up the 191 * caches, FPU, DSP, kicking the UBC, etc. By the time start_kernel() is 192 * hit (and subsequently platform_setup()) things like determining the 193 * CPU subtype and initial configuration will all be done. 194 * 195 * Each processor family is still responsible for doing its own probing 196 * and cache configuration in detect_cpu_and_cache_system(). 197 */ 198 asmlinkage void __init sh_cpu_init(void) 199 { 200 /* First, probe the CPU */ 201 detect_cpu_and_cache_system(); 202 203 /* Init the cache */ 204 cache_init(); 205 206 shm_align_mask = max_t(unsigned long, 207 current_cpu_data.dcache.way_size - 1, 208 PAGE_SIZE - 1); 209 210 /* Disable the FPU */ 211 if (fpu_disabled) { 212 printk("FPU Disabled\n"); 213 current_cpu_data.flags &= ~CPU_HAS_FPU; 214 disable_fpu(); 215 } 216 217 /* FPU initialization */ 218 if ((current_cpu_data.flags & CPU_HAS_FPU)) { 219 clear_thread_flag(TIF_USEDFPU); 220 clear_used_math(); 221 } 222 223 /* 224 * Initialize the per-CPU ASID cache very early, since the 225 * TLB flushing routines depend on this being setup. 226 */ 227 current_cpu_data.asid_cache = NO_CONTEXT; 228 229 #ifdef CONFIG_SH_DSP 230 /* Probe for DSP */ 231 dsp_init(); 232 233 /* Disable the DSP */ 234 if (dsp_disabled) { 235 printk("DSP Disabled\n"); 236 current_cpu_data.flags &= ~CPU_HAS_DSP; 237 release_dsp(); 238 } 239 #endif 240 241 #ifdef CONFIG_UBC_WAKEUP 242 /* 243 * Some brain-damaged loaders decided it would be a good idea to put 244 * the UBC to sleep. This causes some issues when it comes to things 245 * like PTRACE_SINGLESTEP or doing hardware watchpoints in GDB. So .. 246 * we wake it up and hope that all is well. 247 */ 248 ubc_wakeup(); 249 #endif 250 } 251