1 /* 2 * arch/sh/kernel/cpu/init.c 3 * 4 * CPU init code 5 * 6 * Copyright (C) 2002 - 2007 Paul Mundt 7 * Copyright (C) 2003 Richard Curnow 8 * 9 * This file is subject to the terms and conditions of the GNU General Public 10 * License. See the file "COPYING" in the main directory of this archive 11 * for more details. 12 */ 13 #include <linux/init.h> 14 #include <linux/kernel.h> 15 #include <linux/mm.h> 16 #include <asm/mmu_context.h> 17 #include <asm/processor.h> 18 #include <asm/uaccess.h> 19 #include <asm/page.h> 20 #include <asm/system.h> 21 #include <asm/cacheflush.h> 22 #include <asm/cache.h> 23 #include <asm/io.h> 24 25 extern void detect_cpu_and_cache_system(void); 26 27 /* 28 * Generic wrapper for command line arguments to disable on-chip 29 * peripherals (nofpu, nodsp, and so forth). 30 */ 31 #define onchip_setup(x) \ 32 static int x##_disabled __initdata = 0; \ 33 \ 34 static int __init x##_setup(char *opts) \ 35 { \ 36 x##_disabled = 1; \ 37 return 1; \ 38 } \ 39 __setup("no" __stringify(x), x##_setup); 40 41 onchip_setup(fpu); 42 onchip_setup(dsp); 43 44 /* 45 * Generic first-level cache init 46 */ 47 static void __init cache_init(void) 48 { 49 unsigned long ccr, flags; 50 51 /* First setup the rest of the I-cache info */ 52 current_cpu_data.icache.entry_mask = current_cpu_data.icache.way_incr - 53 current_cpu_data.icache.linesz; 54 55 current_cpu_data.icache.way_size = current_cpu_data.icache.sets * 56 current_cpu_data.icache.linesz; 57 58 /* And the D-cache too */ 59 current_cpu_data.dcache.entry_mask = current_cpu_data.dcache.way_incr - 60 current_cpu_data.dcache.linesz; 61 62 current_cpu_data.dcache.way_size = current_cpu_data.dcache.sets * 63 current_cpu_data.dcache.linesz; 64 65 jump_to_P2(); 66 ccr = ctrl_inl(CCR); 67 68 /* 69 * At this point we don't know whether the cache is enabled or not - a 70 * bootloader may have enabled it. There are at least 2 things that 71 * could be dirty in the cache at this point: 72 * 1. kernel command line set up by boot loader 73 * 2. spilled registers from the prolog of this function 74 * => before re-initialising the cache, we must do a purge of the whole 75 * cache out to memory for safety. As long as nothing is spilled 76 * during the loop to lines that have already been done, this is safe. 77 * - RPC 78 */ 79 if (ccr & CCR_CACHE_ENABLE) { 80 unsigned long ways, waysize, addrstart; 81 82 waysize = current_cpu_data.dcache.sets; 83 84 #ifdef CCR_CACHE_ORA 85 /* 86 * If the OC is already in RAM mode, we only have 87 * half of the entries to flush.. 88 */ 89 if (ccr & CCR_CACHE_ORA) 90 waysize >>= 1; 91 #endif 92 93 waysize <<= current_cpu_data.dcache.entry_shift; 94 95 #ifdef CCR_CACHE_EMODE 96 /* If EMODE is not set, we only have 1 way to flush. */ 97 if (!(ccr & CCR_CACHE_EMODE)) 98 ways = 1; 99 else 100 #endif 101 ways = current_cpu_data.dcache.ways; 102 103 addrstart = CACHE_OC_ADDRESS_ARRAY; 104 do { 105 unsigned long addr; 106 107 for (addr = addrstart; 108 addr < addrstart + waysize; 109 addr += current_cpu_data.dcache.linesz) 110 ctrl_outl(0, addr); 111 112 addrstart += current_cpu_data.dcache.way_incr; 113 } while (--ways); 114 } 115 116 /* 117 * Default CCR values .. enable the caches 118 * and invalidate them immediately.. 119 */ 120 flags = CCR_CACHE_ENABLE | CCR_CACHE_INVALIDATE; 121 122 #ifdef CCR_CACHE_EMODE 123 /* Force EMODE if possible */ 124 if (current_cpu_data.dcache.ways > 1) 125 flags |= CCR_CACHE_EMODE; 126 else 127 flags &= ~CCR_CACHE_EMODE; 128 #endif 129 130 #ifdef CONFIG_SH_WRITETHROUGH 131 /* Turn on Write-through caching */ 132 flags |= CCR_CACHE_WT; 133 #else 134 /* .. or default to Write-back */ 135 flags |= CCR_CACHE_CB; 136 #endif 137 138 #ifdef CONFIG_SH_OCRAM 139 /* Turn on OCRAM -- halve the OC */ 140 flags |= CCR_CACHE_ORA; 141 current_cpu_data.dcache.sets >>= 1; 142 143 current_cpu_data.dcache.way_size = current_cpu_data.dcache.sets * 144 current_cpu_data.dcache.linesz; 145 #endif 146 147 ctrl_outl(flags, CCR); 148 back_to_P1(); 149 } 150 151 #ifdef CONFIG_SH_DSP 152 static void __init release_dsp(void) 153 { 154 unsigned long sr; 155 156 /* Clear SR.DSP bit */ 157 __asm__ __volatile__ ( 158 "stc\tsr, %0\n\t" 159 "and\t%1, %0\n\t" 160 "ldc\t%0, sr\n\t" 161 : "=&r" (sr) 162 : "r" (~SR_DSP) 163 ); 164 } 165 166 static void __init dsp_init(void) 167 { 168 unsigned long sr; 169 170 /* 171 * Set the SR.DSP bit, wait for one instruction, and then read 172 * back the SR value. 173 */ 174 __asm__ __volatile__ ( 175 "stc\tsr, %0\n\t" 176 "or\t%1, %0\n\t" 177 "ldc\t%0, sr\n\t" 178 "nop\n\t" 179 "stc\tsr, %0\n\t" 180 : "=&r" (sr) 181 : "r" (SR_DSP) 182 ); 183 184 /* If the DSP bit is still set, this CPU has a DSP */ 185 if (sr & SR_DSP) 186 current_cpu_data.flags |= CPU_HAS_DSP; 187 188 /* Now that we've determined the DSP status, clear the DSP bit. */ 189 release_dsp(); 190 } 191 #endif /* CONFIG_SH_DSP */ 192 193 /** 194 * sh_cpu_init 195 * 196 * This is our initial entry point for each CPU, and is invoked on the boot 197 * CPU prior to calling start_kernel(). For SMP, a combination of this and 198 * start_secondary() will bring up each processor to a ready state prior 199 * to hand forking the idle loop. 200 * 201 * We do all of the basic processor init here, including setting up the 202 * caches, FPU, DSP, kicking the UBC, etc. By the time start_kernel() is 203 * hit (and subsequently platform_setup()) things like determining the 204 * CPU subtype and initial configuration will all be done. 205 * 206 * Each processor family is still responsible for doing its own probing 207 * and cache configuration in detect_cpu_and_cache_system(). 208 */ 209 asmlinkage void __init sh_cpu_init(void) 210 { 211 /* First, probe the CPU */ 212 detect_cpu_and_cache_system(); 213 214 if (current_cpu_data.type == CPU_SH_NONE) 215 panic("Unknown CPU"); 216 217 /* Init the cache */ 218 cache_init(); 219 220 shm_align_mask = max_t(unsigned long, 221 current_cpu_data.dcache.way_size - 1, 222 PAGE_SIZE - 1); 223 224 /* Disable the FPU */ 225 if (fpu_disabled) { 226 printk("FPU Disabled\n"); 227 current_cpu_data.flags &= ~CPU_HAS_FPU; 228 disable_fpu(); 229 } 230 231 /* FPU initialization */ 232 if ((current_cpu_data.flags & CPU_HAS_FPU)) { 233 clear_thread_flag(TIF_USEDFPU); 234 clear_used_math(); 235 } 236 237 /* 238 * Initialize the per-CPU ASID cache very early, since the 239 * TLB flushing routines depend on this being setup. 240 */ 241 current_cpu_data.asid_cache = NO_CONTEXT; 242 243 #ifdef CONFIG_SH_DSP 244 /* Probe for DSP */ 245 dsp_init(); 246 247 /* Disable the DSP */ 248 if (dsp_disabled) { 249 printk("DSP Disabled\n"); 250 current_cpu_data.flags &= ~CPU_HAS_DSP; 251 release_dsp(); 252 } 253 #endif 254 255 #ifdef CONFIG_UBC_WAKEUP 256 /* 257 * Some brain-damaged loaders decided it would be a good idea to put 258 * the UBC to sleep. This causes some issues when it comes to things 259 * like PTRACE_SINGLESTEP or doing hardware watchpoints in GDB. So .. 260 * we wake it up and hope that all is well. 261 */ 262 ubc_wakeup(); 263 #endif 264 } 265