1 /* 2 * arch/sh/kernel/cpu/init.c 3 * 4 * CPU init code 5 * 6 * Copyright (C) 2002 - 2007 Paul Mundt 7 * Copyright (C) 2003 Richard Curnow 8 * 9 * This file is subject to the terms and conditions of the GNU General Public 10 * License. See the file "COPYING" in the main directory of this archive 11 * for more details. 12 */ 13 #include <linux/init.h> 14 #include <linux/kernel.h> 15 #include <linux/mm.h> 16 #include <asm/mmu_context.h> 17 #include <asm/processor.h> 18 #include <asm/uaccess.h> 19 #include <asm/page.h> 20 #include <asm/system.h> 21 #include <asm/cacheflush.h> 22 #include <asm/cache.h> 23 #include <asm/io.h> 24 25 extern void detect_cpu_and_cache_system(void); 26 27 /* 28 * Generic wrapper for command line arguments to disable on-chip 29 * peripherals (nofpu, nodsp, and so forth). 30 */ 31 #define onchip_setup(x) \ 32 static int x##_disabled __initdata = 0; \ 33 \ 34 static int __init x##_setup(char *opts) \ 35 { \ 36 x##_disabled = 1; \ 37 return 1; \ 38 } \ 39 __setup("no" __stringify(x), x##_setup); 40 41 onchip_setup(fpu); 42 onchip_setup(dsp); 43 44 #ifdef CONFIG_SPECULATIVE_EXECUTION 45 #define CPUOPM 0xff2f0000 46 #define CPUOPM_RABD (1 << 5) 47 48 static void __init speculative_execution_init(void) 49 { 50 /* Clear RABD */ 51 ctrl_outl(ctrl_inl(CPUOPM) & ~CPUOPM_RABD, CPUOPM); 52 53 /* Flush the update */ 54 (void)ctrl_inl(CPUOPM); 55 ctrl_barrier(); 56 } 57 #else 58 #define speculative_execution_init() do { } while (0) 59 #endif 60 61 /* 62 * Generic first-level cache init 63 */ 64 static void __init cache_init(void) 65 { 66 unsigned long ccr, flags; 67 68 /* First setup the rest of the I-cache info */ 69 current_cpu_data.icache.entry_mask = current_cpu_data.icache.way_incr - 70 current_cpu_data.icache.linesz; 71 72 current_cpu_data.icache.way_size = current_cpu_data.icache.sets * 73 current_cpu_data.icache.linesz; 74 75 /* And the D-cache too */ 76 current_cpu_data.dcache.entry_mask = current_cpu_data.dcache.way_incr - 77 current_cpu_data.dcache.linesz; 78 79 current_cpu_data.dcache.way_size = current_cpu_data.dcache.sets * 80 current_cpu_data.dcache.linesz; 81 82 jump_to_P2(); 83 ccr = ctrl_inl(CCR); 84 85 /* 86 * At this point we don't know whether the cache is enabled or not - a 87 * bootloader may have enabled it. There are at least 2 things that 88 * could be dirty in the cache at this point: 89 * 1. kernel command line set up by boot loader 90 * 2. spilled registers from the prolog of this function 91 * => before re-initialising the cache, we must do a purge of the whole 92 * cache out to memory for safety. As long as nothing is spilled 93 * during the loop to lines that have already been done, this is safe. 94 * - RPC 95 */ 96 if (ccr & CCR_CACHE_ENABLE) { 97 unsigned long ways, waysize, addrstart; 98 99 waysize = current_cpu_data.dcache.sets; 100 101 #ifdef CCR_CACHE_ORA 102 /* 103 * If the OC is already in RAM mode, we only have 104 * half of the entries to flush.. 105 */ 106 if (ccr & CCR_CACHE_ORA) 107 waysize >>= 1; 108 #endif 109 110 waysize <<= current_cpu_data.dcache.entry_shift; 111 112 #ifdef CCR_CACHE_EMODE 113 /* If EMODE is not set, we only have 1 way to flush. */ 114 if (!(ccr & CCR_CACHE_EMODE)) 115 ways = 1; 116 else 117 #endif 118 ways = current_cpu_data.dcache.ways; 119 120 addrstart = CACHE_OC_ADDRESS_ARRAY; 121 do { 122 unsigned long addr; 123 124 for (addr = addrstart; 125 addr < addrstart + waysize; 126 addr += current_cpu_data.dcache.linesz) 127 ctrl_outl(0, addr); 128 129 addrstart += current_cpu_data.dcache.way_incr; 130 } while (--ways); 131 } 132 133 /* 134 * Default CCR values .. enable the caches 135 * and invalidate them immediately.. 136 */ 137 flags = CCR_CACHE_ENABLE | CCR_CACHE_INVALIDATE; 138 139 #ifdef CCR_CACHE_EMODE 140 /* Force EMODE if possible */ 141 if (current_cpu_data.dcache.ways > 1) 142 flags |= CCR_CACHE_EMODE; 143 else 144 flags &= ~CCR_CACHE_EMODE; 145 #endif 146 147 #ifdef CONFIG_SH_WRITETHROUGH 148 /* Turn on Write-through caching */ 149 flags |= CCR_CACHE_WT; 150 #else 151 /* .. or default to Write-back */ 152 flags |= CCR_CACHE_CB; 153 #endif 154 155 #ifdef CONFIG_SH_OCRAM 156 /* Turn on OCRAM -- halve the OC */ 157 flags |= CCR_CACHE_ORA; 158 current_cpu_data.dcache.sets >>= 1; 159 160 current_cpu_data.dcache.way_size = current_cpu_data.dcache.sets * 161 current_cpu_data.dcache.linesz; 162 #endif 163 164 ctrl_outl(flags, CCR); 165 back_to_P1(); 166 } 167 168 #ifdef CONFIG_SH_DSP 169 static void __init release_dsp(void) 170 { 171 unsigned long sr; 172 173 /* Clear SR.DSP bit */ 174 __asm__ __volatile__ ( 175 "stc\tsr, %0\n\t" 176 "and\t%1, %0\n\t" 177 "ldc\t%0, sr\n\t" 178 : "=&r" (sr) 179 : "r" (~SR_DSP) 180 ); 181 } 182 183 static void __init dsp_init(void) 184 { 185 unsigned long sr; 186 187 /* 188 * Set the SR.DSP bit, wait for one instruction, and then read 189 * back the SR value. 190 */ 191 __asm__ __volatile__ ( 192 "stc\tsr, %0\n\t" 193 "or\t%1, %0\n\t" 194 "ldc\t%0, sr\n\t" 195 "nop\n\t" 196 "stc\tsr, %0\n\t" 197 : "=&r" (sr) 198 : "r" (SR_DSP) 199 ); 200 201 /* If the DSP bit is still set, this CPU has a DSP */ 202 if (sr & SR_DSP) 203 current_cpu_data.flags |= CPU_HAS_DSP; 204 205 /* Now that we've determined the DSP status, clear the DSP bit. */ 206 release_dsp(); 207 } 208 #endif /* CONFIG_SH_DSP */ 209 210 /** 211 * sh_cpu_init 212 * 213 * This is our initial entry point for each CPU, and is invoked on the boot 214 * CPU prior to calling start_kernel(). For SMP, a combination of this and 215 * start_secondary() will bring up each processor to a ready state prior 216 * to hand forking the idle loop. 217 * 218 * We do all of the basic processor init here, including setting up the 219 * caches, FPU, DSP, kicking the UBC, etc. By the time start_kernel() is 220 * hit (and subsequently platform_setup()) things like determining the 221 * CPU subtype and initial configuration will all be done. 222 * 223 * Each processor family is still responsible for doing its own probing 224 * and cache configuration in detect_cpu_and_cache_system(). 225 */ 226 asmlinkage void __init sh_cpu_init(void) 227 { 228 /* First, probe the CPU */ 229 detect_cpu_and_cache_system(); 230 231 if (current_cpu_data.type == CPU_SH_NONE) 232 panic("Unknown CPU"); 233 234 /* Init the cache */ 235 cache_init(); 236 237 shm_align_mask = max_t(unsigned long, 238 current_cpu_data.dcache.way_size - 1, 239 PAGE_SIZE - 1); 240 241 /* Disable the FPU */ 242 if (fpu_disabled) { 243 printk("FPU Disabled\n"); 244 current_cpu_data.flags &= ~CPU_HAS_FPU; 245 disable_fpu(); 246 } 247 248 /* FPU initialization */ 249 if ((current_cpu_data.flags & CPU_HAS_FPU)) { 250 clear_thread_flag(TIF_USEDFPU); 251 clear_used_math(); 252 } 253 254 /* 255 * Initialize the per-CPU ASID cache very early, since the 256 * TLB flushing routines depend on this being setup. 257 */ 258 current_cpu_data.asid_cache = NO_CONTEXT; 259 260 #ifdef CONFIG_SH_DSP 261 /* Probe for DSP */ 262 dsp_init(); 263 264 /* Disable the DSP */ 265 if (dsp_disabled) { 266 printk("DSP Disabled\n"); 267 current_cpu_data.flags &= ~CPU_HAS_DSP; 268 release_dsp(); 269 } 270 #endif 271 272 #ifdef CONFIG_UBC_WAKEUP 273 /* 274 * Some brain-damaged loaders decided it would be a good idea to put 275 * the UBC to sleep. This causes some issues when it comes to things 276 * like PTRACE_SINGLESTEP or doing hardware watchpoints in GDB. So .. 277 * we wake it up and hope that all is well. 278 */ 279 ubc_wakeup(); 280 #endif 281 282 speculative_execution_init(); 283 } 284