1 /* 2 * arch/sh/kernel/cpu/init.c 3 * 4 * CPU init code 5 * 6 * Copyright (C) 2002 - 2009 Paul Mundt 7 * Copyright (C) 2003 Richard Curnow 8 * 9 * This file is subject to the terms and conditions of the GNU General Public 10 * License. See the file "COPYING" in the main directory of this archive 11 * for more details. 12 */ 13 #include <linux/init.h> 14 #include <linux/kernel.h> 15 #include <linux/mm.h> 16 #include <linux/log2.h> 17 #include <asm/mmu_context.h> 18 #include <asm/processor.h> 19 #include <asm/uaccess.h> 20 #include <asm/page.h> 21 #include <asm/system.h> 22 #include <asm/cacheflush.h> 23 #include <asm/cache.h> 24 #include <asm/elf.h> 25 #include <asm/io.h> 26 #include <asm/smp.h> 27 28 /* 29 * Generic wrapper for command line arguments to disable on-chip 30 * peripherals (nofpu, nodsp, and so forth). 31 */ 32 #define onchip_setup(x) \ 33 static int x##_disabled __initdata = 0; \ 34 \ 35 static int __init x##_setup(char *opts) \ 36 { \ 37 x##_disabled = 1; \ 38 return 1; \ 39 } \ 40 __setup("no" __stringify(x), x##_setup); 41 42 onchip_setup(fpu); 43 onchip_setup(dsp); 44 45 #ifdef CONFIG_SPECULATIVE_EXECUTION 46 #define CPUOPM 0xff2f0000 47 #define CPUOPM_RABD (1 << 5) 48 49 static void __init speculative_execution_init(void) 50 { 51 /* Clear RABD */ 52 ctrl_outl(ctrl_inl(CPUOPM) & ~CPUOPM_RABD, CPUOPM); 53 54 /* Flush the update */ 55 (void)ctrl_inl(CPUOPM); 56 ctrl_barrier(); 57 } 58 #else 59 #define speculative_execution_init() do { } while (0) 60 #endif 61 62 #ifdef CONFIG_CPU_SH4A 63 #define EXPMASK 0xff2f0004 64 #define EXPMASK_RTEDS (1 << 0) 65 #define EXPMASK_BRDSSLP (1 << 1) 66 #define EXPMASK_MMCAW (1 << 4) 67 68 static void __init expmask_init(void) 69 { 70 unsigned long expmask = __raw_readl(EXPMASK); 71 72 /* 73 * Future proofing. 74 * 75 * Disable support for slottable sleep instruction, non-nop 76 * instructions in the rte delay slot, and associative writes to 77 * the memory-mapped cache array. 78 */ 79 expmask &= ~(EXPMASK_RTEDS | EXPMASK_BRDSSLP | EXPMASK_MMCAW); 80 81 __raw_writel(expmask, EXPMASK); 82 ctrl_barrier(); 83 } 84 #else 85 #define expmask_init() do { } while (0) 86 #endif 87 88 /* 2nd-level cache init */ 89 void __uses_jump_to_uncached __attribute__ ((weak)) l2_cache_init(void) 90 { 91 } 92 93 /* 94 * Generic first-level cache init 95 */ 96 #ifdef CONFIG_SUPERH32 97 static void __uses_jump_to_uncached cache_init(void) 98 { 99 unsigned long ccr, flags; 100 101 jump_to_uncached(); 102 ccr = ctrl_inl(CCR); 103 104 /* 105 * At this point we don't know whether the cache is enabled or not - a 106 * bootloader may have enabled it. There are at least 2 things that 107 * could be dirty in the cache at this point: 108 * 1. kernel command line set up by boot loader 109 * 2. spilled registers from the prolog of this function 110 * => before re-initialising the cache, we must do a purge of the whole 111 * cache out to memory for safety. As long as nothing is spilled 112 * during the loop to lines that have already been done, this is safe. 113 * - RPC 114 */ 115 if (ccr & CCR_CACHE_ENABLE) { 116 unsigned long ways, waysize, addrstart; 117 118 waysize = current_cpu_data.dcache.sets; 119 120 #ifdef CCR_CACHE_ORA 121 /* 122 * If the OC is already in RAM mode, we only have 123 * half of the entries to flush.. 124 */ 125 if (ccr & CCR_CACHE_ORA) 126 waysize >>= 1; 127 #endif 128 129 waysize <<= current_cpu_data.dcache.entry_shift; 130 131 #ifdef CCR_CACHE_EMODE 132 /* If EMODE is not set, we only have 1 way to flush. */ 133 if (!(ccr & CCR_CACHE_EMODE)) 134 ways = 1; 135 else 136 #endif 137 ways = current_cpu_data.dcache.ways; 138 139 addrstart = CACHE_OC_ADDRESS_ARRAY; 140 do { 141 unsigned long addr; 142 143 for (addr = addrstart; 144 addr < addrstart + waysize; 145 addr += current_cpu_data.dcache.linesz) 146 ctrl_outl(0, addr); 147 148 addrstart += current_cpu_data.dcache.way_incr; 149 } while (--ways); 150 } 151 152 /* 153 * Default CCR values .. enable the caches 154 * and invalidate them immediately.. 155 */ 156 flags = CCR_CACHE_ENABLE | CCR_CACHE_INVALIDATE; 157 158 #ifdef CCR_CACHE_EMODE 159 /* Force EMODE if possible */ 160 if (current_cpu_data.dcache.ways > 1) 161 flags |= CCR_CACHE_EMODE; 162 else 163 flags &= ~CCR_CACHE_EMODE; 164 #endif 165 166 #if defined(CONFIG_CACHE_WRITETHROUGH) 167 /* Write-through */ 168 flags |= CCR_CACHE_WT; 169 #elif defined(CONFIG_CACHE_WRITEBACK) 170 /* Write-back */ 171 flags |= CCR_CACHE_CB; 172 #else 173 /* Off */ 174 flags &= ~CCR_CACHE_ENABLE; 175 #endif 176 177 l2_cache_init(); 178 179 ctrl_outl(flags, CCR); 180 back_to_cached(); 181 } 182 #else 183 #define cache_init() do { } while (0) 184 #endif 185 186 #define CSHAPE(totalsize, linesize, assoc) \ 187 ((totalsize & ~0xff) | (linesize << 4) | assoc) 188 189 #define CACHE_DESC_SHAPE(desc) \ 190 CSHAPE((desc).way_size * (desc).ways, ilog2((desc).linesz), (desc).ways) 191 192 static void detect_cache_shape(void) 193 { 194 l1d_cache_shape = CACHE_DESC_SHAPE(current_cpu_data.dcache); 195 196 if (current_cpu_data.dcache.flags & SH_CACHE_COMBINED) 197 l1i_cache_shape = l1d_cache_shape; 198 else 199 l1i_cache_shape = CACHE_DESC_SHAPE(current_cpu_data.icache); 200 201 if (current_cpu_data.flags & CPU_HAS_L2_CACHE) 202 l2_cache_shape = CACHE_DESC_SHAPE(current_cpu_data.scache); 203 else 204 l2_cache_shape = -1; /* No S-cache */ 205 } 206 207 #ifdef CONFIG_SH_DSP 208 static void __init release_dsp(void) 209 { 210 unsigned long sr; 211 212 /* Clear SR.DSP bit */ 213 __asm__ __volatile__ ( 214 "stc\tsr, %0\n\t" 215 "and\t%1, %0\n\t" 216 "ldc\t%0, sr\n\t" 217 : "=&r" (sr) 218 : "r" (~SR_DSP) 219 ); 220 } 221 222 static void __init dsp_init(void) 223 { 224 unsigned long sr; 225 226 /* 227 * Set the SR.DSP bit, wait for one instruction, and then read 228 * back the SR value. 229 */ 230 __asm__ __volatile__ ( 231 "stc\tsr, %0\n\t" 232 "or\t%1, %0\n\t" 233 "ldc\t%0, sr\n\t" 234 "nop\n\t" 235 "stc\tsr, %0\n\t" 236 : "=&r" (sr) 237 : "r" (SR_DSP) 238 ); 239 240 /* If the DSP bit is still set, this CPU has a DSP */ 241 if (sr & SR_DSP) 242 current_cpu_data.flags |= CPU_HAS_DSP; 243 244 /* Now that we've determined the DSP status, clear the DSP bit. */ 245 release_dsp(); 246 } 247 #endif /* CONFIG_SH_DSP */ 248 249 /** 250 * sh_cpu_init 251 * 252 * This is our initial entry point for each CPU, and is invoked on the 253 * boot CPU prior to calling start_kernel(). For SMP, a combination of 254 * this and start_secondary() will bring up each processor to a ready 255 * state prior to hand forking the idle loop. 256 * 257 * We do all of the basic processor init here, including setting up 258 * the caches, FPU, DSP, etc. By the time start_kernel() is hit (and 259 * subsequently platform_setup()) things like determining the CPU 260 * subtype and initial configuration will all be done. 261 * 262 * Each processor family is still responsible for doing its own probing 263 * and cache configuration in detect_cpu_and_cache_system(). 264 */ 265 asmlinkage void __init sh_cpu_init(void) 266 { 267 current_thread_info()->cpu = hard_smp_processor_id(); 268 269 /* First, probe the CPU */ 270 detect_cpu_and_cache_system(); 271 272 if (current_cpu_data.type == CPU_SH_NONE) 273 panic("Unknown CPU"); 274 275 /* First setup the rest of the I-cache info */ 276 current_cpu_data.icache.entry_mask = current_cpu_data.icache.way_incr - 277 current_cpu_data.icache.linesz; 278 279 current_cpu_data.icache.way_size = current_cpu_data.icache.sets * 280 current_cpu_data.icache.linesz; 281 282 /* And the D-cache too */ 283 current_cpu_data.dcache.entry_mask = current_cpu_data.dcache.way_incr - 284 current_cpu_data.dcache.linesz; 285 286 current_cpu_data.dcache.way_size = current_cpu_data.dcache.sets * 287 current_cpu_data.dcache.linesz; 288 289 /* Init the cache */ 290 cache_init(); 291 292 if (raw_smp_processor_id() == 0) { 293 shm_align_mask = max_t(unsigned long, 294 current_cpu_data.dcache.way_size - 1, 295 PAGE_SIZE - 1); 296 297 /* Boot CPU sets the cache shape */ 298 detect_cache_shape(); 299 } 300 301 /* Disable the FPU */ 302 if (fpu_disabled) { 303 printk("FPU Disabled\n"); 304 current_cpu_data.flags &= ~CPU_HAS_FPU; 305 } 306 307 /* FPU initialization */ 308 disable_fpu(); 309 if ((current_cpu_data.flags & CPU_HAS_FPU)) { 310 current_thread_info()->status &= ~TS_USEDFPU; 311 clear_used_math(); 312 } 313 314 /* 315 * Initialize the per-CPU ASID cache very early, since the 316 * TLB flushing routines depend on this being setup. 317 */ 318 current_cpu_data.asid_cache = NO_CONTEXT; 319 320 #ifdef CONFIG_SH_DSP 321 /* Probe for DSP */ 322 dsp_init(); 323 324 /* Disable the DSP */ 325 if (dsp_disabled) { 326 printk("DSP Disabled\n"); 327 current_cpu_data.flags &= ~CPU_HAS_DSP; 328 release_dsp(); 329 } 330 #endif 331 332 speculative_execution_init(); 333 expmask_init(); 334 } 335