xref: /linux/arch/sh/kernel/cpu/clock.c (revision d680c76eccd9222031ee30dcee5fdedba2467610) 
1 /*
2  * arch/sh/kernel/cpu/clock.c - SuperH clock framework
3  *
4  *  Copyright (C) 2005, 2006, 2007  Paul Mundt
5  *
6  * This clock framework is derived from the OMAP version by:
7  *
8  *	Copyright (C) 2004 - 2005 Nokia Corporation
9  *	Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
10  *
11  *  Modified for omap shared clock framework by Tony Lindgren <tony@atomide.com>
12  *
13  * This file is subject to the terms and conditions of the GNU General Public
14  * License.  See the file "COPYING" in the main directory of this archive
15  * for more details.
16  */
17 #include <linux/kernel.h>
18 #include <linux/init.h>
19 #include <linux/module.h>
20 #include <linux/mutex.h>
21 #include <linux/list.h>
22 #include <linux/kref.h>
23 #include <linux/seq_file.h>
24 #include <linux/err.h>
25 #include <linux/platform_device.h>
26 #include <linux/proc_fs.h>
27 #include <asm/clock.h>
28 #include <asm/timer.h>
29 
30 static LIST_HEAD(clock_list);
31 static DEFINE_SPINLOCK(clock_lock);
32 static DEFINE_MUTEX(clock_list_sem);
33 
34 /*
35  * Each subtype is expected to define the init routines for these clocks,
36  * as each subtype (or processor family) will have these clocks at the
37  * very least. These are all provided through the CPG, which even some of
38  * the more quirky parts (such as ST40, SH4-202, etc.) still have.
39  *
40  * The processor-specific code is expected to register any additional
41  * clock sources that are of interest.
42  */
43 static struct clk master_clk = {
44 	.name		= "master_clk",
45 	.flags		= CLK_ALWAYS_ENABLED | CLK_RATE_PROPAGATES,
46 	.rate		= CONFIG_SH_PCLK_FREQ,
47 };
48 
49 static struct clk module_clk = {
50 	.name		= "module_clk",
51 	.parent		= &master_clk,
52 	.flags		= CLK_ALWAYS_ENABLED | CLK_RATE_PROPAGATES,
53 };
54 
55 static struct clk bus_clk = {
56 	.name		= "bus_clk",
57 	.parent		= &master_clk,
58 	.flags		= CLK_ALWAYS_ENABLED | CLK_RATE_PROPAGATES,
59 };
60 
61 static struct clk cpu_clk = {
62 	.name		= "cpu_clk",
63 	.parent		= &master_clk,
64 	.flags		= CLK_ALWAYS_ENABLED,
65 };
66 
67 /*
68  * The ordering of these clocks matters, do not change it.
69  */
70 static struct clk *onchip_clocks[] = {
71 	&master_clk,
72 	&module_clk,
73 	&bus_clk,
74 	&cpu_clk,
75 };
76 
77 static void propagate_rate(struct clk *clk)
78 {
79 	struct clk *clkp;
80 
81 	list_for_each_entry(clkp, &clock_list, node) {
82 		if (likely(clkp->parent != clk))
83 			continue;
84 		if (likely(clkp->ops && clkp->ops->recalc))
85 			clkp->ops->recalc(clkp);
86 		if (unlikely(clkp->flags & CLK_RATE_PROPAGATES))
87 			propagate_rate(clkp);
88 	}
89 }
90 
91 static int __clk_enable(struct clk *clk)
92 {
93 	/*
94 	 * See if this is the first time we're enabling the clock, some
95 	 * clocks that are always enabled still require "special"
96 	 * initialization. This is especially true if the clock mode
97 	 * changes and the clock needs to hunt for the proper set of
98 	 * divisors to use before it can effectively recalc.
99 	 */
100 	if (unlikely(atomic_read(&clk->kref.refcount) == 1))
101 		if (clk->ops && clk->ops->init)
102 			clk->ops->init(clk);
103 
104 	kref_get(&clk->kref);
105 
106 	if (clk->flags & CLK_ALWAYS_ENABLED)
107 		return 0;
108 
109 	if (likely(clk->ops && clk->ops->enable))
110 		clk->ops->enable(clk);
111 
112 	return 0;
113 }
114 
115 int clk_enable(struct clk *clk)
116 {
117 	unsigned long flags;
118 	int ret;
119 
120 	if (!clk)
121 		return -EINVAL;
122 
123 	clk_enable(clk->parent);
124 
125 	spin_lock_irqsave(&clock_lock, flags);
126 	ret = __clk_enable(clk);
127 	spin_unlock_irqrestore(&clock_lock, flags);
128 
129 	return ret;
130 }
131 EXPORT_SYMBOL_GPL(clk_enable);
132 
133 static void clk_kref_release(struct kref *kref)
134 {
135 	/* Nothing to do */
136 }
137 
138 static void __clk_disable(struct clk *clk)
139 {
140 	int count = kref_put(&clk->kref, clk_kref_release);
141 
142 	if (clk->flags & CLK_ALWAYS_ENABLED)
143 		return;
144 
145 	if (!count) {	/* count reaches zero, disable the clock */
146 		if (likely(clk->ops && clk->ops->disable))
147 			clk->ops->disable(clk);
148 	}
149 }
150 
151 void clk_disable(struct clk *clk)
152 {
153 	unsigned long flags;
154 
155 	if (!clk)
156 		return;
157 
158 	spin_lock_irqsave(&clock_lock, flags);
159 	__clk_disable(clk);
160 	spin_unlock_irqrestore(&clock_lock, flags);
161 
162 	clk_disable(clk->parent);
163 }
164 EXPORT_SYMBOL_GPL(clk_disable);
165 
166 int clk_register(struct clk *clk)
167 {
168 	mutex_lock(&clock_list_sem);
169 
170 	list_add(&clk->node, &clock_list);
171 	kref_init(&clk->kref);
172 
173 	mutex_unlock(&clock_list_sem);
174 
175 	if (clk->flags & CLK_ALWAYS_ENABLED) {
176 		pr_debug( "Clock '%s' is ALWAYS_ENABLED\n", clk->name);
177 		if (clk->ops && clk->ops->init)
178 			clk->ops->init(clk);
179 		if (clk->ops && clk->ops->enable)
180 			clk->ops->enable(clk);
181 		pr_debug( "Enabled.");
182 	}
183 
184 	return 0;
185 }
186 EXPORT_SYMBOL_GPL(clk_register);
187 
188 void clk_unregister(struct clk *clk)
189 {
190 	mutex_lock(&clock_list_sem);
191 	list_del(&clk->node);
192 	mutex_unlock(&clock_list_sem);
193 }
194 EXPORT_SYMBOL_GPL(clk_unregister);
195 
196 unsigned long clk_get_rate(struct clk *clk)
197 {
198 	return clk->rate;
199 }
200 EXPORT_SYMBOL_GPL(clk_get_rate);
201 
202 int clk_set_rate(struct clk *clk, unsigned long rate)
203 {
204 	return clk_set_rate_ex(clk, rate, 0);
205 }
206 EXPORT_SYMBOL_GPL(clk_set_rate);
207 
208 int clk_set_rate_ex(struct clk *clk, unsigned long rate, int algo_id)
209 {
210 	int ret = -EOPNOTSUPP;
211 
212 	if (likely(clk->ops && clk->ops->set_rate)) {
213 		unsigned long flags;
214 
215 		spin_lock_irqsave(&clock_lock, flags);
216 		ret = clk->ops->set_rate(clk, rate, algo_id);
217 		spin_unlock_irqrestore(&clock_lock, flags);
218 	}
219 
220 	if (unlikely(clk->flags & CLK_RATE_PROPAGATES))
221 		propagate_rate(clk);
222 
223 	return ret;
224 }
225 EXPORT_SYMBOL_GPL(clk_set_rate_ex);
226 
227 void clk_recalc_rate(struct clk *clk)
228 {
229 	if (likely(clk->ops && clk->ops->recalc)) {
230 		unsigned long flags;
231 
232 		spin_lock_irqsave(&clock_lock, flags);
233 		clk->ops->recalc(clk);
234 		spin_unlock_irqrestore(&clock_lock, flags);
235 	}
236 
237 	if (unlikely(clk->flags & CLK_RATE_PROPAGATES))
238 		propagate_rate(clk);
239 }
240 EXPORT_SYMBOL_GPL(clk_recalc_rate);
241 
242 int clk_set_parent(struct clk *clk, struct clk *parent)
243 {
244 	int ret = -EINVAL;
245 	struct clk *old;
246 
247 	if (!parent || !clk)
248 		return ret;
249 
250 	old = clk->parent;
251 	if (likely(clk->ops && clk->ops->set_parent)) {
252 		unsigned long flags;
253 		spin_lock_irqsave(&clock_lock, flags);
254 		ret = clk->ops->set_parent(clk, parent);
255 		spin_unlock_irqrestore(&clock_lock, flags);
256 		clk->parent = (ret ? old : parent);
257 	}
258 
259 	if (unlikely(clk->flags & CLK_RATE_PROPAGATES))
260 		propagate_rate(clk);
261 	return ret;
262 }
263 EXPORT_SYMBOL_GPL(clk_set_parent);
264 
265 struct clk *clk_get_parent(struct clk *clk)
266 {
267 	return clk->parent;
268 }
269 EXPORT_SYMBOL_GPL(clk_get_parent);
270 
271 long clk_round_rate(struct clk *clk, unsigned long rate)
272 {
273 	if (likely(clk->ops && clk->ops->round_rate)) {
274 		unsigned long flags, rounded;
275 
276 		spin_lock_irqsave(&clock_lock, flags);
277 		rounded = clk->ops->round_rate(clk, rate);
278 		spin_unlock_irqrestore(&clock_lock, flags);
279 
280 		return rounded;
281 	}
282 
283 	return clk_get_rate(clk);
284 }
285 EXPORT_SYMBOL_GPL(clk_round_rate);
286 
287 /*
288  * Returns a clock. Note that we first try to use device id on the bus
289  * and clock name. If this fails, we try to use clock name only.
290  */
291 struct clk *clk_get(struct device *dev, const char *id)
292 {
293 	struct clk *p, *clk = ERR_PTR(-ENOENT);
294 	int idno;
295 
296 	if (dev == NULL || dev->bus != &platform_bus_type)
297 		idno = -1;
298 	else
299 		idno = to_platform_device(dev)->id;
300 
301 	mutex_lock(&clock_list_sem);
302 	list_for_each_entry(p, &clock_list, node) {
303 		if (p->id == idno &&
304 		    strcmp(id, p->name) == 0 && try_module_get(p->owner)) {
305 			clk = p;
306 			goto found;
307 		}
308 	}
309 
310 	list_for_each_entry(p, &clock_list, node) {
311 		if (strcmp(id, p->name) == 0 && try_module_get(p->owner)) {
312 			clk = p;
313 			break;
314 		}
315 	}
316 
317 found:
318 	mutex_unlock(&clock_list_sem);
319 
320 	return clk;
321 }
322 EXPORT_SYMBOL_GPL(clk_get);
323 
324 void clk_put(struct clk *clk)
325 {
326 	if (clk && !IS_ERR(clk))
327 		module_put(clk->owner);
328 }
329 EXPORT_SYMBOL_GPL(clk_put);
330 
331 void __init __attribute__ ((weak))
332 arch_init_clk_ops(struct clk_ops **ops, int type)
333 {
334 }
335 
336 int __init __attribute__ ((weak))
337 arch_clk_init(void)
338 {
339 	return 0;
340 }
341 
342 static int show_clocks(char *buf, char **start, off_t off,
343 		       int len, int *eof, void *data)
344 {
345 	struct clk *clk;
346 	char *p = buf;
347 
348 	list_for_each_entry_reverse(clk, &clock_list, node) {
349 		unsigned long rate = clk_get_rate(clk);
350 
351 		p += sprintf(p, "%-12s\t: %ld.%02ldMHz\t%s\n", clk->name,
352 			     rate / 1000000, (rate % 1000000) / 10000,
353 			     ((clk->flags & CLK_ALWAYS_ENABLED) ||
354 			      (atomic_read(&clk->kref.refcount) != 1)) ?
355 			     "enabled" : "disabled");
356 	}
357 
358 	return p - buf;
359 }
360 
361 int __init clk_init(void)
362 {
363 	int i, ret = 0;
364 
365 	BUG_ON(!master_clk.rate);
366 
367 	for (i = 0; i < ARRAY_SIZE(onchip_clocks); i++) {
368 		struct clk *clk = onchip_clocks[i];
369 
370 		arch_init_clk_ops(&clk->ops, i);
371 		ret |= clk_register(clk);
372 	}
373 
374 	ret |= arch_clk_init();
375 
376 	/* Kick the child clocks.. */
377 	propagate_rate(&master_clk);
378 	propagate_rate(&bus_clk);
379 
380 	return ret;
381 }
382 
383 static int __init clk_proc_init(void)
384 {
385 	struct proc_dir_entry *p;
386 	p = create_proc_read_entry("clocks", S_IRUSR, NULL,
387 				   show_clocks, NULL);
388 	if (unlikely(!p))
389 		return -EINVAL;
390 
391 	return 0;
392 }
393 subsys_initcall(clk_proc_init);
394