1*f15cbe6fSPaul Mundt #ifndef __ASM_SH_CPU_SH4_RTC_H 2*f15cbe6fSPaul Mundt #define __ASM_SH_CPU_SH4_RTC_H 3*f15cbe6fSPaul Mundt 4*f15cbe6fSPaul Mundt #ifdef CONFIG_CPU_SUBTYPE_SH7723 5*f15cbe6fSPaul Mundt #define rtc_reg_size sizeof(u16) 6*f15cbe6fSPaul Mundt #else 7*f15cbe6fSPaul Mundt #define rtc_reg_size sizeof(u32) 8*f15cbe6fSPaul Mundt #endif 9*f15cbe6fSPaul Mundt 10*f15cbe6fSPaul Mundt #define RTC_BIT_INVERTED 0x40 /* bug on SH7750, SH7750S */ 11*f15cbe6fSPaul Mundt #define RTC_DEF_CAPABILITIES RTC_CAP_4_DIGIT_YEAR 12*f15cbe6fSPaul Mundt 13*f15cbe6fSPaul Mundt #endif /* __ASM_SH_CPU_SH4_RTC_H */ 14