1 #ifndef __ASM_CPU_SH4_DMA_H 2 #define __ASM_CPU_SH4_DMA_H 3 4 /* SH7751/7760/7780 DMA IRQ sources */ 5 6 #ifdef CONFIG_CPU_SH4A 7 8 #define DMAOR_INIT (DMAOR_DME) 9 10 #include <cpu/dma-sh4a.h> 11 #else /* CONFIG_CPU_SH4A */ 12 /* 13 * SH7750/SH7751/SH7760 14 */ 15 #define DMTE0_IRQ 34 16 #define DMTE4_IRQ 44 17 #define DMTE6_IRQ 46 18 #define DMAE0_IRQ 38 19 20 #define DMAOR_INIT (0x8000|DMAOR_DME) 21 #define SH_DMAC_BASE0 0xffa00000 22 #define SH_DMAC_BASE1 0xffa00070 23 /* Definitions for the SuperH DMAC */ 24 #define TM_BURST 0x00000080 25 #define TS_8 0x00000010 26 #define TS_16 0x00000020 27 #define TS_32 0x00000030 28 #define TS_64 0x00000000 29 30 #define CHCR_TS_LOW_MASK 0x70 31 #define CHCR_TS_LOW_SHIFT 4 32 #define CHCR_TS_HIGH_MASK 0 33 #define CHCR_TS_HIGH_SHIFT 0 34 35 #define DMAOR_COD 0x00000008 36 37 /* 38 * The SuperH DMAC supports a number of transmit sizes, we list them here, 39 * with their respective values as they appear in the CHCR registers. 40 * 41 * Defaults to a 64-bit transfer size. 42 */ 43 enum { 44 XMIT_SZ_8BIT = 1, 45 XMIT_SZ_16BIT = 2, 46 XMIT_SZ_32BIT = 3, 47 XMIT_SZ_64BIT = 0, 48 XMIT_SZ_256BIT = 4, 49 }; 50 51 /* 52 * The DMA count is defined as the number of bytes to transfer. 53 */ 54 #define TS_SHIFT { \ 55 [XMIT_SZ_8BIT] = 0, \ 56 [XMIT_SZ_16BIT] = 1, \ 57 [XMIT_SZ_32BIT] = 2, \ 58 [XMIT_SZ_64BIT] = 3, \ 59 [XMIT_SZ_256BIT] = 5, \ 60 } 61 62 #define TS_INDEX2VAL(i) (((i) & 7) << CHCR_TS_LOW_SHIFT) 63 64 #endif 65 66 #endif /* __ASM_CPU_SH4_DMA_H */ 67