1 #ifndef __ASM_CPU_SH3_DMA_H 2 #define __ASM_CPU_SH3_DMA_H 3 4 #if defined(CONFIG_CPU_SUBTYPE_SH7720) || \ 5 defined(CONFIG_CPU_SUBTYPE_SH7721) || \ 6 defined(CONFIG_CPU_SUBTYPE_SH7710) || \ 7 defined(CONFIG_CPU_SUBTYPE_SH7712) 8 #define SH_DMAC_BASE0 0xa4010020 9 #else /* SH7705/06/07/09 */ 10 #define SH_DMAC_BASE0 0xa4000020 11 #endif 12 13 #define DMTE0_IRQ 48 14 #define DMTE4_IRQ 76 15 16 /* Definitions for the SuperH DMAC */ 17 #define TM_BURST 0x00000020 18 #define TS_8 0x00000000 19 #define TS_16 0x00000008 20 #define TS_32 0x00000010 21 #define TS_128 0x00000018 22 23 #define CHCR_TS_LOW_MASK 0x18 24 #define CHCR_TS_LOW_SHIFT 3 25 #define CHCR_TS_HIGH_MASK 0 26 #define CHCR_TS_HIGH_SHIFT 0 27 28 #define DMAOR_INIT DMAOR_DME 29 30 /* 31 * The SuperH DMAC supports a number of transmit sizes, we list them here, 32 * with their respective values as they appear in the CHCR registers. 33 */ 34 enum { 35 XMIT_SZ_8BIT, 36 XMIT_SZ_16BIT, 37 XMIT_SZ_32BIT, 38 XMIT_SZ_128BIT, 39 }; 40 41 #define TS_SHIFT { \ 42 [XMIT_SZ_8BIT] = 0, \ 43 [XMIT_SZ_16BIT] = 1, \ 44 [XMIT_SZ_32BIT] = 2, \ 45 [XMIT_SZ_128BIT] = 4, \ 46 } 47 48 #define TS_INDEX2VAL(i) (((i) & 3) << CHCR_TS_LOW_SHIFT) 49 50 #endif /* __ASM_CPU_SH3_DMA_H */ 51