1*f15cbe6fSPaul Mundt #ifndef __ASM_CPU_SH3_DMA_H 2*f15cbe6fSPaul Mundt #define __ASM_CPU_SH3_DMA_H 3*f15cbe6fSPaul Mundt 4*f15cbe6fSPaul Mundt 5*f15cbe6fSPaul Mundt #if defined(CONFIG_CPU_SUBTYPE_SH7720) || \ 6*f15cbe6fSPaul Mundt defined(CONFIG_CPU_SUBTYPE_SH7721) 7*f15cbe6fSPaul Mundt #define SH_DMAC_BASE 0xa4010020 8*f15cbe6fSPaul Mundt #else 9*f15cbe6fSPaul Mundt #define SH_DMAC_BASE 0xa4000020 10*f15cbe6fSPaul Mundt #endif 11*f15cbe6fSPaul Mundt 12*f15cbe6fSPaul Mundt #if defined(CONFIG_CPU_SUBTYPE_SH7720) || defined(CONFIG_CPU_SUBTYPE_SH7709) 13*f15cbe6fSPaul Mundt #define DMTE0_IRQ 48 14*f15cbe6fSPaul Mundt #define DMTE1_IRQ 49 15*f15cbe6fSPaul Mundt #define DMTE2_IRQ 50 16*f15cbe6fSPaul Mundt #define DMTE3_IRQ 51 17*f15cbe6fSPaul Mundt #define DMTE4_IRQ 76 18*f15cbe6fSPaul Mundt #define DMTE5_IRQ 77 19*f15cbe6fSPaul Mundt #endif 20*f15cbe6fSPaul Mundt 21*f15cbe6fSPaul Mundt /* Definitions for the SuperH DMAC */ 22*f15cbe6fSPaul Mundt #define TM_BURST 0x00000020 23*f15cbe6fSPaul Mundt #define TS_8 0x00000000 24*f15cbe6fSPaul Mundt #define TS_16 0x00000008 25*f15cbe6fSPaul Mundt #define TS_32 0x00000010 26*f15cbe6fSPaul Mundt #define TS_128 0x00000018 27*f15cbe6fSPaul Mundt 28*f15cbe6fSPaul Mundt #define CHCR_TS_MASK 0x18 29*f15cbe6fSPaul Mundt #define CHCR_TS_SHIFT 3 30*f15cbe6fSPaul Mundt 31*f15cbe6fSPaul Mundt #define DMAOR_INIT DMAOR_DME 32*f15cbe6fSPaul Mundt 33*f15cbe6fSPaul Mundt /* 34*f15cbe6fSPaul Mundt * The SuperH DMAC supports a number of transmit sizes, we list them here, 35*f15cbe6fSPaul Mundt * with their respective values as they appear in the CHCR registers. 36*f15cbe6fSPaul Mundt */ 37*f15cbe6fSPaul Mundt enum { 38*f15cbe6fSPaul Mundt XMIT_SZ_8BIT, 39*f15cbe6fSPaul Mundt XMIT_SZ_16BIT, 40*f15cbe6fSPaul Mundt XMIT_SZ_32BIT, 41*f15cbe6fSPaul Mundt XMIT_SZ_128BIT, 42*f15cbe6fSPaul Mundt }; 43*f15cbe6fSPaul Mundt 44*f15cbe6fSPaul Mundt static unsigned int ts_shift[] __maybe_unused = { 45*f15cbe6fSPaul Mundt [XMIT_SZ_8BIT] = 0, 46*f15cbe6fSPaul Mundt [XMIT_SZ_16BIT] = 1, 47*f15cbe6fSPaul Mundt [XMIT_SZ_32BIT] = 2, 48*f15cbe6fSPaul Mundt [XMIT_SZ_128BIT] = 4, 49*f15cbe6fSPaul Mundt }; 50*f15cbe6fSPaul Mundt 51*f15cbe6fSPaul Mundt #endif /* __ASM_CPU_SH3_DMA_H */ 52