1 /* 2 * include/asm-sh/cpu-sh2a/cache.h 3 * 4 * Copyright (C) 2004 Paul Mundt 5 * 6 * This file is subject to the terms and conditions of the GNU General Public 7 * License. See the file "COPYING" in the main directory of this archive 8 * for more details. 9 */ 10 #ifndef __ASM_CPU_SH2A_CACHE_H 11 #define __ASM_CPU_SH2A_CACHE_H 12 13 #define L1_CACHE_SHIFT 4 14 15 #define SH_CACHE_VALID 1 16 #define SH_CACHE_UPDATED 2 17 #define SH_CACHE_COMBINED 4 18 #define SH_CACHE_ASSOC 8 19 20 #define SH_CCR 0xfffc1000 /* CCR1 */ 21 #define SH_CCR2 0xfffc1004 22 23 /* 24 * Most of the SH-2A CCR1 definitions resemble the SH-4 ones. All others not 25 * listed here are reserved. 26 */ 27 #define CCR_CACHE_CB 0x0000 /* Hack */ 28 #define CCR_CACHE_OCE 0x0001 29 #define CCR_CACHE_WT 0x0002 30 #define CCR_CACHE_OCI 0x0008 /* OCF */ 31 #define CCR_CACHE_ICE 0x0100 32 #define CCR_CACHE_ICI 0x0800 /* ICF */ 33 34 #define CACHE_IC_ADDRESS_ARRAY 0xf0000000 35 #define CACHE_OC_ADDRESS_ARRAY 0xf0800000 36 37 #define CCR_CACHE_ENABLE (CCR_CACHE_OCE | CCR_CACHE_ICE) 38 #define CCR_CACHE_INVALIDATE (CCR_CACHE_OCI | CCR_CACHE_ICI) 39 #define CCR_ICACHE_INVALIDATE CCR_CACHE_ICI 40 #define CCR_OCACHE_INVALIDATE CCR_CACHE_OCI 41 #define CACHE_PHYSADDR_MASK 0x1ffffc00 42 43 #endif /* __ASM_CPU_SH2A_CACHE_H */ 44