1 /* 2 * include/asm-sh/spinlock-cas.h 3 * 4 * Copyright (C) 2015 SEI 5 * 6 * This file is subject to the terms and conditions of the GNU General Public 7 * License. See the file "COPYING" in the main directory of this archive 8 * for more details. 9 */ 10 #ifndef __ASM_SH_SPINLOCK_CAS_H 11 #define __ASM_SH_SPINLOCK_CAS_H 12 13 #include <asm/barrier.h> 14 #include <asm/processor.h> 15 16 static inline unsigned __sl_cas(volatile unsigned *p, unsigned old, unsigned new) 17 { 18 __asm__ __volatile__("cas.l %1,%0,@r0" 19 : "+r"(new) 20 : "r"(old), "z"(p) 21 : "t", "memory" ); 22 return new; 23 } 24 25 /* 26 * Your basic SMP spinlocks, allowing only a single CPU anywhere 27 */ 28 29 #define arch_spin_is_locked(x) ((x)->lock <= 0) 30 #define arch_spin_lock_flags(lock, flags) arch_spin_lock(lock) 31 32 static inline void arch_spin_unlock_wait(arch_spinlock_t *lock) 33 { 34 smp_cond_load_acquire(&lock->lock, VAL > 0); 35 } 36 37 static inline void arch_spin_lock(arch_spinlock_t *lock) 38 { 39 while (!__sl_cas(&lock->lock, 1, 0)); 40 } 41 42 static inline void arch_spin_unlock(arch_spinlock_t *lock) 43 { 44 __sl_cas(&lock->lock, 0, 1); 45 } 46 47 static inline int arch_spin_trylock(arch_spinlock_t *lock) 48 { 49 return __sl_cas(&lock->lock, 1, 0); 50 } 51 52 /* 53 * Read-write spinlocks, allowing multiple readers but only one writer. 54 * 55 * NOTE! it is quite common to have readers in interrupts but no interrupt 56 * writers. For those circumstances we can "mix" irq-safe locks - any writer 57 * needs to get a irq-safe write-lock, but readers can get non-irqsafe 58 * read-locks. 59 */ 60 61 /** 62 * read_can_lock - would read_trylock() succeed? 63 * @lock: the rwlock in question. 64 */ 65 #define arch_read_can_lock(x) ((x)->lock > 0) 66 67 /** 68 * write_can_lock - would write_trylock() succeed? 69 * @lock: the rwlock in question. 70 */ 71 #define arch_write_can_lock(x) ((x)->lock == RW_LOCK_BIAS) 72 73 static inline void arch_read_lock(arch_rwlock_t *rw) 74 { 75 unsigned old; 76 do old = rw->lock; 77 while (!old || __sl_cas(&rw->lock, old, old-1) != old); 78 } 79 80 static inline void arch_read_unlock(arch_rwlock_t *rw) 81 { 82 unsigned old; 83 do old = rw->lock; 84 while (__sl_cas(&rw->lock, old, old+1) != old); 85 } 86 87 static inline void arch_write_lock(arch_rwlock_t *rw) 88 { 89 while (__sl_cas(&rw->lock, RW_LOCK_BIAS, 0) != RW_LOCK_BIAS); 90 } 91 92 static inline void arch_write_unlock(arch_rwlock_t *rw) 93 { 94 __sl_cas(&rw->lock, 0, RW_LOCK_BIAS); 95 } 96 97 static inline int arch_read_trylock(arch_rwlock_t *rw) 98 { 99 unsigned old; 100 do old = rw->lock; 101 while (old && __sl_cas(&rw->lock, old, old-1) != old); 102 return !!old; 103 } 104 105 static inline int arch_write_trylock(arch_rwlock_t *rw) 106 { 107 return __sl_cas(&rw->lock, RW_LOCK_BIAS, 0) == RW_LOCK_BIAS; 108 } 109 110 #define arch_read_lock_flags(lock, flags) arch_read_lock(lock) 111 #define arch_write_lock_flags(lock, flags) arch_write_lock(lock) 112 113 #define arch_spin_relax(lock) cpu_relax() 114 #define arch_read_relax(lock) cpu_relax() 115 #define arch_write_relax(lock) cpu_relax() 116 117 #endif /* __ASM_SH_SPINLOCK_CAS_H */ 118