1 /* 2 * sh7760fb.h -- platform data for SH7760/SH7763 LCDC framebuffer driver. 3 * 4 * (c) 2006-2008 MSC Vertriebsges.m.b.H., 5 * Manuel Lauss <mano@roarinelk.homelinux.net> 6 * (c) 2008 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com> 7 */ 8 9 #ifndef _ASM_SH_SH7760FB_H 10 #define _ASM_SH_SH7760FB_H 11 12 /* 13 * some bits of the colormap registers should be written as zero. 14 * create a mask for that. 15 */ 16 #define SH7760FB_PALETTE_MASK 0x00f8fcf8 17 18 /* The LCDC dma engine always sets bits 27-26 to 1: this is Area3 */ 19 #define SH7760FB_DMA_MASK 0x0C000000 20 21 /* palette */ 22 #define LDPR(x) (((x) << 2)) 23 24 /* framebuffer registers and bits */ 25 #define LDICKR 0x400 26 #define LDMTR 0x402 27 /* see sh7760fb.h for LDMTR bits */ 28 #define LDDFR 0x404 29 #define LDDFR_PABD (1 << 8) 30 #define LDDFR_COLOR_MASK 0x7F 31 #define LDSMR 0x406 32 #define LDSMR_ROT (1 << 13) 33 #define LDSARU 0x408 34 #define LDSARL 0x40c 35 #define LDLAOR 0x410 36 #define LDPALCR 0x412 37 #define LDPALCR_PALS (1 << 4) 38 #define LDPALCR_PALEN (1 << 0) 39 #define LDHCNR 0x414 40 #define LDHSYNR 0x416 41 #define LDVDLNR 0x418 42 #define LDVTLNR 0x41a 43 #define LDVSYNR 0x41c 44 #define LDACLNR 0x41e 45 #define LDINTR 0x420 46 #define LDPMMR 0x424 47 #define LDPSPR 0x426 48 #define LDCNTR 0x428 49 #define LDCNTR_DON (1 << 0) 50 #define LDCNTR_DON2 (1 << 4) 51 52 #ifdef CONFIG_CPU_SUBTYPE_SH7763 53 # define LDLIRNR 0x440 54 /* LDINTR bit */ 55 # define LDINTR_MINTEN (1 << 15) 56 # define LDINTR_FINTEN (1 << 14) 57 # define LDINTR_VSINTEN (1 << 13) 58 # define LDINTR_VEINTEN (1 << 12) 59 # define LDINTR_MINTS (1 << 11) 60 # define LDINTR_FINTS (1 << 10) 61 # define LDINTR_VSINTS (1 << 9) 62 # define LDINTR_VEINTS (1 << 8) 63 # define VINT_START (LDINTR_VSINTEN) 64 # define VINT_CHECK (LDINTR_VSINTS) 65 #else 66 /* LDINTR bit */ 67 # define LDINTR_VINTSEL (1 << 12) 68 # define LDINTR_VINTE (1 << 8) 69 # define LDINTR_VINTS (1 << 0) 70 # define VINT_START (LDINTR_VINTSEL) 71 # define VINT_CHECK (LDINTR_VINTS) 72 #endif 73 74 /* HSYNC polarity inversion */ 75 #define LDMTR_FLMPOL (1 << 15) 76 77 /* VSYNC polarity inversion */ 78 #define LDMTR_CL1POL (1 << 14) 79 80 /* DISPLAY-ENABLE polarity inversion */ 81 #define LDMTR_DISPEN_LOWACT (1 << 13) 82 83 /* DISPLAY DATA BUS polarity inversion */ 84 #define LDMTR_DPOL_LOWACT (1 << 12) 85 86 /* AC modulation signal enable */ 87 #define LDMTR_MCNT (1 << 10) 88 89 /* Disable output of HSYNC during VSYNC period */ 90 #define LDMTR_CL1CNT (1 << 9) 91 92 /* Disable output of VSYNC during VSYNC period */ 93 #define LDMTR_CL2CNT (1 << 8) 94 95 /* Display types supported by the LCDC */ 96 #define LDMTR_STN_MONO_4 0x00 97 #define LDMTR_STN_MONO_8 0x01 98 #define LDMTR_STN_COLOR_4 0x08 99 #define LDMTR_STN_COLOR_8 0x09 100 #define LDMTR_STN_COLOR_12 0x0A 101 #define LDMTR_STN_COLOR_16 0x0B 102 #define LDMTR_DSTN_MONO_8 0x11 103 #define LDMTR_DSTN_MONO_16 0x13 104 #define LDMTR_DSTN_COLOR_8 0x19 105 #define LDMTR_DSTN_COLOR_12 0x1A 106 #define LDMTR_DSTN_COLOR_16 0x1B 107 #define LDMTR_TFT_COLOR_16 0x2B 108 109 /* framebuffer color layout */ 110 #define LDDFR_1BPP_MONO 0x00 111 #define LDDFR_2BPP_MONO 0x01 112 #define LDDFR_4BPP_MONO 0x02 113 #define LDDFR_6BPP_MONO 0x04 114 #define LDDFR_4BPP 0x0A 115 #define LDDFR_8BPP 0x0C 116 #define LDDFR_16BPP_RGB555 0x1D 117 #define LDDFR_16BPP_RGB565 0x2D 118 119 /* LCDC Pixclock sources */ 120 #define LCDC_CLKSRC_BUSCLOCK 0 121 #define LCDC_CLKSRC_PERIPHERAL 1 122 #define LCDC_CLKSRC_EXTERNAL 2 123 124 #define LDICKR_CLKSRC(x) \ 125 (((x) & 3) << 12) 126 127 /* LCDC pixclock input divider. Set to 1 at a minimum! */ 128 #define LDICKR_CLKDIV(x) \ 129 ((x) & 0x1f) 130 131 struct sh7760fb_platdata { 132 133 /* Set this member to a valid fb_videmode for the display you 134 * wish to use. The following members must be initialized: 135 * xres, yres, hsync_len, vsync_len, sync, 136 * {left,right,upper,lower}_margin. 137 * The driver uses the above members to calculate register values 138 * and memory requirements. Other members are ignored but may 139 * be used by other framebuffer layer components. 140 */ 141 struct fb_videomode *def_mode; 142 143 /* LDMTR includes display type and signal polarity. The 144 * HSYNC/VSYNC polarities are derived from the fb_var_screeninfo 145 * data above; however the polarities of the following signals 146 * must be encoded in the ldmtr member: 147 * Display Enable signal (default high-active) DISPEN_LOWACT 148 * Display Data signals (default high-active) DPOL_LOWACT 149 * AC Modulation signal (default off) MCNT 150 * Hsync-During-Vsync suppression (default off) CL1CNT 151 * Vsync-during-vsync suppression (default off) CL2CNT 152 * NOTE: also set a display type! 153 * (one of LDMTR_{STN,DSTN,TFT}_{MONO,COLOR}_{4,8,12,16}) 154 */ 155 u16 ldmtr; 156 157 /* LDDFR controls framebuffer image format (depth, organization) 158 * Use ONE of the LDDFR_?BPP_* macros! 159 */ 160 u16 lddfr; 161 162 /* LDPMMR and LDPSPR control the timing of the power signals 163 * for the display. Please read the SH7760 Hardware Manual, 164 * Chapters 30.3.17, 30.3.18 and 30.4.6! 165 */ 166 u16 ldpmmr; 167 u16 ldpspr; 168 169 /* LDACLNR contains the line numbers after which the AC modulation 170 * signal is to toggle. Set to ZERO for TFTs or displays which 171 * do not need it. (Chapter 30.3.15 in SH7760 Hardware Manual). 172 */ 173 u16 ldaclnr; 174 175 /* LDICKR contains information on pixelclock source and config. 176 * Please use the LDICKR_CLKSRC() and LDICKR_CLKDIV() macros. 177 * minimal value for CLKDIV() must be 1!. 178 */ 179 u16 ldickr; 180 181 /* set this member to 1 if you wish to use the LCDC's hardware 182 * rotation function. This is limited to displays <= 320x200 183 * pixels resolution! 184 */ 185 int rotate; /* set to 1 to rotate 90 CCW */ 186 187 /* set this to 1 to suppress vsync irq use. */ 188 int novsync; 189 190 /* blanking hook for platform. Set this if your platform can do 191 * more than the LCDC in terms of blanking (e.g. disable clock 192 * generator / backlight power supply / etc. 193 */ 194 void (*blank) (int); 195 }; 196 197 #endif /* _ASM_SH_SH7760FB_H */ 198