1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef __ASM_SH_MMU_CONTEXT_32_H 3 #define __ASM_SH_MMU_CONTEXT_32_H 4 5 #ifdef CONFIG_CPU_HAS_PTEAEX 6 static inline void set_asid(unsigned long asid) 7 { 8 __raw_writel(asid, MMU_PTEAEX); 9 } 10 11 static inline unsigned long get_asid(void) 12 { 13 return __raw_readl(MMU_PTEAEX) & MMU_CONTEXT_ASID_MASK; 14 } 15 #else 16 static inline void set_asid(unsigned long asid) 17 { 18 unsigned long __dummy; 19 20 __asm__ __volatile__ ("mov.l %2, %0\n\t" 21 "and %3, %0\n\t" 22 "or %1, %0\n\t" 23 "mov.l %0, %2" 24 : "=&r" (__dummy) 25 : "r" (asid), "m" (__m(MMU_PTEH)), 26 "r" (0xffffff00)); 27 } 28 29 static inline unsigned long get_asid(void) 30 { 31 unsigned long asid; 32 33 __asm__ __volatile__ ("mov.l %1, %0" 34 : "=r" (asid) 35 : "m" (__m(MMU_PTEH))); 36 asid &= MMU_CONTEXT_ASID_MASK; 37 return asid; 38 } 39 #endif /* CONFIG_CPU_HAS_PTEAEX */ 40 41 /* MMU_TTB is used for optimizing the fault handling. */ 42 static inline void set_TTB(pgd_t *pgd) 43 { 44 __raw_writel((unsigned long)pgd, MMU_TTB); 45 } 46 47 static inline pgd_t *get_TTB(void) 48 { 49 return (pgd_t *)__raw_readl(MMU_TTB); 50 } 51 #endif /* __ASM_SH_MMU_CONTEXT_32_H */ 52