1 /* 2 * New-style PCI core. 3 * 4 * Copyright (c) 2004 - 2009 Paul Mundt 5 * Copyright (c) 2002 M. R. Brown 6 * 7 * Modelled after arch/mips/pci/pci.c: 8 * Copyright (C) 2003, 04 Ralf Baechle (ralf@linux-mips.org) 9 * 10 * This file is subject to the terms and conditions of the GNU General Public 11 * License. See the file "COPYING" in the main directory of this archive 12 * for more details. 13 */ 14 #include <linux/kernel.h> 15 #include <linux/mm.h> 16 #include <linux/pci.h> 17 #include <linux/init.h> 18 #include <linux/types.h> 19 #include <linux/dma-debug.h> 20 #include <linux/io.h> 21 #include <linux/mutex.h> 22 23 unsigned long PCIBIOS_MIN_IO = 0x0000; 24 unsigned long PCIBIOS_MIN_MEM = 0; 25 26 /* 27 * The PCI controller list. 28 */ 29 static struct pci_channel *hose_head, **hose_tail = &hose_head; 30 31 static int pci_initialized; 32 33 static void __devinit pcibios_scanbus(struct pci_channel *hose) 34 { 35 static int next_busno; 36 static int need_domain_info; 37 struct pci_bus *bus; 38 39 bus = pci_scan_bus(next_busno, hose->pci_ops, hose); 40 hose->bus = bus; 41 42 need_domain_info = need_domain_info || hose->index; 43 hose->need_domain_info = need_domain_info; 44 if (bus) { 45 next_busno = bus->subordinate + 1; 46 /* Don't allow 8-bit bus number overflow inside the hose - 47 reserve some space for bridges. */ 48 if (next_busno > 224) { 49 next_busno = 0; 50 need_domain_info = 1; 51 } 52 53 pci_bus_size_bridges(bus); 54 pci_bus_assign_resources(bus); 55 pci_enable_bridges(bus); 56 } 57 } 58 59 static DEFINE_MUTEX(pci_scan_mutex); 60 61 void __devinit register_pci_controller(struct pci_channel *hose) 62 { 63 if (request_resource(&iomem_resource, hose->mem_resource) < 0) 64 goto out; 65 if (request_resource(&ioport_resource, hose->io_resource) < 0) { 66 release_resource(hose->mem_resource); 67 goto out; 68 } 69 70 *hose_tail = hose; 71 hose_tail = &hose->next; 72 73 /* 74 * Do not panic here but later - this might hapen before console init. 75 */ 76 if (!hose->io_map_base) { 77 printk(KERN_WARNING 78 "registering PCI controller with io_map_base unset\n"); 79 } 80 81 /* 82 * Scan the bus if it is register after the PCI subsystem 83 * initialization. 84 */ 85 if (pci_initialized) { 86 mutex_lock(&pci_scan_mutex); 87 pcibios_scanbus(hose); 88 mutex_unlock(&pci_scan_mutex); 89 } 90 91 return; 92 93 out: 94 printk(KERN_WARNING "Skipping PCI bus scan due to resource conflict\n"); 95 } 96 97 static int __init pcibios_init(void) 98 { 99 struct pci_channel *hose; 100 101 /* Scan all of the recorded PCI controllers. */ 102 for (hose = hose_head; hose; hose = hose->next) 103 pcibios_scanbus(hose); 104 105 pci_fixup_irqs(pci_common_swizzle, pcibios_map_platform_irq); 106 107 dma_debug_add_bus(&pci_bus_type); 108 109 pci_initialized = 1; 110 111 return 0; 112 } 113 subsys_initcall(pcibios_init); 114 115 static void pcibios_fixup_device_resources(struct pci_dev *dev, 116 struct pci_bus *bus) 117 { 118 /* Update device resources. */ 119 struct pci_channel *hose = bus->sysdata; 120 unsigned long offset = 0; 121 int i; 122 123 for (i = 0; i < PCI_NUM_RESOURCES; i++) { 124 if (!dev->resource[i].start) 125 continue; 126 if (dev->resource[i].flags & IORESOURCE_PCI_FIXED) 127 continue; 128 if (dev->resource[i].flags & IORESOURCE_IO) 129 offset = hose->io_offset; 130 else if (dev->resource[i].flags & IORESOURCE_MEM) 131 offset = hose->mem_offset; 132 133 dev->resource[i].start += offset; 134 dev->resource[i].end += offset; 135 } 136 } 137 138 /* 139 * Called after each bus is probed, but before its children 140 * are examined. 141 */ 142 void __devinit pcibios_fixup_bus(struct pci_bus *bus) 143 { 144 struct pci_dev *dev = bus->self; 145 struct list_head *ln; 146 struct pci_channel *chan = bus->sysdata; 147 148 if (!dev) { 149 bus->resource[0] = chan->io_resource; 150 bus->resource[1] = chan->mem_resource; 151 } 152 153 for (ln = bus->devices.next; ln != &bus->devices; ln = ln->next) { 154 dev = pci_dev_b(ln); 155 156 if ((dev->class >> 8) != PCI_CLASS_BRIDGE_PCI) 157 pcibios_fixup_device_resources(dev, bus); 158 } 159 } 160 161 /* 162 * We need to avoid collisions with `mirrored' VGA ports 163 * and other strange ISA hardware, so we always want the 164 * addresses to be allocated in the 0x000-0x0ff region 165 * modulo 0x400. 166 */ 167 void pcibios_align_resource(void *data, struct resource *res, 168 resource_size_t size, resource_size_t align) 169 { 170 struct pci_dev *dev = data; 171 struct pci_channel *chan = dev->sysdata; 172 resource_size_t start = res->start; 173 174 if (res->flags & IORESOURCE_IO) { 175 if (start < PCIBIOS_MIN_IO + chan->io_resource->start) 176 start = PCIBIOS_MIN_IO + chan->io_resource->start; 177 178 /* 179 * Put everything into 0x00-0xff region modulo 0x400. 180 */ 181 if (start & 0x300) 182 start = (start + 0x3ff) & ~0x3ff; 183 } else if (res->flags & IORESOURCE_MEM) { 184 if (start < PCIBIOS_MIN_MEM + chan->mem_resource->start) 185 start = PCIBIOS_MIN_MEM + chan->mem_resource->start; 186 } 187 188 res->start = start; 189 } 190 191 void pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region, 192 struct resource *res) 193 { 194 struct pci_channel *hose = dev->sysdata; 195 unsigned long offset = 0; 196 197 if (res->flags & IORESOURCE_IO) 198 offset = hose->io_offset; 199 else if (res->flags & IORESOURCE_MEM) 200 offset = hose->mem_offset; 201 202 region->start = res->start - offset; 203 region->end = res->end - offset; 204 } 205 206 void __devinit 207 pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res, 208 struct pci_bus_region *region) 209 { 210 struct pci_channel *hose = dev->sysdata; 211 unsigned long offset = 0; 212 213 if (res->flags & IORESOURCE_IO) 214 offset = hose->io_offset; 215 else if (res->flags & IORESOURCE_MEM) 216 offset = hose->mem_offset; 217 218 res->start = region->start + offset; 219 res->end = region->end + offset; 220 } 221 222 int pcibios_enable_device(struct pci_dev *dev, int mask) 223 { 224 u16 cmd, old_cmd; 225 int idx; 226 struct resource *r; 227 228 pci_read_config_word(dev, PCI_COMMAND, &cmd); 229 old_cmd = cmd; 230 for (idx=0; idx < PCI_NUM_RESOURCES; idx++) { 231 /* Only set up the requested stuff */ 232 if (!(mask & (1<<idx))) 233 continue; 234 235 r = &dev->resource[idx]; 236 if (!(r->flags & (IORESOURCE_IO | IORESOURCE_MEM))) 237 continue; 238 if ((idx == PCI_ROM_RESOURCE) && 239 (!(r->flags & IORESOURCE_ROM_ENABLE))) 240 continue; 241 if (!r->start && r->end) { 242 printk(KERN_ERR "PCI: Device %s not available " 243 "because of resource collisions\n", 244 pci_name(dev)); 245 return -EINVAL; 246 } 247 if (r->flags & IORESOURCE_IO) 248 cmd |= PCI_COMMAND_IO; 249 if (r->flags & IORESOURCE_MEM) 250 cmd |= PCI_COMMAND_MEMORY; 251 } 252 if (cmd != old_cmd) { 253 printk("PCI: Enabling device %s (%04x -> %04x)\n", 254 pci_name(dev), old_cmd, cmd); 255 pci_write_config_word(dev, PCI_COMMAND, cmd); 256 } 257 return 0; 258 } 259 260 /* 261 * If we set up a device for bus mastering, we need to check and set 262 * the latency timer as it may not be properly set. 263 */ 264 static unsigned int pcibios_max_latency = 255; 265 266 void pcibios_set_master(struct pci_dev *dev) 267 { 268 u8 lat; 269 pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat); 270 if (lat < 16) 271 lat = (64 <= pcibios_max_latency) ? 64 : pcibios_max_latency; 272 else if (lat > pcibios_max_latency) 273 lat = pcibios_max_latency; 274 else 275 return; 276 printk(KERN_INFO "PCI: Setting latency timer of device %s to %d\n", 277 pci_name(dev), lat); 278 pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat); 279 } 280 281 void __init pcibios_update_irq(struct pci_dev *dev, int irq) 282 { 283 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq); 284 } 285 286 char * __devinit pcibios_setup(char *str) 287 { 288 return str; 289 } 290 291 int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma, 292 enum pci_mmap_state mmap_state, int write_combine) 293 { 294 /* 295 * I/O space can be accessed via normal processor loads and stores on 296 * this platform but for now we elect not to do this and portable 297 * drivers should not do this anyway. 298 */ 299 if (mmap_state == pci_mmap_io) 300 return -EINVAL; 301 302 /* 303 * Ignore write-combine; for now only return uncached mappings. 304 */ 305 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); 306 307 return remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff, 308 vma->vm_end - vma->vm_start, 309 vma->vm_page_prot); 310 } 311 312 #ifndef CONFIG_GENERIC_IOMAP 313 314 static void __iomem *ioport_map_pci(struct pci_dev *dev, 315 unsigned long port, unsigned int nr) 316 { 317 struct pci_channel *chan = dev->sysdata; 318 319 if (unlikely(!chan->io_map_base)) { 320 chan->io_map_base = generic_io_base; 321 322 if (pci_domains_supported) 323 panic("To avoid data corruption io_map_base MUST be " 324 "set with multiple PCI domains."); 325 } 326 327 328 return (void __iomem *)(chan->io_map_base + port); 329 } 330 331 void __iomem *pci_iomap(struct pci_dev *dev, int bar, unsigned long maxlen) 332 { 333 resource_size_t start = pci_resource_start(dev, bar); 334 resource_size_t len = pci_resource_len(dev, bar); 335 unsigned long flags = pci_resource_flags(dev, bar); 336 337 if (unlikely(!len || !start)) 338 return NULL; 339 if (maxlen && len > maxlen) 340 len = maxlen; 341 342 if (flags & IORESOURCE_IO) 343 return ioport_map_pci(dev, start, len); 344 if (flags & IORESOURCE_MEM) { 345 if (flags & IORESOURCE_CACHEABLE) 346 return ioremap(start, len); 347 return ioremap_nocache(start, len); 348 } 349 350 return NULL; 351 } 352 EXPORT_SYMBOL(pci_iomap); 353 354 void pci_iounmap(struct pci_dev *dev, void __iomem *addr) 355 { 356 iounmap(addr); 357 } 358 EXPORT_SYMBOL(pci_iounmap); 359 360 #endif /* CONFIG_GENERIC_IOMAP */ 361 362 #ifdef CONFIG_HOTPLUG 363 EXPORT_SYMBOL(pcibios_resource_to_bus); 364 EXPORT_SYMBOL(pcibios_bus_to_resource); 365 EXPORT_SYMBOL(PCIBIOS_MIN_IO); 366 EXPORT_SYMBOL(PCIBIOS_MIN_MEM); 367 #endif 368