1 /* 2 * arch/sh/drivers/pci/pci.c 3 * 4 * Copyright (c) 2002 M. R. Brown <mrbrown@linux-sh.org> 5 * Copyright (c) 2004 - 2006 Paul Mundt <lethal@linux-sh.org> 6 * 7 * These functions are collected here to reduce duplication of common 8 * code amongst the many platform-specific PCI support code files. 9 * 10 * These routines require the following board-specific routines: 11 * void pcibios_fixup_irqs(); 12 * 13 * See include/asm-sh/pci.h for more information. 14 * 15 * This file is subject to the terms and conditions of the GNU General Public 16 * License. See the file "COPYING" in the main directory of this archive 17 * for more details. 18 */ 19 #include <linux/kernel.h> 20 #include <linux/pci.h> 21 #include <linux/init.h> 22 #include <asm/io.h> 23 24 static int __init pcibios_init(void) 25 { 26 struct pci_channel *p; 27 struct pci_bus *bus; 28 int busno; 29 30 #ifdef CONFIG_PCI_AUTO 31 /* assign resources */ 32 busno = 0; 33 for (p = board_pci_channels; p->pci_ops != NULL; p++) 34 busno = pciauto_assign_resources(busno, p) + 1; 35 #endif 36 37 /* scan the buses */ 38 busno = 0; 39 for (p = board_pci_channels; p->pci_ops != NULL; p++) { 40 bus = pci_scan_bus(busno, p->pci_ops, p); 41 busno = bus->subordinate + 1; 42 } 43 44 pci_fixup_irqs(pci_common_swizzle, pcibios_map_platform_irq); 45 46 return 0; 47 } 48 subsys_initcall(pcibios_init); 49 50 /* 51 * Called after each bus is probed, but before its children 52 * are examined. 53 */ 54 void __devinit __weak pcibios_fixup_bus(struct pci_bus *bus) 55 { 56 pci_read_bridge_bases(bus); 57 } 58 59 void pcibios_align_resource(void *data, struct resource *res, 60 resource_size_t size, resource_size_t align) 61 __attribute__ ((weak)); 62 63 /* 64 * We need to avoid collisions with `mirrored' VGA ports 65 * and other strange ISA hardware, so we always want the 66 * addresses to be allocated in the 0x000-0x0ff region 67 * modulo 0x400. 68 */ 69 void pcibios_align_resource(void *data, struct resource *res, 70 resource_size_t size, resource_size_t align) 71 { 72 if (res->flags & IORESOURCE_IO) { 73 resource_size_t start = res->start; 74 75 if (start & 0x300) { 76 start = (start + 0x3ff) & ~0x3ff; 77 res->start = start; 78 } 79 } 80 } 81 82 int pcibios_enable_device(struct pci_dev *dev, int mask) 83 { 84 u16 cmd, old_cmd; 85 int idx; 86 struct resource *r; 87 88 pci_read_config_word(dev, PCI_COMMAND, &cmd); 89 old_cmd = cmd; 90 for(idx=0; idx<6; idx++) { 91 if (!(mask & (1 << idx))) 92 continue; 93 r = &dev->resource[idx]; 94 if (!r->start && r->end) { 95 printk(KERN_ERR "PCI: Device %s not available because " 96 "of resource collisions\n", pci_name(dev)); 97 return -EINVAL; 98 } 99 if (r->flags & IORESOURCE_IO) 100 cmd |= PCI_COMMAND_IO; 101 if (r->flags & IORESOURCE_MEM) 102 cmd |= PCI_COMMAND_MEMORY; 103 } 104 if (dev->resource[PCI_ROM_RESOURCE].start) 105 cmd |= PCI_COMMAND_MEMORY; 106 if (cmd != old_cmd) { 107 printk(KERN_INFO "PCI: Enabling device %s (%04x -> %04x)\n", 108 pci_name(dev), old_cmd, cmd); 109 pci_write_config_word(dev, PCI_COMMAND, cmd); 110 } 111 return 0; 112 } 113 114 /* 115 * If we set up a device for bus mastering, we need to check and set 116 * the latency timer as it may not be properly set. 117 */ 118 static unsigned int pcibios_max_latency = 255; 119 120 void pcibios_set_master(struct pci_dev *dev) 121 { 122 u8 lat; 123 pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat); 124 if (lat < 16) 125 lat = (64 <= pcibios_max_latency) ? 64 : pcibios_max_latency; 126 else if (lat > pcibios_max_latency) 127 lat = pcibios_max_latency; 128 else 129 return; 130 printk(KERN_INFO "PCI: Setting latency timer of device %s to %d\n", 131 pci_name(dev), lat); 132 pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat); 133 } 134 135 void __init pcibios_update_irq(struct pci_dev *dev, int irq) 136 { 137 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq); 138 } 139 140 void __iomem *pci_iomap(struct pci_dev *dev, int bar, unsigned long maxlen) 141 { 142 resource_size_t start = pci_resource_start(dev, bar); 143 resource_size_t len = pci_resource_len(dev, bar); 144 unsigned long flags = pci_resource_flags(dev, bar); 145 146 if (unlikely(!len || !start)) 147 return NULL; 148 if (maxlen && len > maxlen) 149 len = maxlen; 150 151 /* 152 * Presently the IORESOURCE_MEM case is a bit special, most 153 * SH7751 style PCI controllers have PCI memory at a fixed 154 * location in the address space where no remapping is desired 155 * (typically at 0xfd000000, but is_pci_memaddr() will know 156 * best). With the IORESOURCE_MEM case more care has to be taken 157 * to inhibit page table mapping for legacy cores, but this is 158 * punted off to __ioremap(). 159 * -- PFM. 160 */ 161 if (flags & IORESOURCE_IO) 162 return ioport_map(start, len); 163 if (flags & IORESOURCE_MEM) 164 return ioremap(start, len); 165 166 return NULL; 167 } 168 EXPORT_SYMBOL(pci_iomap); 169 170 void pci_iounmap(struct pci_dev *dev, void __iomem *addr) 171 { 172 iounmap(addr); 173 } 174 EXPORT_SYMBOL(pci_iounmap); 175