1 /* 2 * New-style PCI core. 3 * 4 * Copyright (c) 2004 - 2009 Paul Mundt 5 * Copyright (c) 2002 M. R. Brown 6 * 7 * Modelled after arch/mips/pci/pci.c: 8 * Copyright (C) 2003, 04 Ralf Baechle (ralf@linux-mips.org) 9 * 10 * This file is subject to the terms and conditions of the GNU General Public 11 * License. See the file "COPYING" in the main directory of this archive 12 * for more details. 13 */ 14 #include <linux/kernel.h> 15 #include <linux/mm.h> 16 #include <linux/pci.h> 17 #include <linux/init.h> 18 #include <linux/types.h> 19 #include <linux/dma-debug.h> 20 #include <linux/io.h> 21 #include <linux/mutex.h> 22 23 unsigned long PCIBIOS_MIN_IO = 0x0000; 24 unsigned long PCIBIOS_MIN_MEM = 0; 25 26 /* 27 * The PCI controller list. 28 */ 29 static struct pci_channel *hose_head, **hose_tail = &hose_head; 30 31 static int pci_initialized; 32 33 static void __devinit pcibios_scanbus(struct pci_channel *hose) 34 { 35 static int next_busno; 36 static int need_domain_info; 37 struct pci_bus *bus; 38 39 bus = pci_scan_bus(next_busno, hose->pci_ops, hose); 40 hose->bus = bus; 41 42 need_domain_info = need_domain_info || hose->index; 43 hose->need_domain_info = need_domain_info; 44 if (bus) { 45 next_busno = bus->subordinate + 1; 46 /* Don't allow 8-bit bus number overflow inside the hose - 47 reserve some space for bridges. */ 48 if (next_busno > 224) { 49 next_busno = 0; 50 need_domain_info = 1; 51 } 52 53 pci_bus_size_bridges(bus); 54 pci_bus_assign_resources(bus); 55 pci_enable_bridges(bus); 56 } 57 } 58 59 static DEFINE_MUTEX(pci_scan_mutex); 60 61 void __devinit register_pci_controller(struct pci_channel *hose) 62 { 63 if (request_resource(&iomem_resource, hose->mem_resource) < 0) 64 goto out; 65 if (request_resource(&ioport_resource, hose->io_resource) < 0) { 66 release_resource(hose->mem_resource); 67 goto out; 68 } 69 70 *hose_tail = hose; 71 hose_tail = &hose->next; 72 73 /* 74 * Do not panic here but later - this might hapen before console init. 75 */ 76 if (!hose->io_map_base) { 77 printk(KERN_WARNING 78 "registering PCI controller with io_map_base unset\n"); 79 } 80 81 /* 82 * Scan the bus if it is register after the PCI subsystem 83 * initialization. 84 */ 85 if (pci_initialized) { 86 mutex_lock(&pci_scan_mutex); 87 pcibios_scanbus(hose); 88 mutex_unlock(&pci_scan_mutex); 89 } 90 91 out: 92 printk(KERN_WARNING "Skipping PCI bus scan due to resource conflict\n"); 93 } 94 95 static int __init pcibios_init(void) 96 { 97 struct pci_channel *hose; 98 99 /* Scan all of the recorded PCI controllers. */ 100 for (hose = hose_head; hose; hose = hose->next) 101 pcibios_scanbus(hose); 102 103 pci_fixup_irqs(pci_common_swizzle, pcibios_map_platform_irq); 104 105 dma_debug_add_bus(&pci_bus_type); 106 107 pci_initialized = 1; 108 109 return 0; 110 } 111 subsys_initcall(pcibios_init); 112 113 static void pcibios_fixup_device_resources(struct pci_dev *dev, 114 struct pci_bus *bus) 115 { 116 /* Update device resources. */ 117 struct pci_channel *hose = bus->sysdata; 118 unsigned long offset = 0; 119 int i; 120 121 for (i = 0; i < PCI_NUM_RESOURCES; i++) { 122 if (!dev->resource[i].start) 123 continue; 124 if (dev->resource[i].flags & IORESOURCE_PCI_FIXED) 125 continue; 126 if (dev->resource[i].flags & IORESOURCE_IO) 127 offset = hose->io_offset; 128 else if (dev->resource[i].flags & IORESOURCE_MEM) 129 offset = hose->mem_offset; 130 131 dev->resource[i].start += offset; 132 dev->resource[i].end += offset; 133 } 134 } 135 136 /* 137 * Called after each bus is probed, but before its children 138 * are examined. 139 */ 140 void __devinit pcibios_fixup_bus(struct pci_bus *bus) 141 { 142 struct pci_dev *dev = bus->self; 143 struct list_head *ln; 144 struct pci_channel *chan = bus->sysdata; 145 146 if (!dev) { 147 bus->resource[0] = chan->io_resource; 148 bus->resource[1] = chan->mem_resource; 149 } 150 151 for (ln = bus->devices.next; ln != &bus->devices; ln = ln->next) { 152 dev = pci_dev_b(ln); 153 154 if ((dev->class >> 8) != PCI_CLASS_BRIDGE_PCI) 155 pcibios_fixup_device_resources(dev, bus); 156 } 157 } 158 159 /* 160 * We need to avoid collisions with `mirrored' VGA ports 161 * and other strange ISA hardware, so we always want the 162 * addresses to be allocated in the 0x000-0x0ff region 163 * modulo 0x400. 164 */ 165 void pcibios_align_resource(void *data, struct resource *res, 166 resource_size_t size, resource_size_t align) 167 { 168 struct pci_dev *dev = data; 169 struct pci_channel *chan = dev->sysdata; 170 resource_size_t start = res->start; 171 172 if (res->flags & IORESOURCE_IO) { 173 if (start < PCIBIOS_MIN_IO + chan->io_resource->start) 174 start = PCIBIOS_MIN_IO + chan->io_resource->start; 175 176 /* 177 * Put everything into 0x00-0xff region modulo 0x400. 178 */ 179 if (start & 0x300) 180 start = (start + 0x3ff) & ~0x3ff; 181 } else if (res->flags & IORESOURCE_MEM) { 182 if (start < PCIBIOS_MIN_MEM + chan->mem_resource->start) 183 start = PCIBIOS_MIN_MEM + chan->mem_resource->start; 184 } 185 186 res->start = start; 187 } 188 189 void pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region, 190 struct resource *res) 191 { 192 struct pci_channel *hose = dev->sysdata; 193 unsigned long offset = 0; 194 195 if (res->flags & IORESOURCE_IO) 196 offset = hose->io_offset; 197 else if (res->flags & IORESOURCE_MEM) 198 offset = hose->mem_offset; 199 200 region->start = res->start - offset; 201 region->end = res->end - offset; 202 } 203 204 void __devinit 205 pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res, 206 struct pci_bus_region *region) 207 { 208 struct pci_channel *hose = dev->sysdata; 209 unsigned long offset = 0; 210 211 if (res->flags & IORESOURCE_IO) 212 offset = hose->io_offset; 213 else if (res->flags & IORESOURCE_MEM) 214 offset = hose->mem_offset; 215 216 res->start = region->start + offset; 217 res->end = region->end + offset; 218 } 219 220 int pcibios_enable_device(struct pci_dev *dev, int mask) 221 { 222 u16 cmd, old_cmd; 223 int idx; 224 struct resource *r; 225 226 pci_read_config_word(dev, PCI_COMMAND, &cmd); 227 old_cmd = cmd; 228 for (idx=0; idx < PCI_NUM_RESOURCES; idx++) { 229 /* Only set up the requested stuff */ 230 if (!(mask & (1<<idx))) 231 continue; 232 233 r = &dev->resource[idx]; 234 if (!(r->flags & (IORESOURCE_IO | IORESOURCE_MEM))) 235 continue; 236 if ((idx == PCI_ROM_RESOURCE) && 237 (!(r->flags & IORESOURCE_ROM_ENABLE))) 238 continue; 239 if (!r->start && r->end) { 240 printk(KERN_ERR "PCI: Device %s not available " 241 "because of resource collisions\n", 242 pci_name(dev)); 243 return -EINVAL; 244 } 245 if (r->flags & IORESOURCE_IO) 246 cmd |= PCI_COMMAND_IO; 247 if (r->flags & IORESOURCE_MEM) 248 cmd |= PCI_COMMAND_MEMORY; 249 } 250 if (cmd != old_cmd) { 251 printk("PCI: Enabling device %s (%04x -> %04x)\n", 252 pci_name(dev), old_cmd, cmd); 253 pci_write_config_word(dev, PCI_COMMAND, cmd); 254 } 255 return 0; 256 } 257 258 /* 259 * If we set up a device for bus mastering, we need to check and set 260 * the latency timer as it may not be properly set. 261 */ 262 static unsigned int pcibios_max_latency = 255; 263 264 void pcibios_set_master(struct pci_dev *dev) 265 { 266 u8 lat; 267 pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat); 268 if (lat < 16) 269 lat = (64 <= pcibios_max_latency) ? 64 : pcibios_max_latency; 270 else if (lat > pcibios_max_latency) 271 lat = pcibios_max_latency; 272 else 273 return; 274 printk(KERN_INFO "PCI: Setting latency timer of device %s to %d\n", 275 pci_name(dev), lat); 276 pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat); 277 } 278 279 void __init pcibios_update_irq(struct pci_dev *dev, int irq) 280 { 281 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq); 282 } 283 284 char * __devinit pcibios_setup(char *str) 285 { 286 return str; 287 } 288 289 int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma, 290 enum pci_mmap_state mmap_state, int write_combine) 291 { 292 /* 293 * I/O space can be accessed via normal processor loads and stores on 294 * this platform but for now we elect not to do this and portable 295 * drivers should not do this anyway. 296 */ 297 if (mmap_state == pci_mmap_io) 298 return -EINVAL; 299 300 /* 301 * Ignore write-combine; for now only return uncached mappings. 302 */ 303 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); 304 305 return remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff, 306 vma->vm_end - vma->vm_start, 307 vma->vm_page_prot); 308 } 309 310 #ifndef CONFIG_GENERIC_IOMAP 311 312 static void __iomem *ioport_map_pci(struct pci_dev *dev, 313 unsigned long port, unsigned int nr) 314 { 315 struct pci_channel *chan = dev->sysdata; 316 317 if (unlikely(!chan->io_map_base)) { 318 chan->io_map_base = generic_io_base; 319 320 if (pci_domains_supported) 321 panic("To avoid data corruption io_map_base MUST be " 322 "set with multiple PCI domains."); 323 } 324 325 326 return (void __iomem *)(chan->io_map_base + port); 327 } 328 329 void __iomem *pci_iomap(struct pci_dev *dev, int bar, unsigned long maxlen) 330 { 331 resource_size_t start = pci_resource_start(dev, bar); 332 resource_size_t len = pci_resource_len(dev, bar); 333 unsigned long flags = pci_resource_flags(dev, bar); 334 335 if (unlikely(!len || !start)) 336 return NULL; 337 if (maxlen && len > maxlen) 338 len = maxlen; 339 340 if (flags & IORESOURCE_IO) 341 return ioport_map_pci(dev, start, len); 342 if (flags & IORESOURCE_MEM) { 343 if (flags & IORESOURCE_CACHEABLE) 344 return ioremap(start, len); 345 return ioremap_nocache(start, len); 346 } 347 348 return NULL; 349 } 350 EXPORT_SYMBOL(pci_iomap); 351 352 void pci_iounmap(struct pci_dev *dev, void __iomem *addr) 353 { 354 iounmap(addr); 355 } 356 EXPORT_SYMBOL(pci_iounmap); 357 358 #endif /* CONFIG_GENERIC_IOMAP */ 359 360 #ifdef CONFIG_HOTPLUG 361 EXPORT_SYMBOL(pcibios_resource_to_bus); 362 EXPORT_SYMBOL(pcibios_bus_to_resource); 363 EXPORT_SYMBOL(PCIBIOS_MIN_IO); 364 EXPORT_SYMBOL(PCIBIOS_MIN_MEM); 365 #endif 366