1*ff4a7481SKuninori Morimoto /* SPDX-License-Identifier: GPL-2.0 2*ff4a7481SKuninori Morimoto * 35283ecb5SPaul Mundt * Low-Level PCI Support for SH7780 targets 45283ecb5SPaul Mundt * 55283ecb5SPaul Mundt * Dustin McIntire (dustin@sensoria.com) (c) 2001 65283ecb5SPaul Mundt * Paul Mundt (lethal@linux-sh.org) (c) 2003 75283ecb5SPaul Mundt */ 85283ecb5SPaul Mundt 95283ecb5SPaul Mundt #ifndef _PCI_SH7780_H_ 105283ecb5SPaul Mundt #define _PCI_SH7780_H_ 115283ecb5SPaul Mundt 125283ecb5SPaul Mundt /* SH7780 Control Registers */ 134e7b7fdbSPaul Mundt #define PCIECR 0xFE000008 144e7b7fdbSPaul Mundt #define PCIECR_ENBL 0x01 155283ecb5SPaul Mundt 165283ecb5SPaul Mundt /* SH7780 Specific Values */ 175283ecb5SPaul Mundt #define SH7780_PCI_CONFIG_BASE 0xFD000000 /* Config space base addr */ 185283ecb5SPaul Mundt #define SH7780_PCI_CONFIG_SIZE 0x01000000 /* Config space size */ 19959f85f8SPaul Mundt 205283ecb5SPaul Mundt #define SH7780_PCIREG_BASE 0xFE040000 /* PCI regs base address */ 215283ecb5SPaul Mundt 225283ecb5SPaul Mundt /* SH7780 PCI Config Registers */ 23b7576230SNobuhiro Iwamatsu #define SH7780_PCIIR 0x114 /* PCI Interrupt Register */ 24b7576230SNobuhiro Iwamatsu #define SH7780_PCIIMR 0x118 /* PCI Interrupt Mask Register */ 25b7576230SNobuhiro Iwamatsu #define SH7780_PCIAIR 0x11C /* Error Address Register */ 26b7576230SNobuhiro Iwamatsu #define SH7780_PCICIR 0x120 /* Error Command/Data Register */ 27b7576230SNobuhiro Iwamatsu #define SH7780_PCIAINT 0x130 /* Arbiter Interrupt Register */ 28b7576230SNobuhiro Iwamatsu #define SH7780_PCIAINTM 0x134 /* Arbiter Int. Mask Register */ 29b7576230SNobuhiro Iwamatsu #define SH7780_PCIBMIR 0x138 /* Error Bus Master Register */ 30b7576230SNobuhiro Iwamatsu #define SH7780_PCIPAR 0x1C0 /* PIO Address Register */ 31b7576230SNobuhiro Iwamatsu #define SH7780_PCIPINT 0x1CC /* Power Mgmnt Int. Register */ 32b7576230SNobuhiro Iwamatsu #define SH7780_PCIPINTM 0x1D0 /* Power Mgmnt Mask Register */ 33b7576230SNobuhiro Iwamatsu 34b6c58b1dSPaul Mundt #define SH7780_PCIMBR(x) (0x1E0 + ((x) * 8)) 35b6c58b1dSPaul Mundt #define SH7780_PCIMBMR(x) (0x1E4 + ((x) * 8)) 36959f85f8SPaul Mundt #define SH7780_PCIIOBR 0x1F8 37959f85f8SPaul Mundt #define SH7780_PCIIOBMR 0x1FC 385283ecb5SPaul Mundt #define SH7780_PCICSCR0 0x210 /* Cache Snoop1 Cnt. Register */ 395283ecb5SPaul Mundt #define SH7780_PCICSCR1 0x214 /* Cache Snoop2 Cnt. Register */ 405283ecb5SPaul Mundt #define SH7780_PCICSAR0 0x218 /* Cache Snoop1 Addr. Register */ 415283ecb5SPaul Mundt #define SH7780_PCICSAR1 0x21C /* Cache Snoop2 Addr. Register */ 425283ecb5SPaul Mundt 435283ecb5SPaul Mundt #endif /* _PCI_SH7780_H_ */ 44