1 /* 2 * Low-Level PCI Support for the SH7780 3 * 4 * Copyright (C) 2005 - 2010 Paul Mundt 5 * 6 * This file is subject to the terms and conditions of the GNU General Public 7 * License. See the file "COPYING" in the main directory of this archive 8 * for more details. 9 */ 10 #include <linux/types.h> 11 #include <linux/kernel.h> 12 #include <linux/init.h> 13 #include <linux/pci.h> 14 #include <linux/errno.h> 15 #include <linux/delay.h> 16 #include <linux/log2.h> 17 #include "pci-sh4.h" 18 #include <asm/mmu.h> 19 #include <asm/sizes.h> 20 21 static struct resource sh7785_io_resource = { 22 .name = "SH7785_IO", 23 .start = 0x1000, 24 .end = SH7780_PCI_IO_SIZE - 1, 25 .flags = IORESOURCE_IO 26 }; 27 28 static struct resource sh7785_mem_resource = { 29 .name = "SH7785_mem", 30 .start = SH7780_PCI_MEMORY_BASE, 31 .end = SH7780_PCI_MEMORY_BASE + SH7780_PCI_MEM_SIZE - 1, 32 .flags = IORESOURCE_MEM 33 }; 34 35 static struct pci_channel sh7780_pci_controller = { 36 .pci_ops = &sh4_pci_ops, 37 .mem_resource = &sh7785_mem_resource, 38 .mem_offset = 0x00000000, 39 .io_resource = &sh7785_io_resource, 40 .io_offset = 0x00000000, 41 .io_map_base = SH7780_PCI_IO_BASE, 42 }; 43 44 static void __init sh7780_pci66_init(struct pci_channel *hose) 45 { 46 unsigned int tmp; 47 48 if (!pci_is_66mhz_capable(hose, 0, 0)) 49 return; 50 51 /* Enable register access */ 52 tmp = __raw_readl(hose->reg_base + SH4_PCICR); 53 tmp |= SH4_PCICR_PREFIX; 54 __raw_writel(tmp, hose->reg_base + SH4_PCICR); 55 56 /* Enable 66MHz operation */ 57 tmp = __raw_readw(hose->reg_base + PCI_STATUS); 58 tmp |= PCI_STATUS_66MHZ; 59 __raw_writew(tmp, hose->reg_base + PCI_STATUS); 60 61 /* Done */ 62 tmp = __raw_readl(hose->reg_base + SH4_PCICR); 63 tmp |= SH4_PCICR_PREFIX | SH4_PCICR_CFIN; 64 __raw_writel(tmp, hose->reg_base + SH4_PCICR); 65 } 66 67 static int __init sh7780_pci_init(void) 68 { 69 struct pci_channel *chan = &sh7780_pci_controller; 70 phys_addr_t memphys; 71 size_t memsize; 72 unsigned int id; 73 const char *type; 74 75 printk(KERN_NOTICE "PCI: Starting intialization.\n"); 76 77 chan->reg_base = 0xfe040000; 78 79 /* Enable CPU access to the PCIC registers. */ 80 __raw_writel(PCIECR_ENBL, PCIECR); 81 82 /* Reset */ 83 __raw_writel(SH4_PCICR_PREFIX | SH4_PCICR_PRST, 84 chan->reg_base + SH4_PCICR); 85 86 /* 87 * Wait for it to come back up. The spec says to allow for up to 88 * 1 second after toggling the reset pin, but in practice 100ms 89 * is more than enough. 90 */ 91 mdelay(100); 92 93 id = __raw_readw(chan->reg_base + PCI_VENDOR_ID); 94 if (id != PCI_VENDOR_ID_RENESAS) { 95 printk(KERN_ERR "PCI: Unknown vendor ID 0x%04x.\n", id); 96 return -ENODEV; 97 } 98 99 id = __raw_readw(chan->reg_base + PCI_DEVICE_ID); 100 type = (id == PCI_DEVICE_ID_RENESAS_SH7763) ? "SH7763" : 101 (id == PCI_DEVICE_ID_RENESAS_SH7780) ? "SH7780" : 102 (id == PCI_DEVICE_ID_RENESAS_SH7781) ? "SH7781" : 103 (id == PCI_DEVICE_ID_RENESAS_SH7785) ? "SH7785" : 104 NULL; 105 if (unlikely(!type)) { 106 printk(KERN_ERR "PCI: Found an unsupported Renesas host " 107 "controller, device id 0x%04x.\n", id); 108 return -EINVAL; 109 } 110 111 printk(KERN_NOTICE "PCI: Found a Renesas %s host " 112 "controller, revision %d.\n", type, 113 __raw_readb(chan->reg_base + PCI_REVISION_ID)); 114 115 /* 116 * Now throw it in to register initialization mode and 117 * start the real work. 118 */ 119 __raw_writel(SH4_PCICR_PREFIX, chan->reg_base + SH4_PCICR); 120 121 __raw_writel(0, chan->reg_base + PCI_BASE_ADDRESS_0); 122 123 memphys = __pa(memory_start); 124 memsize = roundup_pow_of_two(memory_end - memory_start); 125 126 /* 127 * If there's more than 512MB of memory, we need to roll over to 128 * LAR1/LSR1. 129 */ 130 if (memsize > SZ_512M) { 131 __raw_writel(memphys + SZ_512M, chan->reg_base + SH4_PCILAR1); 132 __raw_writel((((memsize - SZ_512M) - SZ_1M) & 0x1ff00000) | 1, 133 chan->reg_base + SH4_PCILSR1); 134 memsize = SZ_512M; 135 } else { 136 /* 137 * Otherwise just zero it out and disable it. 138 */ 139 __raw_writel(0, chan->reg_base + SH4_PCILAR1); 140 __raw_writel(0, chan->reg_base + SH4_PCILSR1); 141 } 142 143 /* 144 * LAR0/LSR0 covers up to the first 512MB, which is enough to 145 * cover all of lowmem on most platforms. 146 */ 147 __raw_writel(memphys, chan->reg_base + SH4_PCILAR0); 148 __raw_writel(((memsize - SZ_1M) & 0x1ff00000) | 1, 149 chan->reg_base + SH4_PCILSR0); 150 151 /* Clear out PCI arbiter IRQs */ 152 __raw_writel(0, chan->reg_base + SH4_PCIAINT); 153 154 /* Unmask all of the arbiter IRQs. */ 155 __raw_writel(SH4_PCIAINT_MBKN | SH4_PCIAINT_TBTO | SH4_PCIAINT_MBTO | \ 156 SH4_PCIAINT_TABT | SH4_PCIAINT_MABT | SH4_PCIAINT_RDPE | \ 157 SH4_PCIAINT_WDPE, chan->reg_base + SH4_PCIAINTM); 158 159 /* Clear all error conditions */ 160 __raw_writew(PCI_STATUS_DETECTED_PARITY | \ 161 PCI_STATUS_SIG_SYSTEM_ERROR | \ 162 PCI_STATUS_REC_MASTER_ABORT | \ 163 PCI_STATUS_REC_TARGET_ABORT | \ 164 PCI_STATUS_SIG_TARGET_ABORT | \ 165 PCI_STATUS_PARITY, chan->reg_base + PCI_STATUS); 166 167 __raw_writew(PCI_COMMAND_SERR | PCI_COMMAND_WAIT | \ 168 PCI_COMMAND_PARITY | PCI_COMMAND_MASTER | \ 169 PCI_COMMAND_MEMORY, chan->reg_base + PCI_COMMAND); 170 171 /* Unmask all of the PCI IRQs */ 172 __raw_writel(SH4_PCIINTM_TTADIM | SH4_PCIINTM_TMTOIM | \ 173 SH4_PCIINTM_MDEIM | SH4_PCIINTM_APEDIM | \ 174 SH4_PCIINTM_SDIM | SH4_PCIINTM_DPEITWM | \ 175 SH4_PCIINTM_PEDITRM | SH4_PCIINTM_TADIMM | \ 176 SH4_PCIINTM_MADIMM | SH4_PCIINTM_MWPDIM | \ 177 SH4_PCIINTM_MRDPEIM, chan->reg_base + SH4_PCIINTM); 178 179 /* 180 * Disable the cache snoop controller for non-coherent DMA. 181 */ 182 __raw_writel(0, chan->reg_base + SH7780_PCICSCR0); 183 __raw_writel(0, chan->reg_base + SH7780_PCICSAR0); 184 __raw_writel(0, chan->reg_base + SH7780_PCICSCR1); 185 __raw_writel(0, chan->reg_base + SH7780_PCICSAR1); 186 187 __raw_writel(0xfd000000, chan->reg_base + SH7780_PCIMBR0); 188 __raw_writel(0x00fc0000, chan->reg_base + SH7780_PCIMBMR0); 189 190 __raw_writel(0, chan->reg_base + SH7780_PCIIOBR); 191 __raw_writel(0, chan->reg_base + SH7780_PCIIOBMR); 192 193 /* 194 * Initialization mode complete, release the control register and 195 * enable round robin mode to stop device overruns/starvation. 196 */ 197 __raw_writel(SH4_PCICR_PREFIX | SH4_PCICR_CFIN | SH4_PCICR_FTO, 198 chan->reg_base + SH4_PCICR); 199 200 register_pci_controller(chan); 201 202 sh7780_pci66_init(chan); 203 204 printk(KERN_NOTICE "PCI: Running at %dMHz.\n", 205 (__raw_readw(chan->reg_base + PCI_STATUS) & PCI_STATUS_66MHZ) ? 206 66 : 33); 207 208 return 0; 209 } 210 arch_initcall(sh7780_pci_init); 211