1aaf9128aSKuninori Morimoto // SPDX-License-Identifier: GPL-2.0
202bf6cc7SPaul Mundt /*
302bf6cc7SPaul Mundt * Renesas Technology Europe SDK7786 Support.
402bf6cc7SPaul Mundt *
502bf6cc7SPaul Mundt * Copyright (C) 2010 Matt Fleming
602bf6cc7SPaul Mundt * Copyright (C) 2010 Paul Mundt
702bf6cc7SPaul Mundt */
802bf6cc7SPaul Mundt #include <linux/init.h>
902bf6cc7SPaul Mundt #include <linux/platform_device.h>
1002bf6cc7SPaul Mundt #include <linux/io.h>
112fcfe22aSGuennadi Liakhovetski #include <linux/regulator/fixed.h>
122fcfe22aSGuennadi Liakhovetski #include <linux/regulator/machine.h>
1302bf6cc7SPaul Mundt #include <linux/smsc911x.h>
1402bf6cc7SPaul Mundt #include <linux/i2c.h>
1502bf6cc7SPaul Mundt #include <linux/irq.h>
16c8098218SPaul Mundt #include <linux/clk.h>
173bd75e5eSPaul Mundt #include <linux/clkdev.h>
185f240718SPaul Mundt #include <mach/fpga.h>
195f240718SPaul Mundt #include <mach/irq.h>
2002bf6cc7SPaul Mundt #include <asm/machvec.h>
212267c787SPaul Mundt #include <asm/heartbeat.h>
22*87dfb311SMasahiro Yamada #include <linux/sizes.h>
23b6b77b2dSPaul Mundt #include <asm/clock.h>
24b51989b8SPaul Mundt #include <asm/reboot.h>
253366e358SPaul Mundt #include <asm/smp-ops.h>
2602bf6cc7SPaul Mundt
272267c787SPaul Mundt static struct resource heartbeat_resource = {
282267c787SPaul Mundt .start = 0x07fff8b0,
292267c787SPaul Mundt .end = 0x07fff8b0 + sizeof(u16) - 1,
302267c787SPaul Mundt .flags = IORESOURCE_MEM | IORESOURCE_MEM_16BIT,
312267c787SPaul Mundt };
322267c787SPaul Mundt
332267c787SPaul Mundt static struct platform_device heartbeat_device = {
342267c787SPaul Mundt .name = "heartbeat",
352267c787SPaul Mundt .id = -1,
362267c787SPaul Mundt .num_resources = 1,
372267c787SPaul Mundt .resource = &heartbeat_resource,
382267c787SPaul Mundt };
392267c787SPaul Mundt
402fcfe22aSGuennadi Liakhovetski /* Dummy supplies, where voltage doesn't matter */
412fcfe22aSGuennadi Liakhovetski static struct regulator_consumer_supply dummy_supplies[] = {
422fcfe22aSGuennadi Liakhovetski REGULATOR_SUPPLY("vddvario", "smsc911x"),
432fcfe22aSGuennadi Liakhovetski REGULATOR_SUPPLY("vdd33a", "smsc911x"),
442fcfe22aSGuennadi Liakhovetski };
452fcfe22aSGuennadi Liakhovetski
4602bf6cc7SPaul Mundt static struct resource smsc911x_resources[] = {
4702bf6cc7SPaul Mundt [0] = {
4802bf6cc7SPaul Mundt .name = "smsc911x-memory",
4902bf6cc7SPaul Mundt .start = 0x07ffff00,
5002bf6cc7SPaul Mundt .end = 0x07ffff00 + SZ_256 - 1,
5102bf6cc7SPaul Mundt .flags = IORESOURCE_MEM,
5202bf6cc7SPaul Mundt },
5302bf6cc7SPaul Mundt [1] = {
5402bf6cc7SPaul Mundt .name = "smsc911x-irq",
5502bf6cc7SPaul Mundt .start = evt2irq(0x2c0),
5602bf6cc7SPaul Mundt .end = evt2irq(0x2c0),
5702bf6cc7SPaul Mundt .flags = IORESOURCE_IRQ,
5802bf6cc7SPaul Mundt },
5902bf6cc7SPaul Mundt };
6002bf6cc7SPaul Mundt
6102bf6cc7SPaul Mundt static struct smsc911x_platform_config smsc911x_config = {
6202bf6cc7SPaul Mundt .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
6302bf6cc7SPaul Mundt .irq_type = SMSC911X_IRQ_TYPE_OPEN_DRAIN,
6402bf6cc7SPaul Mundt .flags = SMSC911X_USE_32BIT,
6502bf6cc7SPaul Mundt .phy_interface = PHY_INTERFACE_MODE_MII,
6602bf6cc7SPaul Mundt };
6702bf6cc7SPaul Mundt
6802bf6cc7SPaul Mundt static struct platform_device smsc911x_device = {
6902bf6cc7SPaul Mundt .name = "smsc911x",
7002bf6cc7SPaul Mundt .id = -1,
7102bf6cc7SPaul Mundt .num_resources = ARRAY_SIZE(smsc911x_resources),
7202bf6cc7SPaul Mundt .resource = smsc911x_resources,
7302bf6cc7SPaul Mundt .dev = {
7402bf6cc7SPaul Mundt .platform_data = &smsc911x_config,
7502bf6cc7SPaul Mundt },
7602bf6cc7SPaul Mundt };
7702bf6cc7SPaul Mundt
7802bf6cc7SPaul Mundt static struct resource smbus_fpga_resource = {
7902bf6cc7SPaul Mundt .start = 0x07fff9e0,
8002bf6cc7SPaul Mundt .end = 0x07fff9e0 + SZ_32 - 1,
8102bf6cc7SPaul Mundt .flags = IORESOURCE_MEM,
8202bf6cc7SPaul Mundt };
8302bf6cc7SPaul Mundt
8402bf6cc7SPaul Mundt static struct platform_device smbus_fpga_device = {
8502bf6cc7SPaul Mundt .name = "i2c-sdk7786",
8602bf6cc7SPaul Mundt .id = 0,
8702bf6cc7SPaul Mundt .num_resources = 1,
8802bf6cc7SPaul Mundt .resource = &smbus_fpga_resource,
8902bf6cc7SPaul Mundt };
9002bf6cc7SPaul Mundt
9102bf6cc7SPaul Mundt static struct resource smbus_pcie_resource = {
9202bf6cc7SPaul Mundt .start = 0x07fffc30,
9302bf6cc7SPaul Mundt .end = 0x07fffc30 + SZ_32 - 1,
9402bf6cc7SPaul Mundt .flags = IORESOURCE_MEM,
9502bf6cc7SPaul Mundt };
9602bf6cc7SPaul Mundt
9702bf6cc7SPaul Mundt static struct platform_device smbus_pcie_device = {
9802bf6cc7SPaul Mundt .name = "i2c-sdk7786",
9902bf6cc7SPaul Mundt .id = 1,
10002bf6cc7SPaul Mundt .num_resources = 1,
10102bf6cc7SPaul Mundt .resource = &smbus_pcie_resource,
10202bf6cc7SPaul Mundt };
10302bf6cc7SPaul Mundt
10402bf6cc7SPaul Mundt static struct i2c_board_info __initdata sdk7786_i2c_devices[] = {
10502bf6cc7SPaul Mundt {
10602bf6cc7SPaul Mundt I2C_BOARD_INFO("max6900", 0x68),
10702bf6cc7SPaul Mundt },
10802bf6cc7SPaul Mundt };
10902bf6cc7SPaul Mundt
11002bf6cc7SPaul Mundt static struct platform_device *sh7786_devices[] __initdata = {
1112267c787SPaul Mundt &heartbeat_device,
11202bf6cc7SPaul Mundt &smsc911x_device,
11302bf6cc7SPaul Mundt &smbus_fpga_device,
11402bf6cc7SPaul Mundt &smbus_pcie_device,
11502bf6cc7SPaul Mundt };
11602bf6cc7SPaul Mundt
sdk7786_i2c_setup(void)11702bf6cc7SPaul Mundt static int sdk7786_i2c_setup(void)
11802bf6cc7SPaul Mundt {
11902bf6cc7SPaul Mundt unsigned int tmp;
12002bf6cc7SPaul Mundt
12102bf6cc7SPaul Mundt /*
12202bf6cc7SPaul Mundt * Hand over I2C control to the FPGA.
12302bf6cc7SPaul Mundt */
124efd590d5SPaul Mundt tmp = fpga_read_reg(SBCR);
12502bf6cc7SPaul Mundt tmp &= ~SCBR_I2CCEN;
12602bf6cc7SPaul Mundt tmp |= SCBR_I2CMEN;
127efd590d5SPaul Mundt fpga_write_reg(tmp, SBCR);
12802bf6cc7SPaul Mundt
12902bf6cc7SPaul Mundt return i2c_register_board_info(0, sdk7786_i2c_devices,
13002bf6cc7SPaul Mundt ARRAY_SIZE(sdk7786_i2c_devices));
13102bf6cc7SPaul Mundt }
13202bf6cc7SPaul Mundt
sdk7786_devices_setup(void)13302bf6cc7SPaul Mundt static int __init sdk7786_devices_setup(void)
13402bf6cc7SPaul Mundt {
13502bf6cc7SPaul Mundt int ret;
13602bf6cc7SPaul Mundt
13702bf6cc7SPaul Mundt ret = platform_add_devices(sh7786_devices, ARRAY_SIZE(sh7786_devices));
13802bf6cc7SPaul Mundt if (unlikely(ret != 0))
13902bf6cc7SPaul Mundt return ret;
14002bf6cc7SPaul Mundt
14102bf6cc7SPaul Mundt return sdk7786_i2c_setup();
14202bf6cc7SPaul Mundt }
14395d210ceSNobuhiro Iwamatsu device_initcall(sdk7786_devices_setup);
14402bf6cc7SPaul Mundt
sdk7786_mode_pins(void)1456f832e8aSPaul Mundt static int sdk7786_mode_pins(void)
1466f832e8aSPaul Mundt {
147efd590d5SPaul Mundt return fpga_read_reg(MODSWR);
1486f832e8aSPaul Mundt }
1496f832e8aSPaul Mundt
150b6b77b2dSPaul Mundt /*
151b6b77b2dSPaul Mundt * FPGA-driven PCIe clocks
152b6b77b2dSPaul Mundt *
153b6b77b2dSPaul Mundt * Historically these include the oscillator, clock B (slots 2/3/4) and
154b6b77b2dSPaul Mundt * clock A (slot 1 and the CPU clock). Newer revs of the PCB shove
155b6b77b2dSPaul Mundt * everything under a single PCIe clocks enable bit that happens to map
156b6b77b2dSPaul Mundt * to the same bit position as the oscillator bit for earlier FPGA
157b6b77b2dSPaul Mundt * versions.
158b6b77b2dSPaul Mundt *
159b6b77b2dSPaul Mundt * Given that the legacy clocks have the side-effect of shutting the CPU
160b6b77b2dSPaul Mundt * off through the FPGA along with the PCI slots, we simply leave them in
161b6b77b2dSPaul Mundt * their initial state and don't bother registering them with the clock
162b6b77b2dSPaul Mundt * framework.
163b6b77b2dSPaul Mundt */
sdk7786_pcie_clk_enable(struct clk * clk)164b6b77b2dSPaul Mundt static int sdk7786_pcie_clk_enable(struct clk *clk)
165b6b77b2dSPaul Mundt {
166b6b77b2dSPaul Mundt fpga_write_reg(fpga_read_reg(PCIECR) | PCIECR_CLKEN, PCIECR);
167b6b77b2dSPaul Mundt return 0;
168b6b77b2dSPaul Mundt }
169b6b77b2dSPaul Mundt
sdk7786_pcie_clk_disable(struct clk * clk)170b6b77b2dSPaul Mundt static void sdk7786_pcie_clk_disable(struct clk *clk)
171b6b77b2dSPaul Mundt {
172b6b77b2dSPaul Mundt fpga_write_reg(fpga_read_reg(PCIECR) & ~PCIECR_CLKEN, PCIECR);
173b6b77b2dSPaul Mundt }
174b6b77b2dSPaul Mundt
175c953efdbSMagnus Damm static struct sh_clk_ops sdk7786_pcie_clk_ops = {
176b6b77b2dSPaul Mundt .enable = sdk7786_pcie_clk_enable,
177b6b77b2dSPaul Mundt .disable = sdk7786_pcie_clk_disable,
178b6b77b2dSPaul Mundt };
179b6b77b2dSPaul Mundt
180b6b77b2dSPaul Mundt static struct clk sdk7786_pcie_clk = {
181b6b77b2dSPaul Mundt .ops = &sdk7786_pcie_clk_ops,
182b6b77b2dSPaul Mundt };
183b6b77b2dSPaul Mundt
184b6b77b2dSPaul Mundt static struct clk_lookup sdk7786_pcie_cl = {
185b6b77b2dSPaul Mundt .con_id = "pcie_plat_clk",
186b6b77b2dSPaul Mundt .clk = &sdk7786_pcie_clk,
187b6b77b2dSPaul Mundt };
188b6b77b2dSPaul Mundt
sdk7786_clk_init(void)189c8098218SPaul Mundt static int sdk7786_clk_init(void)
190c8098218SPaul Mundt {
191c8098218SPaul Mundt struct clk *clk;
192c8098218SPaul Mundt int ret;
193c8098218SPaul Mundt
194c8098218SPaul Mundt /*
195c8098218SPaul Mundt * Only handle the EXTAL case, anyone interfacing a crystal
196c8098218SPaul Mundt * resonator will need to provide their own input clock.
197c8098218SPaul Mundt */
198c8098218SPaul Mundt if (test_mode_pin(MODE_PIN9))
199c8098218SPaul Mundt return -EINVAL;
200c8098218SPaul Mundt
201c8098218SPaul Mundt clk = clk_get(NULL, "extal");
2027912825dSPaul Mundt if (IS_ERR(clk))
203c8098218SPaul Mundt return PTR_ERR(clk);
204c8098218SPaul Mundt ret = clk_set_rate(clk, 33333333);
205c8098218SPaul Mundt clk_put(clk);
206c8098218SPaul Mundt
207b6b77b2dSPaul Mundt /*
208b6b77b2dSPaul Mundt * Setup the FPGA clocks.
209b6b77b2dSPaul Mundt */
210b6b77b2dSPaul Mundt ret = clk_register(&sdk7786_pcie_clk);
211b6b77b2dSPaul Mundt if (unlikely(ret)) {
212b6b77b2dSPaul Mundt pr_err("FPGA clock registration failed\n");
213c8098218SPaul Mundt return ret;
214c8098218SPaul Mundt }
215c8098218SPaul Mundt
216b6b77b2dSPaul Mundt clkdev_add(&sdk7786_pcie_cl);
217b6b77b2dSPaul Mundt
218b6b77b2dSPaul Mundt return 0;
219b6b77b2dSPaul Mundt }
220b6b77b2dSPaul Mundt
sdk7786_restart(char * cmd)221b51989b8SPaul Mundt static void sdk7786_restart(char *cmd)
222b51989b8SPaul Mundt {
223b51989b8SPaul Mundt fpga_write_reg(0xa5a5, SRSTR);
224b51989b8SPaul Mundt }
225b51989b8SPaul Mundt
sdk7786_power_off(void)226d9c94446SPaul Mundt static void sdk7786_power_off(void)
227d9c94446SPaul Mundt {
228d9c94446SPaul Mundt fpga_write_reg(fpga_read_reg(PWRCR) | PWRCR_PDWNREQ, PWRCR);
229d9c94446SPaul Mundt
230d9c94446SPaul Mundt /*
231d9c94446SPaul Mundt * It can take up to 20us for the R8C to do its job, back off and
232d9c94446SPaul Mundt * wait a bit until we've been shut off. Even though newer FPGA
233d9c94446SPaul Mundt * versions don't set the ACK bit, the latency issue remains.
234d9c94446SPaul Mundt */
235d9c94446SPaul Mundt while ((fpga_read_reg(PWRCR) & PWRCR_PDWNACK) == 0)
236d9c94446SPaul Mundt cpu_sleep();
237d9c94446SPaul Mundt }
238d9c94446SPaul Mundt
23902bf6cc7SPaul Mundt /* Initialize the board */
sdk7786_setup(char ** cmdline_p)24002bf6cc7SPaul Mundt static void __init sdk7786_setup(char **cmdline_p)
24102bf6cc7SPaul Mundt {
242efd590d5SPaul Mundt pr_info("Renesas Technology Europe SDK7786 support:\n");
243efd590d5SPaul Mundt
2442fcfe22aSGuennadi Liakhovetski regulator_register_fixed(0, dummy_supplies, ARRAY_SIZE(dummy_supplies));
2452fcfe22aSGuennadi Liakhovetski
246efd590d5SPaul Mundt sdk7786_fpga_init();
24776496f8fSPaul Mundt sdk7786_nmi_init();
248efd590d5SPaul Mundt
249efd590d5SPaul Mundt pr_info("\tPCB revision:\t%d\n", fpga_read_reg(PCBRR) & 0xf);
250b51989b8SPaul Mundt
251b51989b8SPaul Mundt machine_ops.restart = sdk7786_restart;
252d9c94446SPaul Mundt pm_power_off = sdk7786_power_off;
2533366e358SPaul Mundt
2543366e358SPaul Mundt register_smp_ops(&shx3_smp_ops);
25502bf6cc7SPaul Mundt }
25602bf6cc7SPaul Mundt
25702bf6cc7SPaul Mundt /*
25802bf6cc7SPaul Mundt * The Machine Vector
25902bf6cc7SPaul Mundt */
26002bf6cc7SPaul Mundt static struct sh_machine_vector mv_sdk7786 __initmv = {
26102bf6cc7SPaul Mundt .mv_name = "SDK7786",
26202bf6cc7SPaul Mundt .mv_setup = sdk7786_setup,
2636f832e8aSPaul Mundt .mv_mode_pins = sdk7786_mode_pins,
264c8098218SPaul Mundt .mv_clk_init = sdk7786_clk_init,
2655f240718SPaul Mundt .mv_init_irq = sdk7786_init_irq,
26602bf6cc7SPaul Mundt };
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