1 /* 2 * Renesas System Solutions Asia Pte. Ltd - Migo-R 3 * 4 * Copyright (C) 2008 Magnus Damm 5 * 6 * This file is subject to the terms and conditions of the GNU General Public 7 * License. See the file "COPYING" in the main directory of this archive 8 * for more details. 9 */ 10 #include <linux/init.h> 11 #include <linux/platform_device.h> 12 #include <linux/interrupt.h> 13 #include <linux/input.h> 14 #include <linux/input/sh_keysc.h> 15 #include <linux/mmc/host.h> 16 #include <linux/mmc/sh_mobile_sdhi.h> 17 #include <linux/mtd/physmap.h> 18 #include <linux/mtd/nand.h> 19 #include <linux/i2c.h> 20 #include <linux/smc91x.h> 21 #include <linux/delay.h> 22 #include <linux/clk.h> 23 #include <linux/gpio.h> 24 #include <linux/videodev2.h> 25 #include <linux/sh_intc.h> 26 #include <video/sh_mobile_lcdc.h> 27 #include <media/sh_mobile_ceu.h> 28 #include <media/ov772x.h> 29 #include <media/soc_camera.h> 30 #include <media/tw9910.h> 31 #include <asm/clock.h> 32 #include <asm/machvec.h> 33 #include <asm/io.h> 34 #include <asm/suspend.h> 35 #include <mach/migor.h> 36 #include <cpu/sh7722.h> 37 38 /* Address IRQ Size Bus Description 39 * 0x00000000 64MB 16 NOR Flash (SP29PL256N) 40 * 0x0c000000 64MB 64 SDRAM (2xK4M563233G) 41 * 0x10000000 IRQ0 16 Ethernet (SMC91C111) 42 * 0x14000000 IRQ4 16 USB 2.0 Host Controller (M66596) 43 * 0x18000000 8GB 8 NAND Flash (K9K8G08U0A) 44 */ 45 46 static struct smc91x_platdata smc91x_info = { 47 .flags = SMC91X_USE_16BIT | SMC91X_NOWAIT, 48 }; 49 50 static struct resource smc91x_eth_resources[] = { 51 [0] = { 52 .name = "SMC91C111" , 53 .start = 0x10000300, 54 .end = 0x1000030f, 55 .flags = IORESOURCE_MEM, 56 }, 57 [1] = { 58 .start = evt2irq(0x600), /* IRQ0 */ 59 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, 60 }, 61 }; 62 63 static struct platform_device smc91x_eth_device = { 64 .name = "smc91x", 65 .num_resources = ARRAY_SIZE(smc91x_eth_resources), 66 .resource = smc91x_eth_resources, 67 .dev = { 68 .platform_data = &smc91x_info, 69 }, 70 }; 71 72 static struct sh_keysc_info sh_keysc_info = { 73 .mode = SH_KEYSC_MODE_2, /* KEYOUT0->4, KEYIN1->5 */ 74 .scan_timing = 3, 75 .delay = 5, 76 .keycodes = { 77 0, KEY_UP, KEY_DOWN, KEY_LEFT, KEY_RIGHT, KEY_ENTER, 78 0, KEY_F, KEY_C, KEY_D, KEY_H, KEY_1, 79 0, KEY_2, KEY_3, KEY_4, KEY_5, KEY_6, 80 0, KEY_7, KEY_8, KEY_9, KEY_S, KEY_0, 81 0, KEY_P, KEY_STOP, KEY_REWIND, KEY_PLAY, KEY_FASTFORWARD, 82 }, 83 }; 84 85 static struct resource sh_keysc_resources[] = { 86 [0] = { 87 .start = 0x044b0000, 88 .end = 0x044b000f, 89 .flags = IORESOURCE_MEM, 90 }, 91 [1] = { 92 .start = evt2irq(0xbe0), 93 .flags = IORESOURCE_IRQ, 94 }, 95 }; 96 97 static struct platform_device sh_keysc_device = { 98 .name = "sh_keysc", 99 .id = 0, /* "keysc0" clock */ 100 .num_resources = ARRAY_SIZE(sh_keysc_resources), 101 .resource = sh_keysc_resources, 102 .dev = { 103 .platform_data = &sh_keysc_info, 104 }, 105 }; 106 107 static struct mtd_partition migor_nor_flash_partitions[] = 108 { 109 { 110 .name = "uboot", 111 .offset = 0, 112 .size = (1 * 1024 * 1024), 113 .mask_flags = MTD_WRITEABLE, /* Read-only */ 114 }, 115 { 116 .name = "rootfs", 117 .offset = MTDPART_OFS_APPEND, 118 .size = (15 * 1024 * 1024), 119 }, 120 { 121 .name = "other", 122 .offset = MTDPART_OFS_APPEND, 123 .size = MTDPART_SIZ_FULL, 124 }, 125 }; 126 127 static struct physmap_flash_data migor_nor_flash_data = { 128 .width = 2, 129 .parts = migor_nor_flash_partitions, 130 .nr_parts = ARRAY_SIZE(migor_nor_flash_partitions), 131 }; 132 133 static struct resource migor_nor_flash_resources[] = { 134 [0] = { 135 .name = "NOR Flash", 136 .start = 0x00000000, 137 .end = 0x03ffffff, 138 .flags = IORESOURCE_MEM, 139 } 140 }; 141 142 static struct platform_device migor_nor_flash_device = { 143 .name = "physmap-flash", 144 .resource = migor_nor_flash_resources, 145 .num_resources = ARRAY_SIZE(migor_nor_flash_resources), 146 .dev = { 147 .platform_data = &migor_nor_flash_data, 148 }, 149 }; 150 151 static struct mtd_partition migor_nand_flash_partitions[] = { 152 { 153 .name = "nanddata1", 154 .offset = 0x0, 155 .size = 512 * 1024 * 1024, 156 }, 157 { 158 .name = "nanddata2", 159 .offset = MTDPART_OFS_APPEND, 160 .size = 512 * 1024 * 1024, 161 }, 162 }; 163 164 static void migor_nand_flash_cmd_ctl(struct mtd_info *mtd, int cmd, 165 unsigned int ctrl) 166 { 167 struct nand_chip *chip = mtd->priv; 168 169 if (cmd == NAND_CMD_NONE) 170 return; 171 172 if (ctrl & NAND_CLE) 173 writeb(cmd, chip->IO_ADDR_W + 0x00400000); 174 else if (ctrl & NAND_ALE) 175 writeb(cmd, chip->IO_ADDR_W + 0x00800000); 176 else 177 writeb(cmd, chip->IO_ADDR_W); 178 } 179 180 static int migor_nand_flash_ready(struct mtd_info *mtd) 181 { 182 return gpio_get_value(GPIO_PTA1); /* NAND_RBn */ 183 } 184 185 static struct platform_nand_data migor_nand_flash_data = { 186 .chip = { 187 .nr_chips = 1, 188 .partitions = migor_nand_flash_partitions, 189 .nr_partitions = ARRAY_SIZE(migor_nand_flash_partitions), 190 .chip_delay = 20, 191 .part_probe_types = (const char *[]) { "cmdlinepart", NULL }, 192 }, 193 .ctrl = { 194 .dev_ready = migor_nand_flash_ready, 195 .cmd_ctrl = migor_nand_flash_cmd_ctl, 196 }, 197 }; 198 199 static struct resource migor_nand_flash_resources[] = { 200 [0] = { 201 .name = "NAND Flash", 202 .start = 0x18000000, 203 .end = 0x18ffffff, 204 .flags = IORESOURCE_MEM, 205 }, 206 }; 207 208 static struct platform_device migor_nand_flash_device = { 209 .name = "gen_nand", 210 .resource = migor_nand_flash_resources, 211 .num_resources = ARRAY_SIZE(migor_nand_flash_resources), 212 .dev = { 213 .platform_data = &migor_nand_flash_data, 214 } 215 }; 216 217 static const struct fb_videomode migor_lcd_modes[] = { 218 { 219 #if defined(CONFIG_SH_MIGOR_RTA_WVGA) 220 .name = "LB070WV1", 221 .xres = 800, 222 .yres = 480, 223 .left_margin = 64, 224 .right_margin = 16, 225 .hsync_len = 120, 226 .sync = 0, 227 #elif defined(CONFIG_SH_MIGOR_QVGA) 228 .name = "PH240320T", 229 .xres = 320, 230 .yres = 240, 231 .left_margin = 0, 232 .right_margin = 16, 233 .hsync_len = 8, 234 .sync = FB_SYNC_HOR_HIGH_ACT, 235 #endif 236 .upper_margin = 1, 237 .lower_margin = 17, 238 .vsync_len = 2, 239 }, 240 }; 241 242 static struct sh_mobile_lcdc_info sh_mobile_lcdc_info = { 243 #if defined(CONFIG_SH_MIGOR_RTA_WVGA) 244 .clock_source = LCDC_CLK_BUS, 245 .ch[0] = { 246 .chan = LCDC_CHAN_MAINLCD, 247 .fourcc = V4L2_PIX_FMT_RGB565, 248 .interface_type = RGB16, 249 .clock_divider = 2, 250 .lcd_modes = migor_lcd_modes, 251 .num_modes = ARRAY_SIZE(migor_lcd_modes), 252 .panel_cfg = { /* 7.0 inch */ 253 .width = 152, 254 .height = 91, 255 }, 256 } 257 #elif defined(CONFIG_SH_MIGOR_QVGA) 258 .clock_source = LCDC_CLK_PERIPHERAL, 259 .ch[0] = { 260 .chan = LCDC_CHAN_MAINLCD, 261 .fourcc = V4L2_PIX_FMT_RGB565, 262 .interface_type = SYS16A, 263 .clock_divider = 10, 264 .lcd_modes = migor_lcd_modes, 265 .num_modes = ARRAY_SIZE(migor_lcd_modes), 266 .panel_cfg = { 267 .width = 49, /* 2.4 inch */ 268 .height = 37, 269 .setup_sys = migor_lcd_qvga_setup, 270 }, 271 .sys_bus_cfg = { 272 .ldmt2r = 0x06000a09, 273 .ldmt3r = 0x180e3418, 274 /* set 1s delay to encourage fsync() */ 275 .deferred_io_msec = 1000, 276 }, 277 } 278 #endif 279 }; 280 281 static struct resource migor_lcdc_resources[] = { 282 [0] = { 283 .name = "LCDC", 284 .start = 0xfe940000, /* P4-only space */ 285 .end = 0xfe942fff, 286 .flags = IORESOURCE_MEM, 287 }, 288 [1] = { 289 .start = evt2irq(0x580), 290 .flags = IORESOURCE_IRQ, 291 }, 292 }; 293 294 static struct platform_device migor_lcdc_device = { 295 .name = "sh_mobile_lcdc_fb", 296 .num_resources = ARRAY_SIZE(migor_lcdc_resources), 297 .resource = migor_lcdc_resources, 298 .dev = { 299 .platform_data = &sh_mobile_lcdc_info, 300 }, 301 }; 302 303 static struct clk *camera_clk; 304 static DEFINE_MUTEX(camera_lock); 305 306 static void camera_power_on(int is_tw) 307 { 308 mutex_lock(&camera_lock); 309 310 /* Use 10 MHz VIO_CKO instead of 24 MHz to work 311 * around signal quality issues on Panel Board V2.1. 312 */ 313 camera_clk = clk_get(NULL, "video_clk"); 314 clk_set_rate(camera_clk, 10000000); 315 clk_enable(camera_clk); /* start VIO_CKO */ 316 317 /* use VIO_RST to take camera out of reset */ 318 mdelay(10); 319 if (is_tw) { 320 gpio_set_value(GPIO_PTT2, 0); 321 gpio_set_value(GPIO_PTT0, 0); 322 } else { 323 gpio_set_value(GPIO_PTT0, 1); 324 } 325 gpio_set_value(GPIO_PTT3, 0); 326 mdelay(10); 327 gpio_set_value(GPIO_PTT3, 1); 328 mdelay(10); /* wait to let chip come out of reset */ 329 } 330 331 static void camera_power_off(void) 332 { 333 clk_disable(camera_clk); /* stop VIO_CKO */ 334 clk_put(camera_clk); 335 336 gpio_set_value(GPIO_PTT3, 0); 337 mutex_unlock(&camera_lock); 338 } 339 340 static int ov7725_power(struct device *dev, int mode) 341 { 342 if (mode) 343 camera_power_on(0); 344 else 345 camera_power_off(); 346 347 return 0; 348 } 349 350 static int tw9910_power(struct device *dev, int mode) 351 { 352 if (mode) 353 camera_power_on(1); 354 else 355 camera_power_off(); 356 357 return 0; 358 } 359 360 static struct sh_mobile_ceu_info sh_mobile_ceu_info = { 361 .flags = SH_CEU_FLAG_USE_8BIT_BUS, 362 }; 363 364 static struct resource migor_ceu_resources[] = { 365 [0] = { 366 .name = "CEU", 367 .start = 0xfe910000, 368 .end = 0xfe91009f, 369 .flags = IORESOURCE_MEM, 370 }, 371 [1] = { 372 .start = evt2irq(0x880), 373 .flags = IORESOURCE_IRQ, 374 }, 375 [2] = { 376 /* place holder for contiguous memory */ 377 }, 378 }; 379 380 static struct platform_device migor_ceu_device = { 381 .name = "sh_mobile_ceu", 382 .id = 0, /* "ceu0" clock */ 383 .num_resources = ARRAY_SIZE(migor_ceu_resources), 384 .resource = migor_ceu_resources, 385 .dev = { 386 .platform_data = &sh_mobile_ceu_info, 387 }, 388 }; 389 390 static struct resource sdhi_cn9_resources[] = { 391 [0] = { 392 .name = "SDHI", 393 .start = 0x04ce0000, 394 .end = 0x04ce00ff, 395 .flags = IORESOURCE_MEM, 396 }, 397 [1] = { 398 .start = evt2irq(0xe80), 399 .flags = IORESOURCE_IRQ, 400 }, 401 }; 402 403 static struct sh_mobile_sdhi_info sh7724_sdhi_data = { 404 .dma_slave_tx = SHDMA_SLAVE_SDHI0_TX, 405 .dma_slave_rx = SHDMA_SLAVE_SDHI0_RX, 406 .tmio_caps = MMC_CAP_SDIO_IRQ, 407 }; 408 409 static struct platform_device sdhi_cn9_device = { 410 .name = "sh_mobile_sdhi", 411 .num_resources = ARRAY_SIZE(sdhi_cn9_resources), 412 .resource = sdhi_cn9_resources, 413 .dev = { 414 .platform_data = &sh7724_sdhi_data, 415 }, 416 }; 417 418 static struct i2c_board_info migor_i2c_devices[] = { 419 { 420 I2C_BOARD_INFO("rs5c372b", 0x32), 421 }, 422 { 423 I2C_BOARD_INFO("migor_ts", 0x51), 424 .irq = evt2irq(0x6c0), /* IRQ6 */ 425 }, 426 { 427 I2C_BOARD_INFO("wm8978", 0x1a), 428 }, 429 }; 430 431 static struct i2c_board_info migor_i2c_camera[] = { 432 { 433 I2C_BOARD_INFO("ov772x", 0x21), 434 }, 435 { 436 I2C_BOARD_INFO("tw9910", 0x45), 437 }, 438 }; 439 440 static struct ov772x_camera_info ov7725_info; 441 442 static struct soc_camera_link ov7725_link = { 443 .power = ov7725_power, 444 .board_info = &migor_i2c_camera[0], 445 .i2c_adapter_id = 0, 446 .priv = &ov7725_info, 447 }; 448 449 static struct tw9910_video_info tw9910_info = { 450 .buswidth = SOCAM_DATAWIDTH_8, 451 .mpout = TW9910_MPO_FIELD, 452 }; 453 454 static struct soc_camera_link tw9910_link = { 455 .power = tw9910_power, 456 .board_info = &migor_i2c_camera[1], 457 .i2c_adapter_id = 0, 458 .priv = &tw9910_info, 459 }; 460 461 static struct platform_device migor_camera[] = { 462 { 463 .name = "soc-camera-pdrv", 464 .id = 0, 465 .dev = { 466 .platform_data = &ov7725_link, 467 }, 468 }, { 469 .name = "soc-camera-pdrv", 470 .id = 1, 471 .dev = { 472 .platform_data = &tw9910_link, 473 }, 474 }, 475 }; 476 477 static struct platform_device *migor_devices[] __initdata = { 478 &smc91x_eth_device, 479 &sh_keysc_device, 480 &migor_lcdc_device, 481 &migor_ceu_device, 482 &migor_nor_flash_device, 483 &migor_nand_flash_device, 484 &sdhi_cn9_device, 485 &migor_camera[0], 486 &migor_camera[1], 487 }; 488 489 extern char migor_sdram_enter_start; 490 extern char migor_sdram_enter_end; 491 extern char migor_sdram_leave_start; 492 extern char migor_sdram_leave_end; 493 494 static int __init migor_devices_setup(void) 495 { 496 /* register board specific self-refresh code */ 497 sh_mobile_register_self_refresh(SUSP_SH_STANDBY | SUSP_SH_SF, 498 &migor_sdram_enter_start, 499 &migor_sdram_enter_end, 500 &migor_sdram_leave_start, 501 &migor_sdram_leave_end); 502 /* Let D11 LED show STATUS0 */ 503 gpio_request(GPIO_FN_STATUS0, NULL); 504 505 /* Lit D12 LED show PDSTATUS */ 506 gpio_request(GPIO_FN_PDSTATUS, NULL); 507 508 /* SMC91C111 - Enable IRQ0, Setup CS4 for 16-bit fast access */ 509 gpio_request(GPIO_FN_IRQ0, NULL); 510 __raw_writel(0x00003400, BSC_CS4BCR); 511 __raw_writel(0x00110080, BSC_CS4WCR); 512 513 /* KEYSC */ 514 gpio_request(GPIO_FN_KEYOUT0, NULL); 515 gpio_request(GPIO_FN_KEYOUT1, NULL); 516 gpio_request(GPIO_FN_KEYOUT2, NULL); 517 gpio_request(GPIO_FN_KEYOUT3, NULL); 518 gpio_request(GPIO_FN_KEYOUT4_IN6, NULL); 519 gpio_request(GPIO_FN_KEYIN1, NULL); 520 gpio_request(GPIO_FN_KEYIN2, NULL); 521 gpio_request(GPIO_FN_KEYIN3, NULL); 522 gpio_request(GPIO_FN_KEYIN4, NULL); 523 gpio_request(GPIO_FN_KEYOUT5_IN5, NULL); 524 525 /* NAND Flash */ 526 gpio_request(GPIO_FN_CS6A_CE2B, NULL); 527 __raw_writel((__raw_readl(BSC_CS6ABCR) & ~0x0600) | 0x0200, BSC_CS6ABCR); 528 gpio_request(GPIO_PTA1, NULL); 529 gpio_direction_input(GPIO_PTA1); 530 531 /* SDHI */ 532 gpio_request(GPIO_FN_SDHICD, NULL); 533 gpio_request(GPIO_FN_SDHIWP, NULL); 534 gpio_request(GPIO_FN_SDHID3, NULL); 535 gpio_request(GPIO_FN_SDHID2, NULL); 536 gpio_request(GPIO_FN_SDHID1, NULL); 537 gpio_request(GPIO_FN_SDHID0, NULL); 538 gpio_request(GPIO_FN_SDHICMD, NULL); 539 gpio_request(GPIO_FN_SDHICLK, NULL); 540 541 /* Touch Panel */ 542 gpio_request(GPIO_FN_IRQ6, NULL); 543 544 /* LCD Panel */ 545 #ifdef CONFIG_SH_MIGOR_QVGA /* LCDC - QVGA - Enable SYS Interface signals */ 546 gpio_request(GPIO_FN_LCDD17, NULL); 547 gpio_request(GPIO_FN_LCDD16, NULL); 548 gpio_request(GPIO_FN_LCDD15, NULL); 549 gpio_request(GPIO_FN_LCDD14, NULL); 550 gpio_request(GPIO_FN_LCDD13, NULL); 551 gpio_request(GPIO_FN_LCDD12, NULL); 552 gpio_request(GPIO_FN_LCDD11, NULL); 553 gpio_request(GPIO_FN_LCDD10, NULL); 554 gpio_request(GPIO_FN_LCDD8, NULL); 555 gpio_request(GPIO_FN_LCDD7, NULL); 556 gpio_request(GPIO_FN_LCDD6, NULL); 557 gpio_request(GPIO_FN_LCDD5, NULL); 558 gpio_request(GPIO_FN_LCDD4, NULL); 559 gpio_request(GPIO_FN_LCDD3, NULL); 560 gpio_request(GPIO_FN_LCDD2, NULL); 561 gpio_request(GPIO_FN_LCDD1, NULL); 562 gpio_request(GPIO_FN_LCDRS, NULL); 563 gpio_request(GPIO_FN_LCDCS, NULL); 564 gpio_request(GPIO_FN_LCDRD, NULL); 565 gpio_request(GPIO_FN_LCDWR, NULL); 566 gpio_request(GPIO_PTH2, NULL); /* LCD_DON */ 567 gpio_direction_output(GPIO_PTH2, 1); 568 #endif 569 #ifdef CONFIG_SH_MIGOR_RTA_WVGA /* LCDC - WVGA - Enable RGB Interface signals */ 570 gpio_request(GPIO_FN_LCDD15, NULL); 571 gpio_request(GPIO_FN_LCDD14, NULL); 572 gpio_request(GPIO_FN_LCDD13, NULL); 573 gpio_request(GPIO_FN_LCDD12, NULL); 574 gpio_request(GPIO_FN_LCDD11, NULL); 575 gpio_request(GPIO_FN_LCDD10, NULL); 576 gpio_request(GPIO_FN_LCDD9, NULL); 577 gpio_request(GPIO_FN_LCDD8, NULL); 578 gpio_request(GPIO_FN_LCDD7, NULL); 579 gpio_request(GPIO_FN_LCDD6, NULL); 580 gpio_request(GPIO_FN_LCDD5, NULL); 581 gpio_request(GPIO_FN_LCDD4, NULL); 582 gpio_request(GPIO_FN_LCDD3, NULL); 583 gpio_request(GPIO_FN_LCDD2, NULL); 584 gpio_request(GPIO_FN_LCDD1, NULL); 585 gpio_request(GPIO_FN_LCDD0, NULL); 586 gpio_request(GPIO_FN_LCDLCLK, NULL); 587 gpio_request(GPIO_FN_LCDDCK, NULL); 588 gpio_request(GPIO_FN_LCDVEPWC, NULL); 589 gpio_request(GPIO_FN_LCDVCPWC, NULL); 590 gpio_request(GPIO_FN_LCDVSYN, NULL); 591 gpio_request(GPIO_FN_LCDHSYN, NULL); 592 gpio_request(GPIO_FN_LCDDISP, NULL); 593 gpio_request(GPIO_FN_LCDDON, NULL); 594 #endif 595 596 /* CEU */ 597 gpio_request(GPIO_FN_VIO_CLK2, NULL); 598 gpio_request(GPIO_FN_VIO_VD2, NULL); 599 gpio_request(GPIO_FN_VIO_HD2, NULL); 600 gpio_request(GPIO_FN_VIO_FLD, NULL); 601 gpio_request(GPIO_FN_VIO_CKO, NULL); 602 gpio_request(GPIO_FN_VIO_D15, NULL); 603 gpio_request(GPIO_FN_VIO_D14, NULL); 604 gpio_request(GPIO_FN_VIO_D13, NULL); 605 gpio_request(GPIO_FN_VIO_D12, NULL); 606 gpio_request(GPIO_FN_VIO_D11, NULL); 607 gpio_request(GPIO_FN_VIO_D10, NULL); 608 gpio_request(GPIO_FN_VIO_D9, NULL); 609 gpio_request(GPIO_FN_VIO_D8, NULL); 610 611 gpio_request(GPIO_PTT3, NULL); /* VIO_RST */ 612 gpio_direction_output(GPIO_PTT3, 0); 613 gpio_request(GPIO_PTT2, NULL); /* TV_IN_EN */ 614 gpio_direction_output(GPIO_PTT2, 1); 615 gpio_request(GPIO_PTT0, NULL); /* CAM_EN */ 616 #ifdef CONFIG_SH_MIGOR_RTA_WVGA 617 gpio_direction_output(GPIO_PTT0, 0); 618 #else 619 gpio_direction_output(GPIO_PTT0, 1); 620 #endif 621 __raw_writew(__raw_readw(PORT_MSELCRB) | 0x2000, PORT_MSELCRB); /* D15->D8 */ 622 623 platform_resource_setup_memory(&migor_ceu_device, "ceu", 4 << 20); 624 625 /* SIU: Port B */ 626 gpio_request(GPIO_FN_SIUBOLR, NULL); 627 gpio_request(GPIO_FN_SIUBOBT, NULL); 628 gpio_request(GPIO_FN_SIUBISLD, NULL); 629 gpio_request(GPIO_FN_SIUBOSLD, NULL); 630 gpio_request(GPIO_FN_SIUMCKB, NULL); 631 632 /* 633 * The original driver sets SIUB OLR/OBT, ILR/IBT, and SIUA OLR/OBT to 634 * output. Need only SIUB, set to output for master mode (table 34.2) 635 */ 636 __raw_writew(__raw_readw(PORT_MSELCRA) | 1, PORT_MSELCRA); 637 638 i2c_register_board_info(0, migor_i2c_devices, 639 ARRAY_SIZE(migor_i2c_devices)); 640 641 return platform_add_devices(migor_devices, ARRAY_SIZE(migor_devices)); 642 } 643 arch_initcall(migor_devices_setup); 644 645 /* Return the board specific boot mode pin configuration */ 646 static int migor_mode_pins(void) 647 { 648 /* MD0=1, MD1=1, MD2=0: Clock Mode 3 649 * MD3=0: 16-bit Area0 Bus Width 650 * MD5=1: Little Endian 651 * TSTMD=1, MD8=0: Test Mode Disabled 652 */ 653 return MODE_PIN0 | MODE_PIN1 | MODE_PIN5; 654 } 655 656 /* 657 * The Machine Vector 658 */ 659 static struct sh_machine_vector mv_migor __initmv = { 660 .mv_name = "Migo-R", 661 .mv_mode_pins = migor_mode_pins, 662 }; 663