1da2014a2SPaul Mundt /* 2da2014a2SPaul Mundt * arch/sh/boards/dreamcast/irq.c 3da2014a2SPaul Mundt * 4da2014a2SPaul Mundt * Holly IRQ support for the Sega Dreamcast. 5da2014a2SPaul Mundt * 6da2014a2SPaul Mundt * Copyright (c) 2001, 2002 M. R. Brown <mrbrown@0xd6.org> 7da2014a2SPaul Mundt * 8da2014a2SPaul Mundt * This file is part of the LinuxDC project (www.linuxdc.org) 9da2014a2SPaul Mundt * Released under the terms of the GNU GPL v2.0 10da2014a2SPaul Mundt */ 11da2014a2SPaul Mundt 12da2014a2SPaul Mundt #include <linux/irq.h> 13*e85a4774SMatt Fleming #include <linux/io.h> 14da2014a2SPaul Mundt #include <asm/irq.h> 15da2014a2SPaul Mundt #include <mach/sysasic.h> 16da2014a2SPaul Mundt 17*e85a4774SMatt Fleming /* 18*e85a4774SMatt Fleming * Dreamcast System ASIC Hardware Events - 19*e85a4774SMatt Fleming * 20*e85a4774SMatt Fleming * The Dreamcast's System ASIC (a.k.a. Holly) is responsible for receiving 21*e85a4774SMatt Fleming * hardware events from system peripherals and triggering an SH7750 IRQ. 22*e85a4774SMatt Fleming * Hardware events can trigger IRQs 13, 11, or 9 depending on which bits are 23*e85a4774SMatt Fleming * set in the Event Mask Registers (EMRs). When a hardware event is 24*e85a4774SMatt Fleming * triggered, its corresponding bit in the Event Status Registers (ESRs) 25*e85a4774SMatt Fleming * is set, and that bit should be rewritten to the ESR to acknowledge that 26*e85a4774SMatt Fleming * event. 27*e85a4774SMatt Fleming * 28*e85a4774SMatt Fleming * There are three 32-bit ESRs located at 0xa05f6900 - 0xa05f6908. Event 29*e85a4774SMatt Fleming * types can be found in arch/sh/include/mach-dreamcast/mach/sysasic.h. 30*e85a4774SMatt Fleming * There are three groups of EMRs that parallel the ESRs. Each EMR group 31*e85a4774SMatt Fleming * corresponds to an IRQ, so 0xa05f6910 - 0xa05f6918 triggers IRQ 13, 32*e85a4774SMatt Fleming * 0xa05f6920 - 0xa05f6928 triggers IRQ 11, and 0xa05f6930 - 0xa05f6938 33*e85a4774SMatt Fleming * triggers IRQ 9. 34*e85a4774SMatt Fleming * 35*e85a4774SMatt Fleming * In the kernel, these events are mapped to virtual IRQs so that drivers can 36*e85a4774SMatt Fleming * respond to them as they would a normal interrupt. In order to keep this 37*e85a4774SMatt Fleming * mapping simple, the events are mapped as: 38*e85a4774SMatt Fleming * 39*e85a4774SMatt Fleming * 6900/6910 - Events 0-31, IRQ 13 40*e85a4774SMatt Fleming * 6904/6924 - Events 32-63, IRQ 11 41*e85a4774SMatt Fleming * 6908/6938 - Events 64-95, IRQ 9 42*e85a4774SMatt Fleming * 43da2014a2SPaul Mundt */ 44da2014a2SPaul Mundt 45da2014a2SPaul Mundt #define ESR_BASE 0x005f6900 /* Base event status register */ 46da2014a2SPaul Mundt #define EMR_BASE 0x005f6910 /* Base event mask register */ 47da2014a2SPaul Mundt 48*e85a4774SMatt Fleming /* 49*e85a4774SMatt Fleming * Helps us determine the EMR group that this event belongs to: 0 = 0x6910, 50*e85a4774SMatt Fleming * 1 = 0x6920, 2 = 0x6930; also determine the event offset. 51*e85a4774SMatt Fleming */ 52da2014a2SPaul Mundt #define LEVEL(event) (((event) - HW_EVENT_IRQ_BASE) / 32) 53da2014a2SPaul Mundt 54da2014a2SPaul Mundt /* Return the hardware event's bit positon within the EMR/ESR */ 55da2014a2SPaul Mundt #define EVENT_BIT(event) (((event) - HW_EVENT_IRQ_BASE) & 31) 56da2014a2SPaul Mundt 57*e85a4774SMatt Fleming /* 58*e85a4774SMatt Fleming * For each of these *_irq routines, the IRQ passed in is the virtual IRQ 59*e85a4774SMatt Fleming * (logically mapped to the corresponding bit for the hardware event). 60*e85a4774SMatt Fleming */ 61da2014a2SPaul Mundt 62da2014a2SPaul Mundt /* Disable the hardware event by masking its bit in its EMR */ 63da2014a2SPaul Mundt static inline void disable_systemasic_irq(unsigned int irq) 64da2014a2SPaul Mundt { 65da2014a2SPaul Mundt __u32 emr = EMR_BASE + (LEVEL(irq) << 4) + (LEVEL(irq) << 2); 66da2014a2SPaul Mundt __u32 mask; 67da2014a2SPaul Mundt 68da2014a2SPaul Mundt mask = inl(emr); 69da2014a2SPaul Mundt mask &= ~(1 << EVENT_BIT(irq)); 70da2014a2SPaul Mundt outl(mask, emr); 71da2014a2SPaul Mundt } 72da2014a2SPaul Mundt 73da2014a2SPaul Mundt /* Enable the hardware event by setting its bit in its EMR */ 74da2014a2SPaul Mundt static inline void enable_systemasic_irq(unsigned int irq) 75da2014a2SPaul Mundt { 76da2014a2SPaul Mundt __u32 emr = EMR_BASE + (LEVEL(irq) << 4) + (LEVEL(irq) << 2); 77da2014a2SPaul Mundt __u32 mask; 78da2014a2SPaul Mundt 79da2014a2SPaul Mundt mask = inl(emr); 80da2014a2SPaul Mundt mask |= (1 << EVENT_BIT(irq)); 81da2014a2SPaul Mundt outl(mask, emr); 82da2014a2SPaul Mundt } 83da2014a2SPaul Mundt 84da2014a2SPaul Mundt /* Acknowledge a hardware event by writing its bit back to its ESR */ 85*e85a4774SMatt Fleming static void mask_ack_systemasic_irq(unsigned int irq) 86da2014a2SPaul Mundt { 87da2014a2SPaul Mundt __u32 esr = ESR_BASE + (LEVEL(irq) << 2); 88da2014a2SPaul Mundt disable_systemasic_irq(irq); 89da2014a2SPaul Mundt outl((1 << EVENT_BIT(irq)), esr); 90da2014a2SPaul Mundt } 91da2014a2SPaul Mundt 92*e85a4774SMatt Fleming struct irq_chip systemasic_int = { 93*e85a4774SMatt Fleming .name = "System ASIC", 94*e85a4774SMatt Fleming .mask = disable_systemasic_irq, 95*e85a4774SMatt Fleming .mask_ack = mask_ack_systemasic_irq, 96*e85a4774SMatt Fleming .unmask = enable_systemasic_irq, 97da2014a2SPaul Mundt }; 98da2014a2SPaul Mundt 99da2014a2SPaul Mundt /* 100da2014a2SPaul Mundt * Map the hardware event indicated by the processor IRQ to a virtual IRQ. 101da2014a2SPaul Mundt */ 102da2014a2SPaul Mundt int systemasic_irq_demux(int irq) 103da2014a2SPaul Mundt { 104da2014a2SPaul Mundt __u32 emr, esr, status, level; 105da2014a2SPaul Mundt __u32 j, bit; 106da2014a2SPaul Mundt 107da2014a2SPaul Mundt switch (irq) { 108da2014a2SPaul Mundt case 13: 109da2014a2SPaul Mundt level = 0; 110da2014a2SPaul Mundt break; 111da2014a2SPaul Mundt case 11: 112da2014a2SPaul Mundt level = 1; 113da2014a2SPaul Mundt break; 114da2014a2SPaul Mundt case 9: 115da2014a2SPaul Mundt level = 2; 116da2014a2SPaul Mundt break; 117da2014a2SPaul Mundt default: 118da2014a2SPaul Mundt return irq; 119da2014a2SPaul Mundt } 120da2014a2SPaul Mundt emr = EMR_BASE + (level << 4) + (level << 2); 121da2014a2SPaul Mundt esr = ESR_BASE + (level << 2); 122da2014a2SPaul Mundt 123da2014a2SPaul Mundt /* Mask the ESR to filter any spurious, unwanted interrupts */ 124da2014a2SPaul Mundt status = inl(esr); 125da2014a2SPaul Mundt status &= inl(emr); 126da2014a2SPaul Mundt 127da2014a2SPaul Mundt /* Now scan and find the first set bit as the event to map */ 128da2014a2SPaul Mundt for (bit = 1, j = 0; j < 32; bit <<= 1, j++) { 129da2014a2SPaul Mundt if (status & bit) { 130da2014a2SPaul Mundt irq = HW_EVENT_IRQ_BASE + j + (level << 5); 131da2014a2SPaul Mundt return irq; 132da2014a2SPaul Mundt } 133da2014a2SPaul Mundt } 134da2014a2SPaul Mundt 135da2014a2SPaul Mundt /* Not reached */ 136da2014a2SPaul Mundt return irq; 137da2014a2SPaul Mundt } 138