xref: /linux/arch/sh/boards/mach-dreamcast/irq.c (revision cdd5b5a9761fd66d17586e4f4ba6588c70e640ea)
1aaf9128aSKuninori Morimoto // SPDX-License-Identifier: GPL-2.0
2da2014a2SPaul Mundt /*
3da2014a2SPaul Mundt  * arch/sh/boards/dreamcast/irq.c
4da2014a2SPaul Mundt  *
5da2014a2SPaul Mundt  * Holly IRQ support for the Sega Dreamcast.
6da2014a2SPaul Mundt  *
7da2014a2SPaul Mundt  * Copyright (c) 2001, 2002 M. R. Brown <mrbrown@0xd6.org>
8da2014a2SPaul Mundt  *
9da2014a2SPaul Mundt  * This file is part of the LinuxDC project (www.linuxdc.org)
10da2014a2SPaul Mundt  */
11da2014a2SPaul Mundt #include <linux/irq.h>
12e85a4774SMatt Fleming #include <linux/io.h>
133b1267b9SPaul Mundt #include <linux/export.h>
143b1267b9SPaul Mundt #include <linux/err.h>
15da2014a2SPaul Mundt #include <mach/sysasic.h>
16da2014a2SPaul Mundt 
17e85a4774SMatt Fleming /*
18e85a4774SMatt Fleming  * Dreamcast System ASIC Hardware Events -
19e85a4774SMatt Fleming  *
20e85a4774SMatt Fleming  * The Dreamcast's System ASIC (a.k.a. Holly) is responsible for receiving
21e85a4774SMatt Fleming  * hardware events from system peripherals and triggering an SH7750 IRQ.
22e85a4774SMatt Fleming  * Hardware events can trigger IRQs 13, 11, or 9 depending on which bits are
23e85a4774SMatt Fleming  * set in the Event Mask Registers (EMRs).  When a hardware event is
24e85a4774SMatt Fleming  * triggered, its corresponding bit in the Event Status Registers (ESRs)
25e85a4774SMatt Fleming  * is set, and that bit should be rewritten to the ESR to acknowledge that
26e85a4774SMatt Fleming  * event.
27e85a4774SMatt Fleming  *
28e85a4774SMatt Fleming  * There are three 32-bit ESRs located at 0xa05f6900 - 0xa05f6908.  Event
29e85a4774SMatt Fleming  * types can be found in arch/sh/include/mach-dreamcast/mach/sysasic.h.
30e85a4774SMatt Fleming  * There are three groups of EMRs that parallel the ESRs.  Each EMR group
31e85a4774SMatt Fleming  * corresponds to an IRQ, so 0xa05f6910 - 0xa05f6918 triggers IRQ 13,
32e85a4774SMatt Fleming  * 0xa05f6920 - 0xa05f6928 triggers IRQ 11, and 0xa05f6930 - 0xa05f6938
33e85a4774SMatt Fleming  * triggers IRQ 9.
34e85a4774SMatt Fleming  *
35e85a4774SMatt Fleming  * In the kernel, these events are mapped to virtual IRQs so that drivers can
36e85a4774SMatt Fleming  * respond to them as they would a normal interrupt.  In order to keep this
37e85a4774SMatt Fleming  * mapping simple, the events are mapped as:
38e85a4774SMatt Fleming  *
39e85a4774SMatt Fleming  * 6900/6910 - Events  0-31, IRQ 13
40e85a4774SMatt Fleming  * 6904/6924 - Events 32-63, IRQ 11
41e85a4774SMatt Fleming  * 6908/6938 - Events 64-95, IRQ  9
42e85a4774SMatt Fleming  *
43da2014a2SPaul Mundt  */
44da2014a2SPaul Mundt 
45da2014a2SPaul Mundt #define ESR_BASE 0x005f6900    /* Base event status register */
46da2014a2SPaul Mundt #define EMR_BASE 0x005f6910    /* Base event mask register */
47da2014a2SPaul Mundt 
48e85a4774SMatt Fleming /*
49e85a4774SMatt Fleming  * Helps us determine the EMR group that this event belongs to: 0 = 0x6910,
50e85a4774SMatt Fleming  * 1 = 0x6920, 2 = 0x6930; also determine the event offset.
51e85a4774SMatt Fleming  */
52da2014a2SPaul Mundt #define LEVEL(event) (((event) - HW_EVENT_IRQ_BASE) / 32)
53da2014a2SPaul Mundt 
5425985edcSLucas De Marchi /* Return the hardware event's bit position within the EMR/ESR */
55da2014a2SPaul Mundt #define EVENT_BIT(event) (((event) - HW_EVENT_IRQ_BASE) & 31)
56da2014a2SPaul Mundt 
57e85a4774SMatt Fleming /*
58e85a4774SMatt Fleming  * For each of these *_irq routines, the IRQ passed in is the virtual IRQ
59e85a4774SMatt Fleming  * (logically mapped to the corresponding bit for the hardware event).
60e85a4774SMatt Fleming  */
61da2014a2SPaul Mundt 
62da2014a2SPaul Mundt /* Disable the hardware event by masking its bit in its EMR */
disable_systemasic_irq(struct irq_data * data)630d338071SPaul Mundt static inline void disable_systemasic_irq(struct irq_data *data)
64da2014a2SPaul Mundt {
650d338071SPaul Mundt 	unsigned int irq = data->irq;
66da2014a2SPaul Mundt 	__u32 emr = EMR_BASE + (LEVEL(irq) << 4) + (LEVEL(irq) << 2);
67da2014a2SPaul Mundt 	__u32 mask;
68da2014a2SPaul Mundt 
69da2014a2SPaul Mundt 	mask = inl(emr);
70da2014a2SPaul Mundt 	mask &= ~(1 << EVENT_BIT(irq));
71da2014a2SPaul Mundt 	outl(mask, emr);
72da2014a2SPaul Mundt }
73da2014a2SPaul Mundt 
74da2014a2SPaul Mundt /* Enable the hardware event by setting its bit in its EMR */
enable_systemasic_irq(struct irq_data * data)750d338071SPaul Mundt static inline void enable_systemasic_irq(struct irq_data *data)
76da2014a2SPaul Mundt {
770d338071SPaul Mundt 	unsigned int irq = data->irq;
78da2014a2SPaul Mundt 	__u32 emr = EMR_BASE + (LEVEL(irq) << 4) + (LEVEL(irq) << 2);
79da2014a2SPaul Mundt 	__u32 mask;
80da2014a2SPaul Mundt 
81da2014a2SPaul Mundt 	mask = inl(emr);
82da2014a2SPaul Mundt 	mask |= (1 << EVENT_BIT(irq));
83da2014a2SPaul Mundt 	outl(mask, emr);
84da2014a2SPaul Mundt }
85da2014a2SPaul Mundt 
86da2014a2SPaul Mundt /* Acknowledge a hardware event by writing its bit back to its ESR */
mask_ack_systemasic_irq(struct irq_data * data)870d338071SPaul Mundt static void mask_ack_systemasic_irq(struct irq_data *data)
88da2014a2SPaul Mundt {
890d338071SPaul Mundt 	unsigned int irq = data->irq;
90da2014a2SPaul Mundt 	__u32 esr = ESR_BASE + (LEVEL(irq) << 2);
910d338071SPaul Mundt 	disable_systemasic_irq(data);
92da2014a2SPaul Mundt 	outl((1 << EVENT_BIT(irq)), esr);
93da2014a2SPaul Mundt }
94da2014a2SPaul Mundt 
95e85a4774SMatt Fleming struct irq_chip systemasic_int = {
96e85a4774SMatt Fleming 	.name		= "System ASIC",
970d338071SPaul Mundt 	.irq_mask	= disable_systemasic_irq,
980d338071SPaul Mundt 	.irq_mask_ack	= mask_ack_systemasic_irq,
990d338071SPaul Mundt 	.irq_unmask	= enable_systemasic_irq,
100da2014a2SPaul Mundt };
101da2014a2SPaul Mundt 
102da2014a2SPaul Mundt /*
103da2014a2SPaul Mundt  * Map the hardware event indicated by the processor IRQ to a virtual IRQ.
104da2014a2SPaul Mundt  */
systemasic_irq_demux(int irq)105da2014a2SPaul Mundt int systemasic_irq_demux(int irq)
106da2014a2SPaul Mundt {
107da2014a2SPaul Mundt 	__u32 emr, esr, status, level;
108da2014a2SPaul Mundt 	__u32 j, bit;
109da2014a2SPaul Mundt 
110da2014a2SPaul Mundt 	switch (irq) {
111*3d20f7a6SGeert Uytterhoeven 	case 13 + 16:
112da2014a2SPaul Mundt 		level = 0;
113da2014a2SPaul Mundt 		break;
114*3d20f7a6SGeert Uytterhoeven 	case 11 + 16:
115da2014a2SPaul Mundt 		level = 1;
116da2014a2SPaul Mundt 		break;
117*3d20f7a6SGeert Uytterhoeven 	case 9 + 16:
118da2014a2SPaul Mundt 		level = 2;
119da2014a2SPaul Mundt 		break;
120da2014a2SPaul Mundt 	default:
121da2014a2SPaul Mundt 		return irq;
122da2014a2SPaul Mundt 	}
123da2014a2SPaul Mundt 	emr = EMR_BASE + (level << 4) + (level << 2);
124da2014a2SPaul Mundt 	esr = ESR_BASE + (level << 2);
125da2014a2SPaul Mundt 
126da2014a2SPaul Mundt 	/* Mask the ESR to filter any spurious, unwanted interrupts */
127da2014a2SPaul Mundt 	status = inl(esr);
128da2014a2SPaul Mundt 	status &= inl(emr);
129da2014a2SPaul Mundt 
130da2014a2SPaul Mundt 	/* Now scan and find the first set bit as the event to map */
131da2014a2SPaul Mundt 	for (bit = 1, j = 0; j < 32; bit <<= 1, j++) {
132da2014a2SPaul Mundt 		if (status & bit) {
133da2014a2SPaul Mundt 			irq = HW_EVENT_IRQ_BASE + j + (level << 5);
134da2014a2SPaul Mundt 			return irq;
135da2014a2SPaul Mundt 		}
136da2014a2SPaul Mundt 	}
137da2014a2SPaul Mundt 
138da2014a2SPaul Mundt 	/* Not reached */
139da2014a2SPaul Mundt 	return irq;
140da2014a2SPaul Mundt }
141deb9b22bSPaul Mundt 
systemasic_irq_init(void)142deb9b22bSPaul Mundt void systemasic_irq_init(void)
143deb9b22bSPaul Mundt {
1443b1267b9SPaul Mundt 	int irq_base, i;
145deb9b22bSPaul Mundt 
1463b1267b9SPaul Mundt 	irq_base = irq_alloc_descs(HW_EVENT_IRQ_BASE, HW_EVENT_IRQ_BASE,
1473b1267b9SPaul Mundt 				   HW_EVENT_IRQ_MAX - HW_EVENT_IRQ_BASE, -1);
1483b1267b9SPaul Mundt 	if (IS_ERR_VALUE(irq_base)) {
1493b1267b9SPaul Mundt 		pr_err("%s: failed hooking irqs\n", __func__);
150deb9b22bSPaul Mundt 		return;
151deb9b22bSPaul Mundt 	}
152deb9b22bSPaul Mundt 
1533b1267b9SPaul Mundt 	for (i = HW_EVENT_IRQ_BASE; i < HW_EVENT_IRQ_MAX; i++)
154fcb8918fSThomas Gleixner 		irq_set_chip_and_handler(i, &systemasic_int, handle_level_irq);
155deb9b22bSPaul Mundt }
156