1da2014a2SPaul Mundt /* 2da2014a2SPaul Mundt * arch/sh/boards/dreamcast/irq.c 3da2014a2SPaul Mundt * 4da2014a2SPaul Mundt * Holly IRQ support for the Sega Dreamcast. 5da2014a2SPaul Mundt * 6da2014a2SPaul Mundt * Copyright (c) 2001, 2002 M. R. Brown <mrbrown@0xd6.org> 7da2014a2SPaul Mundt * 8da2014a2SPaul Mundt * This file is part of the LinuxDC project (www.linuxdc.org) 9da2014a2SPaul Mundt * Released under the terms of the GNU GPL v2.0 10da2014a2SPaul Mundt */ 11da2014a2SPaul Mundt #include <linux/irq.h> 12e85a4774SMatt Fleming #include <linux/io.h> 13*3b1267b9SPaul Mundt #include <linux/irq.h> 14*3b1267b9SPaul Mundt #include <linux/export.h> 15*3b1267b9SPaul Mundt #include <linux/err.h> 16da2014a2SPaul Mundt #include <mach/sysasic.h> 17da2014a2SPaul Mundt 18e85a4774SMatt Fleming /* 19e85a4774SMatt Fleming * Dreamcast System ASIC Hardware Events - 20e85a4774SMatt Fleming * 21e85a4774SMatt Fleming * The Dreamcast's System ASIC (a.k.a. Holly) is responsible for receiving 22e85a4774SMatt Fleming * hardware events from system peripherals and triggering an SH7750 IRQ. 23e85a4774SMatt Fleming * Hardware events can trigger IRQs 13, 11, or 9 depending on which bits are 24e85a4774SMatt Fleming * set in the Event Mask Registers (EMRs). When a hardware event is 25e85a4774SMatt Fleming * triggered, its corresponding bit in the Event Status Registers (ESRs) 26e85a4774SMatt Fleming * is set, and that bit should be rewritten to the ESR to acknowledge that 27e85a4774SMatt Fleming * event. 28e85a4774SMatt Fleming * 29e85a4774SMatt Fleming * There are three 32-bit ESRs located at 0xa05f6900 - 0xa05f6908. Event 30e85a4774SMatt Fleming * types can be found in arch/sh/include/mach-dreamcast/mach/sysasic.h. 31e85a4774SMatt Fleming * There are three groups of EMRs that parallel the ESRs. Each EMR group 32e85a4774SMatt Fleming * corresponds to an IRQ, so 0xa05f6910 - 0xa05f6918 triggers IRQ 13, 33e85a4774SMatt Fleming * 0xa05f6920 - 0xa05f6928 triggers IRQ 11, and 0xa05f6930 - 0xa05f6938 34e85a4774SMatt Fleming * triggers IRQ 9. 35e85a4774SMatt Fleming * 36e85a4774SMatt Fleming * In the kernel, these events are mapped to virtual IRQs so that drivers can 37e85a4774SMatt Fleming * respond to them as they would a normal interrupt. In order to keep this 38e85a4774SMatt Fleming * mapping simple, the events are mapped as: 39e85a4774SMatt Fleming * 40e85a4774SMatt Fleming * 6900/6910 - Events 0-31, IRQ 13 41e85a4774SMatt Fleming * 6904/6924 - Events 32-63, IRQ 11 42e85a4774SMatt Fleming * 6908/6938 - Events 64-95, IRQ 9 43e85a4774SMatt Fleming * 44da2014a2SPaul Mundt */ 45da2014a2SPaul Mundt 46da2014a2SPaul Mundt #define ESR_BASE 0x005f6900 /* Base event status register */ 47da2014a2SPaul Mundt #define EMR_BASE 0x005f6910 /* Base event mask register */ 48da2014a2SPaul Mundt 49e85a4774SMatt Fleming /* 50e85a4774SMatt Fleming * Helps us determine the EMR group that this event belongs to: 0 = 0x6910, 51e85a4774SMatt Fleming * 1 = 0x6920, 2 = 0x6930; also determine the event offset. 52e85a4774SMatt Fleming */ 53da2014a2SPaul Mundt #define LEVEL(event) (((event) - HW_EVENT_IRQ_BASE) / 32) 54da2014a2SPaul Mundt 5525985edcSLucas De Marchi /* Return the hardware event's bit position within the EMR/ESR */ 56da2014a2SPaul Mundt #define EVENT_BIT(event) (((event) - HW_EVENT_IRQ_BASE) & 31) 57da2014a2SPaul Mundt 58e85a4774SMatt Fleming /* 59e85a4774SMatt Fleming * For each of these *_irq routines, the IRQ passed in is the virtual IRQ 60e85a4774SMatt Fleming * (logically mapped to the corresponding bit for the hardware event). 61e85a4774SMatt Fleming */ 62da2014a2SPaul Mundt 63da2014a2SPaul Mundt /* Disable the hardware event by masking its bit in its EMR */ 640d338071SPaul Mundt static inline void disable_systemasic_irq(struct irq_data *data) 65da2014a2SPaul Mundt { 660d338071SPaul Mundt unsigned int irq = data->irq; 67da2014a2SPaul Mundt __u32 emr = EMR_BASE + (LEVEL(irq) << 4) + (LEVEL(irq) << 2); 68da2014a2SPaul Mundt __u32 mask; 69da2014a2SPaul Mundt 70da2014a2SPaul Mundt mask = inl(emr); 71da2014a2SPaul Mundt mask &= ~(1 << EVENT_BIT(irq)); 72da2014a2SPaul Mundt outl(mask, emr); 73da2014a2SPaul Mundt } 74da2014a2SPaul Mundt 75da2014a2SPaul Mundt /* Enable the hardware event by setting its bit in its EMR */ 760d338071SPaul Mundt static inline void enable_systemasic_irq(struct irq_data *data) 77da2014a2SPaul Mundt { 780d338071SPaul Mundt unsigned int irq = data->irq; 79da2014a2SPaul Mundt __u32 emr = EMR_BASE + (LEVEL(irq) << 4) + (LEVEL(irq) << 2); 80da2014a2SPaul Mundt __u32 mask; 81da2014a2SPaul Mundt 82da2014a2SPaul Mundt mask = inl(emr); 83da2014a2SPaul Mundt mask |= (1 << EVENT_BIT(irq)); 84da2014a2SPaul Mundt outl(mask, emr); 85da2014a2SPaul Mundt } 86da2014a2SPaul Mundt 87da2014a2SPaul Mundt /* Acknowledge a hardware event by writing its bit back to its ESR */ 880d338071SPaul Mundt static void mask_ack_systemasic_irq(struct irq_data *data) 89da2014a2SPaul Mundt { 900d338071SPaul Mundt unsigned int irq = data->irq; 91da2014a2SPaul Mundt __u32 esr = ESR_BASE + (LEVEL(irq) << 2); 920d338071SPaul Mundt disable_systemasic_irq(data); 93da2014a2SPaul Mundt outl((1 << EVENT_BIT(irq)), esr); 94da2014a2SPaul Mundt } 95da2014a2SPaul Mundt 96e85a4774SMatt Fleming struct irq_chip systemasic_int = { 97e85a4774SMatt Fleming .name = "System ASIC", 980d338071SPaul Mundt .irq_mask = disable_systemasic_irq, 990d338071SPaul Mundt .irq_mask_ack = mask_ack_systemasic_irq, 1000d338071SPaul Mundt .irq_unmask = enable_systemasic_irq, 101da2014a2SPaul Mundt }; 102da2014a2SPaul Mundt 103da2014a2SPaul Mundt /* 104da2014a2SPaul Mundt * Map the hardware event indicated by the processor IRQ to a virtual IRQ. 105da2014a2SPaul Mundt */ 106da2014a2SPaul Mundt int systemasic_irq_demux(int irq) 107da2014a2SPaul Mundt { 108da2014a2SPaul Mundt __u32 emr, esr, status, level; 109da2014a2SPaul Mundt __u32 j, bit; 110da2014a2SPaul Mundt 111da2014a2SPaul Mundt switch (irq) { 112da2014a2SPaul Mundt case 13: 113da2014a2SPaul Mundt level = 0; 114da2014a2SPaul Mundt break; 115da2014a2SPaul Mundt case 11: 116da2014a2SPaul Mundt level = 1; 117da2014a2SPaul Mundt break; 118da2014a2SPaul Mundt case 9: 119da2014a2SPaul Mundt level = 2; 120da2014a2SPaul Mundt break; 121da2014a2SPaul Mundt default: 122da2014a2SPaul Mundt return irq; 123da2014a2SPaul Mundt } 124da2014a2SPaul Mundt emr = EMR_BASE + (level << 4) + (level << 2); 125da2014a2SPaul Mundt esr = ESR_BASE + (level << 2); 126da2014a2SPaul Mundt 127da2014a2SPaul Mundt /* Mask the ESR to filter any spurious, unwanted interrupts */ 128da2014a2SPaul Mundt status = inl(esr); 129da2014a2SPaul Mundt status &= inl(emr); 130da2014a2SPaul Mundt 131da2014a2SPaul Mundt /* Now scan and find the first set bit as the event to map */ 132da2014a2SPaul Mundt for (bit = 1, j = 0; j < 32; bit <<= 1, j++) { 133da2014a2SPaul Mundt if (status & bit) { 134da2014a2SPaul Mundt irq = HW_EVENT_IRQ_BASE + j + (level << 5); 135da2014a2SPaul Mundt return irq; 136da2014a2SPaul Mundt } 137da2014a2SPaul Mundt } 138da2014a2SPaul Mundt 139da2014a2SPaul Mundt /* Not reached */ 140da2014a2SPaul Mundt return irq; 141da2014a2SPaul Mundt } 142deb9b22bSPaul Mundt 143deb9b22bSPaul Mundt void systemasic_irq_init(void) 144deb9b22bSPaul Mundt { 145*3b1267b9SPaul Mundt int irq_base, i; 146deb9b22bSPaul Mundt 147*3b1267b9SPaul Mundt irq_base = irq_alloc_descs(HW_EVENT_IRQ_BASE, HW_EVENT_IRQ_BASE, 148*3b1267b9SPaul Mundt HW_EVENT_IRQ_MAX - HW_EVENT_IRQ_BASE, -1); 149*3b1267b9SPaul Mundt if (IS_ERR_VALUE(irq_base)) { 150*3b1267b9SPaul Mundt pr_err("%s: failed hooking irqs\n", __func__); 151deb9b22bSPaul Mundt return; 152deb9b22bSPaul Mundt } 153deb9b22bSPaul Mundt 154*3b1267b9SPaul Mundt for (i = HW_EVENT_IRQ_BASE; i < HW_EVENT_IRQ_MAX; i++) 155fcb8918fSThomas Gleixner irq_set_chip_and_handler(i, &systemasic_int, handle_level_irq); 156deb9b22bSPaul Mundt } 157