1 /* 2 * linux/arch/sh/boards/magicpanel/setup.c 3 * 4 * Copyright (C) 2007 Markus Brunner, Mark Jonas 5 * 6 * Magic Panel Release 2 board setup 7 * 8 * This file is subject to the terms and conditions of the GNU General Public 9 * License. See the file "COPYING" in the main directory of this archive 10 * for more details. 11 */ 12 #include <linux/init.h> 13 #include <linux/irq.h> 14 #include <linux/platform_device.h> 15 #include <linux/delay.h> 16 #include <linux/gpio.h> 17 #include <linux/smsc911x.h> 18 #include <linux/mtd/mtd.h> 19 #include <linux/mtd/partitions.h> 20 #include <linux/mtd/physmap.h> 21 #include <linux/mtd/map.h> 22 #include <mach/magicpanelr2.h> 23 #include <asm/heartbeat.h> 24 #include <cpu/sh7720.h> 25 26 #define LAN9115_READY (__raw_readl(0xA8000084UL) & 0x00000001UL) 27 28 /* Wait until reset finished. Timeout is 100ms. */ 29 static int __init ethernet_reset_finished(void) 30 { 31 int i; 32 33 if (LAN9115_READY) 34 return 1; 35 36 for (i = 0; i < 10; ++i) { 37 mdelay(10); 38 if (LAN9115_READY) 39 return 1; 40 } 41 42 return 0; 43 } 44 45 static void __init reset_ethernet(void) 46 { 47 /* PMDR: LAN_RESET=on */ 48 CLRBITS_OUTB(0x10, PORT_PMDR); 49 50 udelay(200); 51 52 /* PMDR: LAN_RESET=off */ 53 SETBITS_OUTB(0x10, PORT_PMDR); 54 } 55 56 static void __init setup_chip_select(void) 57 { 58 /* CS2: LAN (0x08000000 - 0x0bffffff) */ 59 /* no idle cycles, normal space, 8 bit data bus */ 60 __raw_writel(0x36db0400, CS2BCR); 61 /* (SW:1.5 WR:3 HW:1.5), ext. wait */ 62 __raw_writel(0x000003c0, CS2WCR); 63 64 /* CS4: CAN1 (0xb0000000 - 0xb3ffffff) */ 65 /* no idle cycles, normal space, 8 bit data bus */ 66 __raw_writel(0x00000200, CS4BCR); 67 /* (SW:1.5 WR:3 HW:1.5), ext. wait */ 68 __raw_writel(0x00100981, CS4WCR); 69 70 /* CS5a: CAN2 (0xb4000000 - 0xb5ffffff) */ 71 /* no idle cycles, normal space, 8 bit data bus */ 72 __raw_writel(0x00000200, CS5ABCR); 73 /* (SW:1.5 WR:3 HW:1.5), ext. wait */ 74 __raw_writel(0x00100981, CS5AWCR); 75 76 /* CS5b: CAN3 (0xb6000000 - 0xb7ffffff) */ 77 /* no idle cycles, normal space, 8 bit data bus */ 78 __raw_writel(0x00000200, CS5BBCR); 79 /* (SW:1.5 WR:3 HW:1.5), ext. wait */ 80 __raw_writel(0x00100981, CS5BWCR); 81 82 /* CS6a: Rotary (0xb8000000 - 0xb9ffffff) */ 83 /* no idle cycles, normal space, 8 bit data bus */ 84 __raw_writel(0x00000200, CS6ABCR); 85 /* (SW:1.5 WR:3 HW:1.5), no ext. wait */ 86 __raw_writel(0x001009C1, CS6AWCR); 87 } 88 89 static void __init setup_port_multiplexing(void) 90 { 91 /* A7 GPO(LED8); A6 GPO(LED7); A5 GPO(LED6); A4 GPO(LED5); 92 * A3 GPO(LED4); A2 GPO(LED3); A1 GPO(LED2); A0 GPO(LED1); 93 */ 94 __raw_writew(0x5555, PORT_PACR); /* 01 01 01 01 01 01 01 01 */ 95 96 /* B7 GPO(RST4); B6 GPO(RST3); B5 GPO(RST2); B4 GPO(RST1); 97 * B3 GPO(PB3); B2 GPO(PB2); B1 GPO(PB1); B0 GPO(PB0); 98 */ 99 __raw_writew(0x5555, PORT_PBCR); /* 01 01 01 01 01 01 01 01 */ 100 101 /* C7 GPO(PC7); C6 GPO(PC6); C5 GPO(PC5); C4 GPO(PC4); 102 * C3 LCD_DATA3; C2 LCD_DATA2; C1 LCD_DATA1; C0 LCD_DATA0; 103 */ 104 __raw_writew(0x5500, PORT_PCCR); /* 01 01 01 01 00 00 00 00 */ 105 106 /* D7 GPO(PD7); D6 GPO(PD6); D5 GPO(PD5); D4 GPO(PD4); 107 * D3 GPO(PD3); D2 GPO(PD2); D1 GPO(PD1); D0 GPO(PD0); 108 */ 109 __raw_writew(0x5555, PORT_PDCR); /* 01 01 01 01 01 01 01 01 */ 110 111 /* E7 (x); E6 GPI(nu); E5 GPI(nu); E4 LCD_M_DISP; 112 * E3 LCD_CL1; E2 LCD_CL2; E1 LCD_DON; E0 LCD_FLM; 113 */ 114 __raw_writew(0x3C00, PORT_PECR); /* 00 11 11 00 00 00 00 00 */ 115 116 /* F7 (x); F6 DA1(VLCD); F5 DA0(nc); F4 AN3; 117 * F3 AN2(MID_AD); F2 AN1(EARTH_AD); F1 AN0(TEMP); F0 GPI+(nc); 118 */ 119 __raw_writew(0x0002, PORT_PFCR); /* 00 00 00 00 00 00 00 10 */ 120 121 /* G7 (x); G6 IRQ5(TOUCH_BUSY); G5 IRQ4(TOUCH_IRQ); G4 GPI(KEY2); 122 * G3 GPI(KEY1); G2 GPO(LED11); G1 GPO(LED10); G0 GPO(LED9); 123 */ 124 __raw_writew(0x03D5, PORT_PGCR); /* 00 00 00 11 11 01 01 01 */ 125 126 /* H7 (x); H6 /RAS(BRAS); H5 /CAS(BCAS); H4 CKE(BCKE); 127 * H3 GPO(EARTH_OFF); H2 GPO(EARTH_TEST); H1 USB2_PWR; H0 USB1_PWR; 128 */ 129 __raw_writew(0x0050, PORT_PHCR); /* 00 00 00 00 01 01 00 00 */ 130 131 /* J7 (x); J6 AUDCK; J5 ASEBRKAK; J4 AUDATA3; 132 * J3 AUDATA2; J2 AUDATA1; J1 AUDATA0; J0 AUDSYNC; 133 */ 134 __raw_writew(0x0000, PORT_PJCR); /* 00 00 00 00 00 00 00 00 */ 135 136 /* K7 (x); K6 (x); K5 (x); K4 (x); 137 * K3 PINT7(/PWR2); K2 PINT6(/PWR1); K1 PINT5(nu); K0 PINT4(FLASH_READY) 138 */ 139 __raw_writew(0x00FF, PORT_PKCR); /* 00 00 00 00 11 11 11 11 */ 140 141 /* L7 TRST; L6 TMS; L5 TDO; L4 TDI; 142 * L3 TCK; L2 (x); L1 (x); L0 (x); 143 */ 144 __raw_writew(0x0000, PORT_PLCR); /* 00 00 00 00 00 00 00 00 */ 145 146 /* M7 GPO(CURRENT_SINK); M6 GPO(PWR_SWITCH); M5 GPO(LAN_SPEED); 147 * M4 GPO(LAN_RESET); M3 GPO(BUZZER); M2 GPO(LCD_BL); 148 * M1 CS5B(CAN3_CS); M0 GPI+(nc); 149 */ 150 __raw_writew(0x5552, PORT_PMCR); /* 01 01 01 01 01 01 00 10 */ 151 152 /* CURRENT_SINK=off, PWR_SWITCH=off, LAN_SPEED=100MBit, 153 * LAN_RESET=off, BUZZER=off, LCD_BL=off 154 */ 155 #if CONFIG_SH_MAGIC_PANEL_R2_VERSION == 2 156 __raw_writeb(0x30, PORT_PMDR); 157 #elif CONFIG_SH_MAGIC_PANEL_R2_VERSION == 3 158 __raw_writeb(0xF0, PORT_PMDR); 159 #else 160 #error Unknown revision of PLATFORM_MP_R2 161 #endif 162 163 /* P7 (x); P6 (x); P5 (x); 164 * P4 GPO(nu); P3 IRQ3(LAN_IRQ); P2 IRQ2(CAN3_IRQ); 165 * P1 IRQ1(CAN2_IRQ); P0 IRQ0(CAN1_IRQ) 166 */ 167 __raw_writew(0x0100, PORT_PPCR); /* 00 00 00 01 00 00 00 00 */ 168 __raw_writeb(0x10, PORT_PPDR); 169 170 /* R7 A25; R6 A24; R5 A23; R4 A22; 171 * R3 A21; R2 A20; R1 A19; R0 A0; 172 */ 173 gpio_request(GPIO_FN_A25, NULL); 174 gpio_request(GPIO_FN_A24, NULL); 175 gpio_request(GPIO_FN_A23, NULL); 176 gpio_request(GPIO_FN_A22, NULL); 177 gpio_request(GPIO_FN_A21, NULL); 178 gpio_request(GPIO_FN_A20, NULL); 179 gpio_request(GPIO_FN_A19, NULL); 180 gpio_request(GPIO_FN_A0, NULL); 181 182 /* S7 (x); S6 (x); S5 (x); S4 GPO(EEPROM_CS2); 183 * S3 GPO(EEPROM_CS1); S2 SIOF0_TXD; S1 SIOF0_RXD; S0 SIOF0_SCK; 184 */ 185 __raw_writew(0x0140, PORT_PSCR); /* 00 00 00 01 01 00 00 00 */ 186 187 /* T7 (x); T6 (x); T5 (x); T4 COM1_CTS; 188 * T3 COM1_RTS; T2 COM1_TXD; T1 COM1_RXD; T0 GPO(WDOG) 189 */ 190 __raw_writew(0x0001, PORT_PTCR); /* 00 00 00 00 00 00 00 01 */ 191 192 /* U7 (x); U6 (x); U5 (x); U4 GPI+(/AC_FAULT); 193 * U3 GPO(TOUCH_CS); U2 TOUCH_TXD; U1 TOUCH_RXD; U0 TOUCH_SCK; 194 */ 195 __raw_writew(0x0240, PORT_PUCR); /* 00 00 00 10 01 00 00 00 */ 196 197 /* V7 (x); V6 (x); V5 (x); V4 GPO(MID2); 198 * V3 GPO(MID1); V2 CARD_TxD; V1 CARD_RxD; V0 GPI+(/BAT_FAULT); 199 */ 200 __raw_writew(0x0142, PORT_PVCR); /* 00 00 00 01 01 00 00 10 */ 201 } 202 203 static void __init mpr2_setup(char **cmdline_p) 204 { 205 /* set Pin Select Register A: 206 * /PCC_CD1, /PCC_CD2, PCC_BVD1, PCC_BVD2, 207 * /IOIS16, IRQ4, IRQ5, USB1d_SUSPEND 208 */ 209 __raw_writew(0xAABC, PORT_PSELA); 210 /* set Pin Select Register B: 211 * /SCIF0_RTS, /SCIF0_CTS, LCD_VCPWC, 212 * LCD_VEPWC, IIC_SDA, IIC_SCL, Reserved 213 */ 214 __raw_writew(0x3C00, PORT_PSELB); 215 /* set Pin Select Register C: 216 * SIOF1_SCK, SIOF1_RxD, SCIF1_RxD, SCIF1_TxD, Reserved 217 */ 218 __raw_writew(0x0000, PORT_PSELC); 219 /* set Pin Select Register D: Reserved, SIOF1_TxD, Reserved, SIOF1_MCLK, 220 * Reserved, SIOF1_SYNC, Reserved, SCIF1_SCK, Reserved 221 */ 222 __raw_writew(0x0000, PORT_PSELD); 223 /* set USB TxRx Control: Reserved, DRV, Reserved, USB_TRANS, USB_SEL */ 224 __raw_writew(0x0101, PORT_UTRCTL); 225 /* set USB Clock Control: USSCS, USSTB, Reserved (HighByte always A5) */ 226 __raw_writew(0xA5C0, PORT_UCLKCR_W); 227 228 setup_chip_select(); 229 230 setup_port_multiplexing(); 231 232 reset_ethernet(); 233 234 printk(KERN_INFO "Magic Panel Release 2 A.%i\n", 235 CONFIG_SH_MAGIC_PANEL_R2_VERSION); 236 237 if (ethernet_reset_finished() == 0) 238 printk(KERN_WARNING "Ethernet not ready\n"); 239 } 240 241 static struct resource smsc911x_resources[] = { 242 [0] = { 243 .start = 0xa8000000, 244 .end = 0xabffffff, 245 .flags = IORESOURCE_MEM, 246 }, 247 [1] = { 248 .start = 35, 249 .end = 35, 250 .flags = IORESOURCE_IRQ, 251 }, 252 }; 253 254 static struct smsc911x_platform_config smsc911x_config = { 255 .phy_interface = PHY_INTERFACE_MODE_MII, 256 .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW, 257 .irq_type = SMSC911X_IRQ_TYPE_OPEN_DRAIN, 258 .flags = SMSC911X_USE_32BIT, 259 }; 260 261 static struct platform_device smsc911x_device = { 262 .name = "smsc911x", 263 .id = -1, 264 .num_resources = ARRAY_SIZE(smsc911x_resources), 265 .resource = smsc911x_resources, 266 .dev = { 267 .platform_data = &smsc911x_config, 268 }, 269 }; 270 271 static struct resource heartbeat_resources[] = { 272 [0] = { 273 .start = PA_LED, 274 .end = PA_LED, 275 .flags = IORESOURCE_MEM, 276 }, 277 }; 278 279 static struct heartbeat_data heartbeat_data = { 280 .flags = HEARTBEAT_INVERTED, 281 }; 282 283 static struct platform_device heartbeat_device = { 284 .name = "heartbeat", 285 .id = -1, 286 .dev = { 287 .platform_data = &heartbeat_data, 288 }, 289 .num_resources = ARRAY_SIZE(heartbeat_resources), 290 .resource = heartbeat_resources, 291 }; 292 293 static struct mtd_partition mpr2_partitions[] = { 294 /* Reserved for bootloader, read-only */ 295 { 296 .name = "Bootloader", 297 .offset = 0x00000000UL, 298 .size = MPR2_MTD_BOOTLOADER_SIZE, 299 .mask_flags = MTD_WRITEABLE, 300 }, 301 /* Reserved for kernel image */ 302 { 303 .name = "Kernel", 304 .offset = MTDPART_OFS_NXTBLK, 305 .size = MPR2_MTD_KERNEL_SIZE, 306 }, 307 /* Rest is used for Flash FS */ 308 { 309 .name = "Flash_FS", 310 .offset = MTDPART_OFS_NXTBLK, 311 .size = MTDPART_SIZ_FULL, 312 } 313 }; 314 315 static struct physmap_flash_data flash_data = { 316 .parts = mpr2_partitions, 317 .nr_parts = ARRAY_SIZE(mpr2_partitions), 318 .width = 2, 319 }; 320 321 static struct resource flash_resource = { 322 .start = 0x00000000, 323 .end = 0x2000000UL, 324 .flags = IORESOURCE_MEM, 325 }; 326 327 static struct platform_device flash_device = { 328 .name = "physmap-flash", 329 .id = -1, 330 .resource = &flash_resource, 331 .num_resources = 1, 332 .dev = { 333 .platform_data = &flash_data, 334 }, 335 }; 336 337 /* 338 * Add all resources to the platform_device 339 */ 340 341 static struct platform_device *mpr2_devices[] __initdata = { 342 &heartbeat_device, 343 &smsc911x_device, 344 &flash_device, 345 }; 346 347 348 static int __init mpr2_devices_setup(void) 349 { 350 return platform_add_devices(mpr2_devices, ARRAY_SIZE(mpr2_devices)); 351 } 352 device_initcall(mpr2_devices_setup); 353 354 /* 355 * Initialize IRQ setting 356 */ 357 static void __init init_mpr2_IRQ(void) 358 { 359 plat_irq_setup_pins(IRQ_MODE_IRQ); /* install handlers for IRQ0-5 */ 360 361 irq_set_irq_type(32, IRQ_TYPE_LEVEL_LOW); /* IRQ0 CAN1 */ 362 irq_set_irq_type(33, IRQ_TYPE_LEVEL_LOW); /* IRQ1 CAN2 */ 363 irq_set_irq_type(34, IRQ_TYPE_LEVEL_LOW); /* IRQ2 CAN3 */ 364 irq_set_irq_type(35, IRQ_TYPE_LEVEL_LOW); /* IRQ3 SMSC9115 */ 365 irq_set_irq_type(36, IRQ_TYPE_EDGE_RISING); /* IRQ4 touchscreen */ 366 irq_set_irq_type(37, IRQ_TYPE_EDGE_FALLING); /* IRQ5 touchscreen */ 367 368 intc_set_priority(32, 13); /* IRQ0 CAN1 */ 369 intc_set_priority(33, 13); /* IRQ0 CAN2 */ 370 intc_set_priority(34, 13); /* IRQ0 CAN3 */ 371 intc_set_priority(35, 6); /* IRQ3 SMSC9115 */ 372 } 373 374 /* 375 * The Machine Vector 376 */ 377 378 static struct sh_machine_vector mv_mpr2 __initmv = { 379 .mv_name = "mpr2", 380 .mv_setup = mpr2_setup, 381 .mv_init_irq = init_mpr2_IRQ, 382 }; 383