1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * BPF Jit compiler for s390. 4 * 5 * Minimum build requirements: 6 * 7 * - HAVE_MARCH_Z196_FEATURES: laal, laalg 8 * - HAVE_MARCH_Z10_FEATURES: msfi, cgrj, clgrj 9 * - HAVE_MARCH_Z9_109_FEATURES: alfi, llilf, clfi, oilf, nilf 10 * - PACK_STACK 11 * - 64BIT 12 * 13 * Copyright IBM Corp. 2012,2015 14 * 15 * Author(s): Martin Schwidefsky <schwidefsky@de.ibm.com> 16 * Michael Holzheu <holzheu@linux.vnet.ibm.com> 17 */ 18 19 #define KMSG_COMPONENT "bpf_jit" 20 #define pr_fmt(fmt) KMSG_COMPONENT ": " fmt 21 22 #include <linux/netdevice.h> 23 #include <linux/filter.h> 24 #include <linux/init.h> 25 #include <linux/bpf.h> 26 #include <asm/cacheflush.h> 27 #include <asm/dis.h> 28 #include <asm/facility.h> 29 #include <asm/nospec-branch.h> 30 #include <asm/set_memory.h> 31 #include "bpf_jit.h" 32 33 struct bpf_jit { 34 u32 seen; /* Flags to remember seen eBPF instructions */ 35 u32 seen_reg[16]; /* Array to remember which registers are used */ 36 u32 *addrs; /* Array with relative instruction addresses */ 37 u8 *prg_buf; /* Start of program */ 38 int size; /* Size of program and literal pool */ 39 int size_prg; /* Size of program */ 40 int prg; /* Current position in program */ 41 int lit_start; /* Start of literal pool */ 42 int lit; /* Current position in literal pool */ 43 int base_ip; /* Base address for literal pool */ 44 int ret0_ip; /* Address of return 0 */ 45 int exit_ip; /* Address of exit */ 46 int r1_thunk_ip; /* Address of expoline thunk for 'br %r1' */ 47 int r14_thunk_ip; /* Address of expoline thunk for 'br %r14' */ 48 int tail_call_start; /* Tail call start offset */ 49 int labels[1]; /* Labels for local jumps */ 50 }; 51 52 #define BPF_SIZE_MAX 0xffff /* Max size for program (16 bit branches) */ 53 54 #define SEEN_MEM (1 << 0) /* use mem[] for temporary storage */ 55 #define SEEN_RET0 (1 << 1) /* ret0_ip points to a valid return 0 */ 56 #define SEEN_LITERAL (1 << 2) /* code uses literals */ 57 #define SEEN_FUNC (1 << 3) /* calls C functions */ 58 #define SEEN_TAIL_CALL (1 << 4) /* code uses tail calls */ 59 #define SEEN_REG_AX (1 << 5) /* code uses constant blinding */ 60 #define SEEN_STACK (SEEN_FUNC | SEEN_MEM) 61 62 /* 63 * s390 registers 64 */ 65 #define REG_W0 (MAX_BPF_JIT_REG + 0) /* Work register 1 (even) */ 66 #define REG_W1 (MAX_BPF_JIT_REG + 1) /* Work register 2 (odd) */ 67 #define REG_L (MAX_BPF_JIT_REG + 2) /* Literal pool register */ 68 #define REG_15 (MAX_BPF_JIT_REG + 3) /* Register 15 */ 69 #define REG_0 REG_W0 /* Register 0 */ 70 #define REG_1 REG_W1 /* Register 1 */ 71 #define REG_2 BPF_REG_1 /* Register 2 */ 72 #define REG_14 BPF_REG_0 /* Register 14 */ 73 74 /* 75 * Mapping of BPF registers to s390 registers 76 */ 77 static const int reg2hex[] = { 78 /* Return code */ 79 [BPF_REG_0] = 14, 80 /* Function parameters */ 81 [BPF_REG_1] = 2, 82 [BPF_REG_2] = 3, 83 [BPF_REG_3] = 4, 84 [BPF_REG_4] = 5, 85 [BPF_REG_5] = 6, 86 /* Call saved registers */ 87 [BPF_REG_6] = 7, 88 [BPF_REG_7] = 8, 89 [BPF_REG_8] = 9, 90 [BPF_REG_9] = 10, 91 /* BPF stack pointer */ 92 [BPF_REG_FP] = 13, 93 /* Register for blinding */ 94 [BPF_REG_AX] = 12, 95 /* Work registers for s390x backend */ 96 [REG_W0] = 0, 97 [REG_W1] = 1, 98 [REG_L] = 11, 99 [REG_15] = 15, 100 }; 101 102 static inline u32 reg(u32 dst_reg, u32 src_reg) 103 { 104 return reg2hex[dst_reg] << 4 | reg2hex[src_reg]; 105 } 106 107 static inline u32 reg_high(u32 reg) 108 { 109 return reg2hex[reg] << 4; 110 } 111 112 static inline void reg_set_seen(struct bpf_jit *jit, u32 b1) 113 { 114 u32 r1 = reg2hex[b1]; 115 116 if (!jit->seen_reg[r1] && r1 >= 6 && r1 <= 15) 117 jit->seen_reg[r1] = 1; 118 } 119 120 #define REG_SET_SEEN(b1) \ 121 ({ \ 122 reg_set_seen(jit, b1); \ 123 }) 124 125 #define REG_SEEN(b1) jit->seen_reg[reg2hex[(b1)]] 126 127 /* 128 * EMIT macros for code generation 129 */ 130 131 #define _EMIT2(op) \ 132 ({ \ 133 if (jit->prg_buf) \ 134 *(u16 *) (jit->prg_buf + jit->prg) = op; \ 135 jit->prg += 2; \ 136 }) 137 138 #define EMIT2(op, b1, b2) \ 139 ({ \ 140 _EMIT2(op | reg(b1, b2)); \ 141 REG_SET_SEEN(b1); \ 142 REG_SET_SEEN(b2); \ 143 }) 144 145 #define _EMIT4(op) \ 146 ({ \ 147 if (jit->prg_buf) \ 148 *(u32 *) (jit->prg_buf + jit->prg) = op; \ 149 jit->prg += 4; \ 150 }) 151 152 #define EMIT4(op, b1, b2) \ 153 ({ \ 154 _EMIT4(op | reg(b1, b2)); \ 155 REG_SET_SEEN(b1); \ 156 REG_SET_SEEN(b2); \ 157 }) 158 159 #define EMIT4_RRF(op, b1, b2, b3) \ 160 ({ \ 161 _EMIT4(op | reg_high(b3) << 8 | reg(b1, b2)); \ 162 REG_SET_SEEN(b1); \ 163 REG_SET_SEEN(b2); \ 164 REG_SET_SEEN(b3); \ 165 }) 166 167 #define _EMIT4_DISP(op, disp) \ 168 ({ \ 169 unsigned int __disp = (disp) & 0xfff; \ 170 _EMIT4(op | __disp); \ 171 }) 172 173 #define EMIT4_DISP(op, b1, b2, disp) \ 174 ({ \ 175 _EMIT4_DISP(op | reg_high(b1) << 16 | \ 176 reg_high(b2) << 8, disp); \ 177 REG_SET_SEEN(b1); \ 178 REG_SET_SEEN(b2); \ 179 }) 180 181 #define EMIT4_IMM(op, b1, imm) \ 182 ({ \ 183 unsigned int __imm = (imm) & 0xffff; \ 184 _EMIT4(op | reg_high(b1) << 16 | __imm); \ 185 REG_SET_SEEN(b1); \ 186 }) 187 188 #define EMIT4_PCREL(op, pcrel) \ 189 ({ \ 190 long __pcrel = ((pcrel) >> 1) & 0xffff; \ 191 _EMIT4(op | __pcrel); \ 192 }) 193 194 #define _EMIT6(op1, op2) \ 195 ({ \ 196 if (jit->prg_buf) { \ 197 *(u32 *) (jit->prg_buf + jit->prg) = op1; \ 198 *(u16 *) (jit->prg_buf + jit->prg + 4) = op2; \ 199 } \ 200 jit->prg += 6; \ 201 }) 202 203 #define _EMIT6_DISP(op1, op2, disp) \ 204 ({ \ 205 unsigned int __disp = (disp) & 0xfff; \ 206 _EMIT6(op1 | __disp, op2); \ 207 }) 208 209 #define _EMIT6_DISP_LH(op1, op2, disp) \ 210 ({ \ 211 u32 _disp = (u32) disp; \ 212 unsigned int __disp_h = _disp & 0xff000; \ 213 unsigned int __disp_l = _disp & 0x00fff; \ 214 _EMIT6(op1 | __disp_l, op2 | __disp_h >> 4); \ 215 }) 216 217 #define EMIT6_DISP_LH(op1, op2, b1, b2, b3, disp) \ 218 ({ \ 219 _EMIT6_DISP_LH(op1 | reg(b1, b2) << 16 | \ 220 reg_high(b3) << 8, op2, disp); \ 221 REG_SET_SEEN(b1); \ 222 REG_SET_SEEN(b2); \ 223 REG_SET_SEEN(b3); \ 224 }) 225 226 #define EMIT6_PCREL_LABEL(op1, op2, b1, b2, label, mask) \ 227 ({ \ 228 int rel = (jit->labels[label] - jit->prg) >> 1; \ 229 _EMIT6(op1 | reg(b1, b2) << 16 | (rel & 0xffff), \ 230 op2 | mask << 12); \ 231 REG_SET_SEEN(b1); \ 232 REG_SET_SEEN(b2); \ 233 }) 234 235 #define EMIT6_PCREL_IMM_LABEL(op1, op2, b1, imm, label, mask) \ 236 ({ \ 237 int rel = (jit->labels[label] - jit->prg) >> 1; \ 238 _EMIT6(op1 | (reg_high(b1) | mask) << 16 | \ 239 (rel & 0xffff), op2 | (imm & 0xff) << 8); \ 240 REG_SET_SEEN(b1); \ 241 BUILD_BUG_ON(((unsigned long) imm) > 0xff); \ 242 }) 243 244 #define EMIT6_PCREL(op1, op2, b1, b2, i, off, mask) \ 245 ({ \ 246 /* Branch instruction needs 6 bytes */ \ 247 int rel = (addrs[i + off + 1] - (addrs[i + 1] - 6)) / 2;\ 248 _EMIT6(op1 | reg(b1, b2) << 16 | (rel & 0xffff), op2 | mask); \ 249 REG_SET_SEEN(b1); \ 250 REG_SET_SEEN(b2); \ 251 }) 252 253 #define EMIT6_PCREL_RILB(op, b, target) \ 254 ({ \ 255 int rel = (target - jit->prg) / 2; \ 256 _EMIT6(op | reg_high(b) << 16 | rel >> 16, rel & 0xffff); \ 257 REG_SET_SEEN(b); \ 258 }) 259 260 #define EMIT6_PCREL_RIL(op, target) \ 261 ({ \ 262 int rel = (target - jit->prg) / 2; \ 263 _EMIT6(op | rel >> 16, rel & 0xffff); \ 264 }) 265 266 #define _EMIT6_IMM(op, imm) \ 267 ({ \ 268 unsigned int __imm = (imm); \ 269 _EMIT6(op | (__imm >> 16), __imm & 0xffff); \ 270 }) 271 272 #define EMIT6_IMM(op, b1, imm) \ 273 ({ \ 274 _EMIT6_IMM(op | reg_high(b1) << 16, imm); \ 275 REG_SET_SEEN(b1); \ 276 }) 277 278 #define EMIT_CONST_U32(val) \ 279 ({ \ 280 unsigned int ret; \ 281 ret = jit->lit - jit->base_ip; \ 282 jit->seen |= SEEN_LITERAL; \ 283 if (jit->prg_buf) \ 284 *(u32 *) (jit->prg_buf + jit->lit) = (u32) val; \ 285 jit->lit += 4; \ 286 ret; \ 287 }) 288 289 #define EMIT_CONST_U64(val) \ 290 ({ \ 291 unsigned int ret; \ 292 ret = jit->lit - jit->base_ip; \ 293 jit->seen |= SEEN_LITERAL; \ 294 if (jit->prg_buf) \ 295 *(u64 *) (jit->prg_buf + jit->lit) = (u64) val; \ 296 jit->lit += 8; \ 297 ret; \ 298 }) 299 300 #define EMIT_ZERO(b1) \ 301 ({ \ 302 /* llgfr %dst,%dst (zero extend to 64 bit) */ \ 303 EMIT4(0xb9160000, b1, b1); \ 304 REG_SET_SEEN(b1); \ 305 }) 306 307 /* 308 * Fill whole space with illegal instructions 309 */ 310 static void jit_fill_hole(void *area, unsigned int size) 311 { 312 memset(area, 0, size); 313 } 314 315 /* 316 * Save registers from "rs" (register start) to "re" (register end) on stack 317 */ 318 static void save_regs(struct bpf_jit *jit, u32 rs, u32 re) 319 { 320 u32 off = STK_OFF_R6 + (rs - 6) * 8; 321 322 if (rs == re) 323 /* stg %rs,off(%r15) */ 324 _EMIT6(0xe300f000 | rs << 20 | off, 0x0024); 325 else 326 /* stmg %rs,%re,off(%r15) */ 327 _EMIT6_DISP(0xeb00f000 | rs << 20 | re << 16, 0x0024, off); 328 } 329 330 /* 331 * Restore registers from "rs" (register start) to "re" (register end) on stack 332 */ 333 static void restore_regs(struct bpf_jit *jit, u32 rs, u32 re, u32 stack_depth) 334 { 335 u32 off = STK_OFF_R6 + (rs - 6) * 8; 336 337 if (jit->seen & SEEN_STACK) 338 off += STK_OFF + stack_depth; 339 340 if (rs == re) 341 /* lg %rs,off(%r15) */ 342 _EMIT6(0xe300f000 | rs << 20 | off, 0x0004); 343 else 344 /* lmg %rs,%re,off(%r15) */ 345 _EMIT6_DISP(0xeb00f000 | rs << 20 | re << 16, 0x0004, off); 346 } 347 348 /* 349 * Return first seen register (from start) 350 */ 351 static int get_start(struct bpf_jit *jit, int start) 352 { 353 int i; 354 355 for (i = start; i <= 15; i++) { 356 if (jit->seen_reg[i]) 357 return i; 358 } 359 return 0; 360 } 361 362 /* 363 * Return last seen register (from start) (gap >= 2) 364 */ 365 static int get_end(struct bpf_jit *jit, int start) 366 { 367 int i; 368 369 for (i = start; i < 15; i++) { 370 if (!jit->seen_reg[i] && !jit->seen_reg[i + 1]) 371 return i - 1; 372 } 373 return jit->seen_reg[15] ? 15 : 14; 374 } 375 376 #define REGS_SAVE 1 377 #define REGS_RESTORE 0 378 /* 379 * Save and restore clobbered registers (6-15) on stack. 380 * We save/restore registers in chunks with gap >= 2 registers. 381 */ 382 static void save_restore_regs(struct bpf_jit *jit, int op, u32 stack_depth) 383 { 384 385 int re = 6, rs; 386 387 do { 388 rs = get_start(jit, re); 389 if (!rs) 390 break; 391 re = get_end(jit, rs + 1); 392 if (op == REGS_SAVE) 393 save_regs(jit, rs, re); 394 else 395 restore_regs(jit, rs, re, stack_depth); 396 re++; 397 } while (re <= 15); 398 } 399 400 /* 401 * Emit function prologue 402 * 403 * Save registers and create stack frame if necessary. 404 * See stack frame layout desription in "bpf_jit.h"! 405 */ 406 static void bpf_jit_prologue(struct bpf_jit *jit, u32 stack_depth) 407 { 408 if (jit->seen & SEEN_TAIL_CALL) { 409 /* xc STK_OFF_TCCNT(4,%r15),STK_OFF_TCCNT(%r15) */ 410 _EMIT6(0xd703f000 | STK_OFF_TCCNT, 0xf000 | STK_OFF_TCCNT); 411 } else { 412 /* j tail_call_start: NOP if no tail calls are used */ 413 EMIT4_PCREL(0xa7f40000, 6); 414 _EMIT2(0); 415 } 416 /* Tail calls have to skip above initialization */ 417 jit->tail_call_start = jit->prg; 418 /* Save registers */ 419 save_restore_regs(jit, REGS_SAVE, stack_depth); 420 /* Setup literal pool */ 421 if (jit->seen & SEEN_LITERAL) { 422 /* basr %r13,0 */ 423 EMIT2(0x0d00, REG_L, REG_0); 424 jit->base_ip = jit->prg; 425 } 426 /* Setup stack and backchain */ 427 if (jit->seen & SEEN_STACK) { 428 if (jit->seen & SEEN_FUNC) 429 /* lgr %w1,%r15 (backchain) */ 430 EMIT4(0xb9040000, REG_W1, REG_15); 431 /* la %bfp,STK_160_UNUSED(%r15) (BPF frame pointer) */ 432 EMIT4_DISP(0x41000000, BPF_REG_FP, REG_15, STK_160_UNUSED); 433 /* aghi %r15,-STK_OFF */ 434 EMIT4_IMM(0xa70b0000, REG_15, -(STK_OFF + stack_depth)); 435 if (jit->seen & SEEN_FUNC) 436 /* stg %w1,152(%r15) (backchain) */ 437 EMIT6_DISP_LH(0xe3000000, 0x0024, REG_W1, REG_0, 438 REG_15, 152); 439 } 440 } 441 442 /* 443 * Function epilogue 444 */ 445 static void bpf_jit_epilogue(struct bpf_jit *jit, u32 stack_depth) 446 { 447 /* Return 0 */ 448 if (jit->seen & SEEN_RET0) { 449 jit->ret0_ip = jit->prg; 450 /* lghi %b0,0 */ 451 EMIT4_IMM(0xa7090000, BPF_REG_0, 0); 452 } 453 jit->exit_ip = jit->prg; 454 /* Load exit code: lgr %r2,%b0 */ 455 EMIT4(0xb9040000, REG_2, BPF_REG_0); 456 /* Restore registers */ 457 save_restore_regs(jit, REGS_RESTORE, stack_depth); 458 if (IS_ENABLED(CC_USING_EXPOLINE) && !nospec_disable) { 459 jit->r14_thunk_ip = jit->prg; 460 /* Generate __s390_indirect_jump_r14 thunk */ 461 if (test_facility(35)) { 462 /* exrl %r0,.+10 */ 463 EMIT6_PCREL_RIL(0xc6000000, jit->prg + 10); 464 } else { 465 /* larl %r1,.+14 */ 466 EMIT6_PCREL_RILB(0xc0000000, REG_1, jit->prg + 14); 467 /* ex 0,0(%r1) */ 468 EMIT4_DISP(0x44000000, REG_0, REG_1, 0); 469 } 470 /* j . */ 471 EMIT4_PCREL(0xa7f40000, 0); 472 } 473 /* br %r14 */ 474 _EMIT2(0x07fe); 475 476 if (IS_ENABLED(CC_USING_EXPOLINE) && !nospec_disable && 477 (jit->seen & SEEN_FUNC)) { 478 jit->r1_thunk_ip = jit->prg; 479 /* Generate __s390_indirect_jump_r1 thunk */ 480 if (test_facility(35)) { 481 /* exrl %r0,.+10 */ 482 EMIT6_PCREL_RIL(0xc6000000, jit->prg + 10); 483 /* j . */ 484 EMIT4_PCREL(0xa7f40000, 0); 485 /* br %r1 */ 486 _EMIT2(0x07f1); 487 } else { 488 /* ex 0,S390_lowcore.br_r1_tampoline */ 489 EMIT4_DISP(0x44000000, REG_0, REG_0, 490 offsetof(struct lowcore, br_r1_trampoline)); 491 /* j . */ 492 EMIT4_PCREL(0xa7f40000, 0); 493 } 494 } 495 } 496 497 /* 498 * Compile one eBPF instruction into s390x code 499 * 500 * NOTE: Use noinline because for gcov (-fprofile-arcs) gcc allocates a lot of 501 * stack space for the large switch statement. 502 */ 503 static noinline int bpf_jit_insn(struct bpf_jit *jit, struct bpf_prog *fp, int i) 504 { 505 struct bpf_insn *insn = &fp->insnsi[i]; 506 int jmp_off, last, insn_count = 1; 507 u32 dst_reg = insn->dst_reg; 508 u32 src_reg = insn->src_reg; 509 u32 *addrs = jit->addrs; 510 s32 imm = insn->imm; 511 s16 off = insn->off; 512 unsigned int mask; 513 514 if (dst_reg == BPF_REG_AX || src_reg == BPF_REG_AX) 515 jit->seen |= SEEN_REG_AX; 516 switch (insn->code) { 517 /* 518 * BPF_MOV 519 */ 520 case BPF_ALU | BPF_MOV | BPF_X: /* dst = (u32) src */ 521 /* llgfr %dst,%src */ 522 EMIT4(0xb9160000, dst_reg, src_reg); 523 break; 524 case BPF_ALU64 | BPF_MOV | BPF_X: /* dst = src */ 525 /* lgr %dst,%src */ 526 EMIT4(0xb9040000, dst_reg, src_reg); 527 break; 528 case BPF_ALU | BPF_MOV | BPF_K: /* dst = (u32) imm */ 529 /* llilf %dst,imm */ 530 EMIT6_IMM(0xc00f0000, dst_reg, imm); 531 break; 532 case BPF_ALU64 | BPF_MOV | BPF_K: /* dst = imm */ 533 /* lgfi %dst,imm */ 534 EMIT6_IMM(0xc0010000, dst_reg, imm); 535 break; 536 /* 537 * BPF_LD 64 538 */ 539 case BPF_LD | BPF_IMM | BPF_DW: /* dst = (u64) imm */ 540 { 541 /* 16 byte instruction that uses two 'struct bpf_insn' */ 542 u64 imm64; 543 544 imm64 = (u64)(u32) insn[0].imm | ((u64)(u32) insn[1].imm) << 32; 545 /* lg %dst,<d(imm)>(%l) */ 546 EMIT6_DISP_LH(0xe3000000, 0x0004, dst_reg, REG_0, REG_L, 547 EMIT_CONST_U64(imm64)); 548 insn_count = 2; 549 break; 550 } 551 /* 552 * BPF_ADD 553 */ 554 case BPF_ALU | BPF_ADD | BPF_X: /* dst = (u32) dst + (u32) src */ 555 /* ar %dst,%src */ 556 EMIT2(0x1a00, dst_reg, src_reg); 557 EMIT_ZERO(dst_reg); 558 break; 559 case BPF_ALU64 | BPF_ADD | BPF_X: /* dst = dst + src */ 560 /* agr %dst,%src */ 561 EMIT4(0xb9080000, dst_reg, src_reg); 562 break; 563 case BPF_ALU | BPF_ADD | BPF_K: /* dst = (u32) dst + (u32) imm */ 564 if (!imm) 565 break; 566 /* alfi %dst,imm */ 567 EMIT6_IMM(0xc20b0000, dst_reg, imm); 568 EMIT_ZERO(dst_reg); 569 break; 570 case BPF_ALU64 | BPF_ADD | BPF_K: /* dst = dst + imm */ 571 if (!imm) 572 break; 573 /* agfi %dst,imm */ 574 EMIT6_IMM(0xc2080000, dst_reg, imm); 575 break; 576 /* 577 * BPF_SUB 578 */ 579 case BPF_ALU | BPF_SUB | BPF_X: /* dst = (u32) dst - (u32) src */ 580 /* sr %dst,%src */ 581 EMIT2(0x1b00, dst_reg, src_reg); 582 EMIT_ZERO(dst_reg); 583 break; 584 case BPF_ALU64 | BPF_SUB | BPF_X: /* dst = dst - src */ 585 /* sgr %dst,%src */ 586 EMIT4(0xb9090000, dst_reg, src_reg); 587 break; 588 case BPF_ALU | BPF_SUB | BPF_K: /* dst = (u32) dst - (u32) imm */ 589 if (!imm) 590 break; 591 /* alfi %dst,-imm */ 592 EMIT6_IMM(0xc20b0000, dst_reg, -imm); 593 EMIT_ZERO(dst_reg); 594 break; 595 case BPF_ALU64 | BPF_SUB | BPF_K: /* dst = dst - imm */ 596 if (!imm) 597 break; 598 /* agfi %dst,-imm */ 599 EMIT6_IMM(0xc2080000, dst_reg, -imm); 600 break; 601 /* 602 * BPF_MUL 603 */ 604 case BPF_ALU | BPF_MUL | BPF_X: /* dst = (u32) dst * (u32) src */ 605 /* msr %dst,%src */ 606 EMIT4(0xb2520000, dst_reg, src_reg); 607 EMIT_ZERO(dst_reg); 608 break; 609 case BPF_ALU64 | BPF_MUL | BPF_X: /* dst = dst * src */ 610 /* msgr %dst,%src */ 611 EMIT4(0xb90c0000, dst_reg, src_reg); 612 break; 613 case BPF_ALU | BPF_MUL | BPF_K: /* dst = (u32) dst * (u32) imm */ 614 if (imm == 1) 615 break; 616 /* msfi %r5,imm */ 617 EMIT6_IMM(0xc2010000, dst_reg, imm); 618 EMIT_ZERO(dst_reg); 619 break; 620 case BPF_ALU64 | BPF_MUL | BPF_K: /* dst = dst * imm */ 621 if (imm == 1) 622 break; 623 /* msgfi %dst,imm */ 624 EMIT6_IMM(0xc2000000, dst_reg, imm); 625 break; 626 /* 627 * BPF_DIV / BPF_MOD 628 */ 629 case BPF_ALU | BPF_DIV | BPF_X: /* dst = (u32) dst / (u32) src */ 630 case BPF_ALU | BPF_MOD | BPF_X: /* dst = (u32) dst % (u32) src */ 631 { 632 int rc_reg = BPF_OP(insn->code) == BPF_DIV ? REG_W1 : REG_W0; 633 634 /* lhi %w0,0 */ 635 EMIT4_IMM(0xa7080000, REG_W0, 0); 636 /* lr %w1,%dst */ 637 EMIT2(0x1800, REG_W1, dst_reg); 638 /* dlr %w0,%src */ 639 EMIT4(0xb9970000, REG_W0, src_reg); 640 /* llgfr %dst,%rc */ 641 EMIT4(0xb9160000, dst_reg, rc_reg); 642 break; 643 } 644 case BPF_ALU64 | BPF_DIV | BPF_X: /* dst = dst / src */ 645 case BPF_ALU64 | BPF_MOD | BPF_X: /* dst = dst % src */ 646 { 647 int rc_reg = BPF_OP(insn->code) == BPF_DIV ? REG_W1 : REG_W0; 648 649 /* lghi %w0,0 */ 650 EMIT4_IMM(0xa7090000, REG_W0, 0); 651 /* lgr %w1,%dst */ 652 EMIT4(0xb9040000, REG_W1, dst_reg); 653 /* dlgr %w0,%dst */ 654 EMIT4(0xb9870000, REG_W0, src_reg); 655 /* lgr %dst,%rc */ 656 EMIT4(0xb9040000, dst_reg, rc_reg); 657 break; 658 } 659 case BPF_ALU | BPF_DIV | BPF_K: /* dst = (u32) dst / (u32) imm */ 660 case BPF_ALU | BPF_MOD | BPF_K: /* dst = (u32) dst % (u32) imm */ 661 { 662 int rc_reg = BPF_OP(insn->code) == BPF_DIV ? REG_W1 : REG_W0; 663 664 if (imm == 1) { 665 if (BPF_OP(insn->code) == BPF_MOD) 666 /* lhgi %dst,0 */ 667 EMIT4_IMM(0xa7090000, dst_reg, 0); 668 break; 669 } 670 /* lhi %w0,0 */ 671 EMIT4_IMM(0xa7080000, REG_W0, 0); 672 /* lr %w1,%dst */ 673 EMIT2(0x1800, REG_W1, dst_reg); 674 /* dl %w0,<d(imm)>(%l) */ 675 EMIT6_DISP_LH(0xe3000000, 0x0097, REG_W0, REG_0, REG_L, 676 EMIT_CONST_U32(imm)); 677 /* llgfr %dst,%rc */ 678 EMIT4(0xb9160000, dst_reg, rc_reg); 679 break; 680 } 681 case BPF_ALU64 | BPF_DIV | BPF_K: /* dst = dst / imm */ 682 case BPF_ALU64 | BPF_MOD | BPF_K: /* dst = dst % imm */ 683 { 684 int rc_reg = BPF_OP(insn->code) == BPF_DIV ? REG_W1 : REG_W0; 685 686 if (imm == 1) { 687 if (BPF_OP(insn->code) == BPF_MOD) 688 /* lhgi %dst,0 */ 689 EMIT4_IMM(0xa7090000, dst_reg, 0); 690 break; 691 } 692 /* lghi %w0,0 */ 693 EMIT4_IMM(0xa7090000, REG_W0, 0); 694 /* lgr %w1,%dst */ 695 EMIT4(0xb9040000, REG_W1, dst_reg); 696 /* dlg %w0,<d(imm)>(%l) */ 697 EMIT6_DISP_LH(0xe3000000, 0x0087, REG_W0, REG_0, REG_L, 698 EMIT_CONST_U64(imm)); 699 /* lgr %dst,%rc */ 700 EMIT4(0xb9040000, dst_reg, rc_reg); 701 break; 702 } 703 /* 704 * BPF_AND 705 */ 706 case BPF_ALU | BPF_AND | BPF_X: /* dst = (u32) dst & (u32) src */ 707 /* nr %dst,%src */ 708 EMIT2(0x1400, dst_reg, src_reg); 709 EMIT_ZERO(dst_reg); 710 break; 711 case BPF_ALU64 | BPF_AND | BPF_X: /* dst = dst & src */ 712 /* ngr %dst,%src */ 713 EMIT4(0xb9800000, dst_reg, src_reg); 714 break; 715 case BPF_ALU | BPF_AND | BPF_K: /* dst = (u32) dst & (u32) imm */ 716 /* nilf %dst,imm */ 717 EMIT6_IMM(0xc00b0000, dst_reg, imm); 718 EMIT_ZERO(dst_reg); 719 break; 720 case BPF_ALU64 | BPF_AND | BPF_K: /* dst = dst & imm */ 721 /* ng %dst,<d(imm)>(%l) */ 722 EMIT6_DISP_LH(0xe3000000, 0x0080, dst_reg, REG_0, REG_L, 723 EMIT_CONST_U64(imm)); 724 break; 725 /* 726 * BPF_OR 727 */ 728 case BPF_ALU | BPF_OR | BPF_X: /* dst = (u32) dst | (u32) src */ 729 /* or %dst,%src */ 730 EMIT2(0x1600, dst_reg, src_reg); 731 EMIT_ZERO(dst_reg); 732 break; 733 case BPF_ALU64 | BPF_OR | BPF_X: /* dst = dst | src */ 734 /* ogr %dst,%src */ 735 EMIT4(0xb9810000, dst_reg, src_reg); 736 break; 737 case BPF_ALU | BPF_OR | BPF_K: /* dst = (u32) dst | (u32) imm */ 738 /* oilf %dst,imm */ 739 EMIT6_IMM(0xc00d0000, dst_reg, imm); 740 EMIT_ZERO(dst_reg); 741 break; 742 case BPF_ALU64 | BPF_OR | BPF_K: /* dst = dst | imm */ 743 /* og %dst,<d(imm)>(%l) */ 744 EMIT6_DISP_LH(0xe3000000, 0x0081, dst_reg, REG_0, REG_L, 745 EMIT_CONST_U64(imm)); 746 break; 747 /* 748 * BPF_XOR 749 */ 750 case BPF_ALU | BPF_XOR | BPF_X: /* dst = (u32) dst ^ (u32) src */ 751 /* xr %dst,%src */ 752 EMIT2(0x1700, dst_reg, src_reg); 753 EMIT_ZERO(dst_reg); 754 break; 755 case BPF_ALU64 | BPF_XOR | BPF_X: /* dst = dst ^ src */ 756 /* xgr %dst,%src */ 757 EMIT4(0xb9820000, dst_reg, src_reg); 758 break; 759 case BPF_ALU | BPF_XOR | BPF_K: /* dst = (u32) dst ^ (u32) imm */ 760 if (!imm) 761 break; 762 /* xilf %dst,imm */ 763 EMIT6_IMM(0xc0070000, dst_reg, imm); 764 EMIT_ZERO(dst_reg); 765 break; 766 case BPF_ALU64 | BPF_XOR | BPF_K: /* dst = dst ^ imm */ 767 /* xg %dst,<d(imm)>(%l) */ 768 EMIT6_DISP_LH(0xe3000000, 0x0082, dst_reg, REG_0, REG_L, 769 EMIT_CONST_U64(imm)); 770 break; 771 /* 772 * BPF_LSH 773 */ 774 case BPF_ALU | BPF_LSH | BPF_X: /* dst = (u32) dst << (u32) src */ 775 /* sll %dst,0(%src) */ 776 EMIT4_DISP(0x89000000, dst_reg, src_reg, 0); 777 EMIT_ZERO(dst_reg); 778 break; 779 case BPF_ALU64 | BPF_LSH | BPF_X: /* dst = dst << src */ 780 /* sllg %dst,%dst,0(%src) */ 781 EMIT6_DISP_LH(0xeb000000, 0x000d, dst_reg, dst_reg, src_reg, 0); 782 break; 783 case BPF_ALU | BPF_LSH | BPF_K: /* dst = (u32) dst << (u32) imm */ 784 if (imm == 0) 785 break; 786 /* sll %dst,imm(%r0) */ 787 EMIT4_DISP(0x89000000, dst_reg, REG_0, imm); 788 EMIT_ZERO(dst_reg); 789 break; 790 case BPF_ALU64 | BPF_LSH | BPF_K: /* dst = dst << imm */ 791 if (imm == 0) 792 break; 793 /* sllg %dst,%dst,imm(%r0) */ 794 EMIT6_DISP_LH(0xeb000000, 0x000d, dst_reg, dst_reg, REG_0, imm); 795 break; 796 /* 797 * BPF_RSH 798 */ 799 case BPF_ALU | BPF_RSH | BPF_X: /* dst = (u32) dst >> (u32) src */ 800 /* srl %dst,0(%src) */ 801 EMIT4_DISP(0x88000000, dst_reg, src_reg, 0); 802 EMIT_ZERO(dst_reg); 803 break; 804 case BPF_ALU64 | BPF_RSH | BPF_X: /* dst = dst >> src */ 805 /* srlg %dst,%dst,0(%src) */ 806 EMIT6_DISP_LH(0xeb000000, 0x000c, dst_reg, dst_reg, src_reg, 0); 807 break; 808 case BPF_ALU | BPF_RSH | BPF_K: /* dst = (u32) dst >> (u32) imm */ 809 if (imm == 0) 810 break; 811 /* srl %dst,imm(%r0) */ 812 EMIT4_DISP(0x88000000, dst_reg, REG_0, imm); 813 EMIT_ZERO(dst_reg); 814 break; 815 case BPF_ALU64 | BPF_RSH | BPF_K: /* dst = dst >> imm */ 816 if (imm == 0) 817 break; 818 /* srlg %dst,%dst,imm(%r0) */ 819 EMIT6_DISP_LH(0xeb000000, 0x000c, dst_reg, dst_reg, REG_0, imm); 820 break; 821 /* 822 * BPF_ARSH 823 */ 824 case BPF_ALU | BPF_ARSH | BPF_X: /* ((s32) dst) >>= src */ 825 /* sra %dst,%dst,0(%src) */ 826 EMIT4_DISP(0x8a000000, dst_reg, src_reg, 0); 827 EMIT_ZERO(dst_reg); 828 break; 829 case BPF_ALU64 | BPF_ARSH | BPF_X: /* ((s64) dst) >>= src */ 830 /* srag %dst,%dst,0(%src) */ 831 EMIT6_DISP_LH(0xeb000000, 0x000a, dst_reg, dst_reg, src_reg, 0); 832 break; 833 case BPF_ALU | BPF_ARSH | BPF_K: /* ((s32) dst >> imm */ 834 if (imm == 0) 835 break; 836 /* sra %dst,imm(%r0) */ 837 EMIT4_DISP(0x8a000000, dst_reg, REG_0, imm); 838 EMIT_ZERO(dst_reg); 839 break; 840 case BPF_ALU64 | BPF_ARSH | BPF_K: /* ((s64) dst) >>= imm */ 841 if (imm == 0) 842 break; 843 /* srag %dst,%dst,imm(%r0) */ 844 EMIT6_DISP_LH(0xeb000000, 0x000a, dst_reg, dst_reg, REG_0, imm); 845 break; 846 /* 847 * BPF_NEG 848 */ 849 case BPF_ALU | BPF_NEG: /* dst = (u32) -dst */ 850 /* lcr %dst,%dst */ 851 EMIT2(0x1300, dst_reg, dst_reg); 852 EMIT_ZERO(dst_reg); 853 break; 854 case BPF_ALU64 | BPF_NEG: /* dst = -dst */ 855 /* lcgr %dst,%dst */ 856 EMIT4(0xb9130000, dst_reg, dst_reg); 857 break; 858 /* 859 * BPF_FROM_BE/LE 860 */ 861 case BPF_ALU | BPF_END | BPF_FROM_BE: 862 /* s390 is big endian, therefore only clear high order bytes */ 863 switch (imm) { 864 case 16: /* dst = (u16) cpu_to_be16(dst) */ 865 /* llghr %dst,%dst */ 866 EMIT4(0xb9850000, dst_reg, dst_reg); 867 break; 868 case 32: /* dst = (u32) cpu_to_be32(dst) */ 869 /* llgfr %dst,%dst */ 870 EMIT4(0xb9160000, dst_reg, dst_reg); 871 break; 872 case 64: /* dst = (u64) cpu_to_be64(dst) */ 873 break; 874 } 875 break; 876 case BPF_ALU | BPF_END | BPF_FROM_LE: 877 switch (imm) { 878 case 16: /* dst = (u16) cpu_to_le16(dst) */ 879 /* lrvr %dst,%dst */ 880 EMIT4(0xb91f0000, dst_reg, dst_reg); 881 /* srl %dst,16(%r0) */ 882 EMIT4_DISP(0x88000000, dst_reg, REG_0, 16); 883 /* llghr %dst,%dst */ 884 EMIT4(0xb9850000, dst_reg, dst_reg); 885 break; 886 case 32: /* dst = (u32) cpu_to_le32(dst) */ 887 /* lrvr %dst,%dst */ 888 EMIT4(0xb91f0000, dst_reg, dst_reg); 889 /* llgfr %dst,%dst */ 890 EMIT4(0xb9160000, dst_reg, dst_reg); 891 break; 892 case 64: /* dst = (u64) cpu_to_le64(dst) */ 893 /* lrvgr %dst,%dst */ 894 EMIT4(0xb90f0000, dst_reg, dst_reg); 895 break; 896 } 897 break; 898 /* 899 * BPF_ST(X) 900 */ 901 case BPF_STX | BPF_MEM | BPF_B: /* *(u8 *)(dst + off) = src_reg */ 902 /* stcy %src,off(%dst) */ 903 EMIT6_DISP_LH(0xe3000000, 0x0072, src_reg, dst_reg, REG_0, off); 904 jit->seen |= SEEN_MEM; 905 break; 906 case BPF_STX | BPF_MEM | BPF_H: /* (u16 *)(dst + off) = src */ 907 /* sthy %src,off(%dst) */ 908 EMIT6_DISP_LH(0xe3000000, 0x0070, src_reg, dst_reg, REG_0, off); 909 jit->seen |= SEEN_MEM; 910 break; 911 case BPF_STX | BPF_MEM | BPF_W: /* *(u32 *)(dst + off) = src */ 912 /* sty %src,off(%dst) */ 913 EMIT6_DISP_LH(0xe3000000, 0x0050, src_reg, dst_reg, REG_0, off); 914 jit->seen |= SEEN_MEM; 915 break; 916 case BPF_STX | BPF_MEM | BPF_DW: /* (u64 *)(dst + off) = src */ 917 /* stg %src,off(%dst) */ 918 EMIT6_DISP_LH(0xe3000000, 0x0024, src_reg, dst_reg, REG_0, off); 919 jit->seen |= SEEN_MEM; 920 break; 921 case BPF_ST | BPF_MEM | BPF_B: /* *(u8 *)(dst + off) = imm */ 922 /* lhi %w0,imm */ 923 EMIT4_IMM(0xa7080000, REG_W0, (u8) imm); 924 /* stcy %w0,off(dst) */ 925 EMIT6_DISP_LH(0xe3000000, 0x0072, REG_W0, dst_reg, REG_0, off); 926 jit->seen |= SEEN_MEM; 927 break; 928 case BPF_ST | BPF_MEM | BPF_H: /* (u16 *)(dst + off) = imm */ 929 /* lhi %w0,imm */ 930 EMIT4_IMM(0xa7080000, REG_W0, (u16) imm); 931 /* sthy %w0,off(dst) */ 932 EMIT6_DISP_LH(0xe3000000, 0x0070, REG_W0, dst_reg, REG_0, off); 933 jit->seen |= SEEN_MEM; 934 break; 935 case BPF_ST | BPF_MEM | BPF_W: /* *(u32 *)(dst + off) = imm */ 936 /* llilf %w0,imm */ 937 EMIT6_IMM(0xc00f0000, REG_W0, (u32) imm); 938 /* sty %w0,off(%dst) */ 939 EMIT6_DISP_LH(0xe3000000, 0x0050, REG_W0, dst_reg, REG_0, off); 940 jit->seen |= SEEN_MEM; 941 break; 942 case BPF_ST | BPF_MEM | BPF_DW: /* *(u64 *)(dst + off) = imm */ 943 /* lgfi %w0,imm */ 944 EMIT6_IMM(0xc0010000, REG_W0, imm); 945 /* stg %w0,off(%dst) */ 946 EMIT6_DISP_LH(0xe3000000, 0x0024, REG_W0, dst_reg, REG_0, off); 947 jit->seen |= SEEN_MEM; 948 break; 949 /* 950 * BPF_STX XADD (atomic_add) 951 */ 952 case BPF_STX | BPF_XADD | BPF_W: /* *(u32 *)(dst + off) += src */ 953 /* laal %w0,%src,off(%dst) */ 954 EMIT6_DISP_LH(0xeb000000, 0x00fa, REG_W0, src_reg, 955 dst_reg, off); 956 jit->seen |= SEEN_MEM; 957 break; 958 case BPF_STX | BPF_XADD | BPF_DW: /* *(u64 *)(dst + off) += src */ 959 /* laalg %w0,%src,off(%dst) */ 960 EMIT6_DISP_LH(0xeb000000, 0x00ea, REG_W0, src_reg, 961 dst_reg, off); 962 jit->seen |= SEEN_MEM; 963 break; 964 /* 965 * BPF_LDX 966 */ 967 case BPF_LDX | BPF_MEM | BPF_B: /* dst = *(u8 *)(ul) (src + off) */ 968 /* llgc %dst,0(off,%src) */ 969 EMIT6_DISP_LH(0xe3000000, 0x0090, dst_reg, src_reg, REG_0, off); 970 jit->seen |= SEEN_MEM; 971 break; 972 case BPF_LDX | BPF_MEM | BPF_H: /* dst = *(u16 *)(ul) (src + off) */ 973 /* llgh %dst,0(off,%src) */ 974 EMIT6_DISP_LH(0xe3000000, 0x0091, dst_reg, src_reg, REG_0, off); 975 jit->seen |= SEEN_MEM; 976 break; 977 case BPF_LDX | BPF_MEM | BPF_W: /* dst = *(u32 *)(ul) (src + off) */ 978 /* llgf %dst,off(%src) */ 979 jit->seen |= SEEN_MEM; 980 EMIT6_DISP_LH(0xe3000000, 0x0016, dst_reg, src_reg, REG_0, off); 981 break; 982 case BPF_LDX | BPF_MEM | BPF_DW: /* dst = *(u64 *)(ul) (src + off) */ 983 /* lg %dst,0(off,%src) */ 984 jit->seen |= SEEN_MEM; 985 EMIT6_DISP_LH(0xe3000000, 0x0004, dst_reg, src_reg, REG_0, off); 986 break; 987 /* 988 * BPF_JMP / CALL 989 */ 990 case BPF_JMP | BPF_CALL: 991 { 992 /* 993 * b0 = (__bpf_call_base + imm)(b1, b2, b3, b4, b5) 994 */ 995 const u64 func = (u64)__bpf_call_base + imm; 996 997 REG_SET_SEEN(BPF_REG_5); 998 jit->seen |= SEEN_FUNC; 999 /* lg %w1,<d(imm)>(%l) */ 1000 EMIT6_DISP_LH(0xe3000000, 0x0004, REG_W1, REG_0, REG_L, 1001 EMIT_CONST_U64(func)); 1002 if (IS_ENABLED(CC_USING_EXPOLINE) && !nospec_disable) { 1003 /* brasl %r14,__s390_indirect_jump_r1 */ 1004 EMIT6_PCREL_RILB(0xc0050000, REG_14, jit->r1_thunk_ip); 1005 } else { 1006 /* basr %r14,%w1 */ 1007 EMIT2(0x0d00, REG_14, REG_W1); 1008 } 1009 /* lgr %b0,%r2: load return value into %b0 */ 1010 EMIT4(0xb9040000, BPF_REG_0, REG_2); 1011 break; 1012 } 1013 case BPF_JMP | BPF_TAIL_CALL: 1014 /* 1015 * Implicit input: 1016 * B1: pointer to ctx 1017 * B2: pointer to bpf_array 1018 * B3: index in bpf_array 1019 */ 1020 jit->seen |= SEEN_TAIL_CALL; 1021 1022 /* 1023 * if (index >= array->map.max_entries) 1024 * goto out; 1025 */ 1026 1027 /* llgf %w1,map.max_entries(%b2) */ 1028 EMIT6_DISP_LH(0xe3000000, 0x0016, REG_W1, REG_0, BPF_REG_2, 1029 offsetof(struct bpf_array, map.max_entries)); 1030 /* clgrj %b3,%w1,0xa,label0: if %b3 >= %w1 goto out */ 1031 EMIT6_PCREL_LABEL(0xec000000, 0x0065, BPF_REG_3, 1032 REG_W1, 0, 0xa); 1033 1034 /* 1035 * if (tail_call_cnt++ > MAX_TAIL_CALL_CNT) 1036 * goto out; 1037 */ 1038 1039 if (jit->seen & SEEN_STACK) 1040 off = STK_OFF_TCCNT + STK_OFF + fp->aux->stack_depth; 1041 else 1042 off = STK_OFF_TCCNT; 1043 /* lhi %w0,1 */ 1044 EMIT4_IMM(0xa7080000, REG_W0, 1); 1045 /* laal %w1,%w0,off(%r15) */ 1046 EMIT6_DISP_LH(0xeb000000, 0x00fa, REG_W1, REG_W0, REG_15, off); 1047 /* clij %w1,MAX_TAIL_CALL_CNT,0x2,label0 */ 1048 EMIT6_PCREL_IMM_LABEL(0xec000000, 0x007f, REG_W1, 1049 MAX_TAIL_CALL_CNT, 0, 0x2); 1050 1051 /* 1052 * prog = array->ptrs[index]; 1053 * if (prog == NULL) 1054 * goto out; 1055 */ 1056 1057 /* sllg %r1,%b3,3: %r1 = index * 8 */ 1058 EMIT6_DISP_LH(0xeb000000, 0x000d, REG_1, BPF_REG_3, REG_0, 3); 1059 /* lg %r1,prog(%b2,%r1) */ 1060 EMIT6_DISP_LH(0xe3000000, 0x0004, REG_1, BPF_REG_2, 1061 REG_1, offsetof(struct bpf_array, ptrs)); 1062 /* clgij %r1,0,0x8,label0 */ 1063 EMIT6_PCREL_IMM_LABEL(0xec000000, 0x007d, REG_1, 0, 0, 0x8); 1064 1065 /* 1066 * Restore registers before calling function 1067 */ 1068 save_restore_regs(jit, REGS_RESTORE, fp->aux->stack_depth); 1069 1070 /* 1071 * goto *(prog->bpf_func + tail_call_start); 1072 */ 1073 1074 /* lg %r1,bpf_func(%r1) */ 1075 EMIT6_DISP_LH(0xe3000000, 0x0004, REG_1, REG_1, REG_0, 1076 offsetof(struct bpf_prog, bpf_func)); 1077 /* bc 0xf,tail_call_start(%r1) */ 1078 _EMIT4(0x47f01000 + jit->tail_call_start); 1079 /* out: */ 1080 jit->labels[0] = jit->prg; 1081 break; 1082 case BPF_JMP | BPF_EXIT: /* return b0 */ 1083 last = (i == fp->len - 1) ? 1 : 0; 1084 if (last && !(jit->seen & SEEN_RET0)) 1085 break; 1086 /* j <exit> */ 1087 EMIT4_PCREL(0xa7f40000, jit->exit_ip - jit->prg); 1088 break; 1089 /* 1090 * Branch relative (number of skipped instructions) to offset on 1091 * condition. 1092 * 1093 * Condition code to mask mapping: 1094 * 1095 * CC | Description | Mask 1096 * ------------------------------ 1097 * 0 | Operands equal | 8 1098 * 1 | First operand low | 4 1099 * 2 | First operand high | 2 1100 * 3 | Unused | 1 1101 * 1102 * For s390x relative branches: ip = ip + off_bytes 1103 * For BPF relative branches: insn = insn + off_insns + 1 1104 * 1105 * For example for s390x with offset 0 we jump to the branch 1106 * instruction itself (loop) and for BPF with offset 0 we 1107 * branch to the instruction behind the branch. 1108 */ 1109 case BPF_JMP | BPF_JA: /* if (true) */ 1110 mask = 0xf000; /* j */ 1111 goto branch_oc; 1112 case BPF_JMP | BPF_JSGT | BPF_K: /* ((s64) dst > (s64) imm) */ 1113 mask = 0x2000; /* jh */ 1114 goto branch_ks; 1115 case BPF_JMP | BPF_JSLT | BPF_K: /* ((s64) dst < (s64) imm) */ 1116 mask = 0x4000; /* jl */ 1117 goto branch_ks; 1118 case BPF_JMP | BPF_JSGE | BPF_K: /* ((s64) dst >= (s64) imm) */ 1119 mask = 0xa000; /* jhe */ 1120 goto branch_ks; 1121 case BPF_JMP | BPF_JSLE | BPF_K: /* ((s64) dst <= (s64) imm) */ 1122 mask = 0xc000; /* jle */ 1123 goto branch_ks; 1124 case BPF_JMP | BPF_JGT | BPF_K: /* (dst_reg > imm) */ 1125 mask = 0x2000; /* jh */ 1126 goto branch_ku; 1127 case BPF_JMP | BPF_JLT | BPF_K: /* (dst_reg < imm) */ 1128 mask = 0x4000; /* jl */ 1129 goto branch_ku; 1130 case BPF_JMP | BPF_JGE | BPF_K: /* (dst_reg >= imm) */ 1131 mask = 0xa000; /* jhe */ 1132 goto branch_ku; 1133 case BPF_JMP | BPF_JLE | BPF_K: /* (dst_reg <= imm) */ 1134 mask = 0xc000; /* jle */ 1135 goto branch_ku; 1136 case BPF_JMP | BPF_JNE | BPF_K: /* (dst_reg != imm) */ 1137 mask = 0x7000; /* jne */ 1138 goto branch_ku; 1139 case BPF_JMP | BPF_JEQ | BPF_K: /* (dst_reg == imm) */ 1140 mask = 0x8000; /* je */ 1141 goto branch_ku; 1142 case BPF_JMP | BPF_JSET | BPF_K: /* (dst_reg & imm) */ 1143 mask = 0x7000; /* jnz */ 1144 /* lgfi %w1,imm (load sign extend imm) */ 1145 EMIT6_IMM(0xc0010000, REG_W1, imm); 1146 /* ngr %w1,%dst */ 1147 EMIT4(0xb9800000, REG_W1, dst_reg); 1148 goto branch_oc; 1149 1150 case BPF_JMP | BPF_JSGT | BPF_X: /* ((s64) dst > (s64) src) */ 1151 mask = 0x2000; /* jh */ 1152 goto branch_xs; 1153 case BPF_JMP | BPF_JSLT | BPF_X: /* ((s64) dst < (s64) src) */ 1154 mask = 0x4000; /* jl */ 1155 goto branch_xs; 1156 case BPF_JMP | BPF_JSGE | BPF_X: /* ((s64) dst >= (s64) src) */ 1157 mask = 0xa000; /* jhe */ 1158 goto branch_xs; 1159 case BPF_JMP | BPF_JSLE | BPF_X: /* ((s64) dst <= (s64) src) */ 1160 mask = 0xc000; /* jle */ 1161 goto branch_xs; 1162 case BPF_JMP | BPF_JGT | BPF_X: /* (dst > src) */ 1163 mask = 0x2000; /* jh */ 1164 goto branch_xu; 1165 case BPF_JMP | BPF_JLT | BPF_X: /* (dst < src) */ 1166 mask = 0x4000; /* jl */ 1167 goto branch_xu; 1168 case BPF_JMP | BPF_JGE | BPF_X: /* (dst >= src) */ 1169 mask = 0xa000; /* jhe */ 1170 goto branch_xu; 1171 case BPF_JMP | BPF_JLE | BPF_X: /* (dst <= src) */ 1172 mask = 0xc000; /* jle */ 1173 goto branch_xu; 1174 case BPF_JMP | BPF_JNE | BPF_X: /* (dst != src) */ 1175 mask = 0x7000; /* jne */ 1176 goto branch_xu; 1177 case BPF_JMP | BPF_JEQ | BPF_X: /* (dst == src) */ 1178 mask = 0x8000; /* je */ 1179 goto branch_xu; 1180 case BPF_JMP | BPF_JSET | BPF_X: /* (dst & src) */ 1181 mask = 0x7000; /* jnz */ 1182 /* ngrk %w1,%dst,%src */ 1183 EMIT4_RRF(0xb9e40000, REG_W1, dst_reg, src_reg); 1184 goto branch_oc; 1185 branch_ks: 1186 /* lgfi %w1,imm (load sign extend imm) */ 1187 EMIT6_IMM(0xc0010000, REG_W1, imm); 1188 /* cgrj %dst,%w1,mask,off */ 1189 EMIT6_PCREL(0xec000000, 0x0064, dst_reg, REG_W1, i, off, mask); 1190 break; 1191 branch_ku: 1192 /* lgfi %w1,imm (load sign extend imm) */ 1193 EMIT6_IMM(0xc0010000, REG_W1, imm); 1194 /* clgrj %dst,%w1,mask,off */ 1195 EMIT6_PCREL(0xec000000, 0x0065, dst_reg, REG_W1, i, off, mask); 1196 break; 1197 branch_xs: 1198 /* cgrj %dst,%src,mask,off */ 1199 EMIT6_PCREL(0xec000000, 0x0064, dst_reg, src_reg, i, off, mask); 1200 break; 1201 branch_xu: 1202 /* clgrj %dst,%src,mask,off */ 1203 EMIT6_PCREL(0xec000000, 0x0065, dst_reg, src_reg, i, off, mask); 1204 break; 1205 branch_oc: 1206 /* brc mask,jmp_off (branch instruction needs 4 bytes) */ 1207 jmp_off = addrs[i + off + 1] - (addrs[i + 1] - 4); 1208 EMIT4_PCREL(0xa7040000 | mask << 8, jmp_off); 1209 break; 1210 default: /* too complex, give up */ 1211 pr_err("Unknown opcode %02x\n", insn->code); 1212 return -1; 1213 } 1214 return insn_count; 1215 } 1216 1217 /* 1218 * Compile eBPF program into s390x code 1219 */ 1220 static int bpf_jit_prog(struct bpf_jit *jit, struct bpf_prog *fp) 1221 { 1222 int i, insn_count; 1223 1224 jit->lit = jit->lit_start; 1225 jit->prg = 0; 1226 1227 bpf_jit_prologue(jit, fp->aux->stack_depth); 1228 for (i = 0; i < fp->len; i += insn_count) { 1229 insn_count = bpf_jit_insn(jit, fp, i); 1230 if (insn_count < 0) 1231 return -1; 1232 /* Next instruction address */ 1233 jit->addrs[i + insn_count] = jit->prg; 1234 } 1235 bpf_jit_epilogue(jit, fp->aux->stack_depth); 1236 1237 jit->lit_start = jit->prg; 1238 jit->size = jit->lit; 1239 jit->size_prg = jit->prg; 1240 return 0; 1241 } 1242 1243 /* 1244 * Compile eBPF program "fp" 1245 */ 1246 struct bpf_prog *bpf_int_jit_compile(struct bpf_prog *fp) 1247 { 1248 struct bpf_prog *tmp, *orig_fp = fp; 1249 struct bpf_binary_header *header; 1250 bool tmp_blinded = false; 1251 struct bpf_jit jit; 1252 int pass; 1253 1254 if (!fp->jit_requested) 1255 return orig_fp; 1256 1257 tmp = bpf_jit_blind_constants(fp); 1258 /* 1259 * If blinding was requested and we failed during blinding, 1260 * we must fall back to the interpreter. 1261 */ 1262 if (IS_ERR(tmp)) 1263 return orig_fp; 1264 if (tmp != fp) { 1265 tmp_blinded = true; 1266 fp = tmp; 1267 } 1268 1269 memset(&jit, 0, sizeof(jit)); 1270 jit.addrs = kcalloc(fp->len + 1, sizeof(*jit.addrs), GFP_KERNEL); 1271 if (jit.addrs == NULL) { 1272 fp = orig_fp; 1273 goto out; 1274 } 1275 /* 1276 * Three initial passes: 1277 * - 1/2: Determine clobbered registers 1278 * - 3: Calculate program size and addrs arrray 1279 */ 1280 for (pass = 1; pass <= 3; pass++) { 1281 if (bpf_jit_prog(&jit, fp)) { 1282 fp = orig_fp; 1283 goto free_addrs; 1284 } 1285 } 1286 /* 1287 * Final pass: Allocate and generate program 1288 */ 1289 if (jit.size >= BPF_SIZE_MAX) { 1290 fp = orig_fp; 1291 goto free_addrs; 1292 } 1293 header = bpf_jit_binary_alloc(jit.size, &jit.prg_buf, 2, jit_fill_hole); 1294 if (!header) { 1295 fp = orig_fp; 1296 goto free_addrs; 1297 } 1298 if (bpf_jit_prog(&jit, fp)) { 1299 bpf_jit_binary_free(header); 1300 fp = orig_fp; 1301 goto free_addrs; 1302 } 1303 if (bpf_jit_enable > 1) { 1304 bpf_jit_dump(fp->len, jit.size, pass, jit.prg_buf); 1305 print_fn_code(jit.prg_buf, jit.size_prg); 1306 } 1307 bpf_jit_binary_lock_ro(header); 1308 fp->bpf_func = (void *) jit.prg_buf; 1309 fp->jited = 1; 1310 fp->jited_len = jit.size; 1311 free_addrs: 1312 kfree(jit.addrs); 1313 out: 1314 if (tmp_blinded) 1315 bpf_jit_prog_release_other(fp, fp == orig_fp ? 1316 tmp : orig_fp); 1317 return fp; 1318 } 1319