1 /* 2 * arch/s390/kernel/time.c 3 * Time of day based timer functions. 4 * 5 * S390 version 6 * Copyright (C) 1999 IBM Deutschland Entwicklung GmbH, IBM Corporation 7 * Author(s): Hartmut Penner (hp@de.ibm.com), 8 * Martin Schwidefsky (schwidefsky@de.ibm.com), 9 * Denis Joseph Barrow (djbarrow@de.ibm.com,barrow_dj@yahoo.com) 10 * 11 * Derived from "arch/i386/kernel/time.c" 12 * Copyright (C) 1991, 1992, 1995 Linus Torvalds 13 */ 14 15 #include <linux/errno.h> 16 #include <linux/module.h> 17 #include <linux/sched.h> 18 #include <linux/kernel.h> 19 #include <linux/param.h> 20 #include <linux/string.h> 21 #include <linux/mm.h> 22 #include <linux/interrupt.h> 23 #include <linux/time.h> 24 #include <linux/sysdev.h> 25 #include <linux/delay.h> 26 #include <linux/init.h> 27 #include <linux/smp.h> 28 #include <linux/types.h> 29 #include <linux/profile.h> 30 #include <linux/timex.h> 31 #include <linux/notifier.h> 32 #include <linux/clocksource.h> 33 34 #include <asm/uaccess.h> 35 #include <asm/delay.h> 36 #include <asm/s390_ext.h> 37 #include <asm/div64.h> 38 #include <asm/irq.h> 39 #include <asm/irq_regs.h> 40 #include <asm/timer.h> 41 #include <asm/etr.h> 42 43 /* change this if you have some constant time drift */ 44 #define USECS_PER_JIFFY ((unsigned long) 1000000/HZ) 45 #define CLK_TICKS_PER_JIFFY ((unsigned long) USECS_PER_JIFFY << 12) 46 47 /* The value of the TOD clock for 1.1.1970. */ 48 #define TOD_UNIX_EPOCH 0x7d91048bca000000ULL 49 50 /* 51 * Create a small time difference between the timer interrupts 52 * on the different cpus to avoid lock contention. 53 */ 54 #define CPU_DEVIATION (smp_processor_id() << 12) 55 56 #define TICK_SIZE tick 57 58 static ext_int_info_t ext_int_info_cc; 59 static ext_int_info_t ext_int_etr_cc; 60 static u64 init_timer_cc; 61 static u64 jiffies_timer_cc; 62 static u64 xtime_cc; 63 64 /* 65 * Scheduler clock - returns current time in nanosec units. 66 */ 67 unsigned long long sched_clock(void) 68 { 69 return ((get_clock() - jiffies_timer_cc) * 125) >> 9; 70 } 71 72 /* 73 * Monotonic_clock - returns # of nanoseconds passed since time_init() 74 */ 75 unsigned long long monotonic_clock(void) 76 { 77 return sched_clock(); 78 } 79 EXPORT_SYMBOL(monotonic_clock); 80 81 void tod_to_timeval(__u64 todval, struct timespec *xtime) 82 { 83 unsigned long long sec; 84 85 sec = todval >> 12; 86 do_div(sec, 1000000); 87 xtime->tv_sec = sec; 88 todval -= (sec * 1000000) << 12; 89 xtime->tv_nsec = ((todval * 1000) >> 12); 90 } 91 92 #ifdef CONFIG_PROFILING 93 #define s390_do_profile() profile_tick(CPU_PROFILING) 94 #else 95 #define s390_do_profile() do { ; } while(0) 96 #endif /* CONFIG_PROFILING */ 97 98 /* 99 * Advance the per cpu tick counter up to the time given with the 100 * "time" argument. The per cpu update consists of accounting 101 * the virtual cpu time, calling update_process_times and calling 102 * the profiling hook. If xtime is before time it is advanced as well. 103 */ 104 void account_ticks(u64 time) 105 { 106 __u32 ticks; 107 __u64 tmp; 108 109 /* Calculate how many ticks have passed. */ 110 if (time < S390_lowcore.jiffy_timer) 111 return; 112 tmp = time - S390_lowcore.jiffy_timer; 113 if (tmp >= 2*CLK_TICKS_PER_JIFFY) { /* more than two ticks ? */ 114 ticks = __div(tmp, CLK_TICKS_PER_JIFFY) + 1; 115 S390_lowcore.jiffy_timer += 116 CLK_TICKS_PER_JIFFY * (__u64) ticks; 117 } else if (tmp >= CLK_TICKS_PER_JIFFY) { 118 ticks = 2; 119 S390_lowcore.jiffy_timer += 2*CLK_TICKS_PER_JIFFY; 120 } else { 121 ticks = 1; 122 S390_lowcore.jiffy_timer += CLK_TICKS_PER_JIFFY; 123 } 124 125 #ifdef CONFIG_SMP 126 /* 127 * Do not rely on the boot cpu to do the calls to do_timer. 128 * Spread it over all cpus instead. 129 */ 130 write_seqlock(&xtime_lock); 131 if (S390_lowcore.jiffy_timer > xtime_cc) { 132 __u32 xticks; 133 tmp = S390_lowcore.jiffy_timer - xtime_cc; 134 if (tmp >= 2*CLK_TICKS_PER_JIFFY) { 135 xticks = __div(tmp, CLK_TICKS_PER_JIFFY); 136 xtime_cc += (__u64) xticks * CLK_TICKS_PER_JIFFY; 137 } else { 138 xticks = 1; 139 xtime_cc += CLK_TICKS_PER_JIFFY; 140 } 141 do_timer(xticks); 142 } 143 write_sequnlock(&xtime_lock); 144 #else 145 do_timer(ticks); 146 #endif 147 148 while (ticks--) 149 update_process_times(user_mode(get_irq_regs())); 150 151 s390_do_profile(); 152 } 153 154 #ifdef CONFIG_NO_IDLE_HZ 155 156 #ifdef CONFIG_NO_IDLE_HZ_INIT 157 int sysctl_hz_timer = 0; 158 #else 159 int sysctl_hz_timer = 1; 160 #endif 161 162 /* 163 * Stop the HZ tick on the current CPU. 164 * Only cpu_idle may call this function. 165 */ 166 static void stop_hz_timer(void) 167 { 168 unsigned long flags; 169 unsigned long seq, next; 170 __u64 timer, todval; 171 int cpu = smp_processor_id(); 172 173 if (sysctl_hz_timer != 0) 174 return; 175 176 cpu_set(cpu, nohz_cpu_mask); 177 178 /* 179 * Leave the clock comparator set up for the next timer 180 * tick if either rcu or a softirq is pending. 181 */ 182 if (rcu_needs_cpu(cpu) || local_softirq_pending()) { 183 cpu_clear(cpu, nohz_cpu_mask); 184 return; 185 } 186 187 /* 188 * This cpu is going really idle. Set up the clock comparator 189 * for the next event. 190 */ 191 next = next_timer_interrupt(); 192 do { 193 seq = read_seqbegin_irqsave(&xtime_lock, flags); 194 timer = ((__u64) next) - ((__u64) jiffies) + jiffies_64; 195 } while (read_seqretry_irqrestore(&xtime_lock, seq, flags)); 196 todval = -1ULL; 197 /* Be careful about overflows. */ 198 if (timer < (-1ULL / CLK_TICKS_PER_JIFFY)) { 199 timer = jiffies_timer_cc + timer * CLK_TICKS_PER_JIFFY; 200 if (timer >= jiffies_timer_cc) 201 todval = timer; 202 } 203 set_clock_comparator(todval); 204 } 205 206 /* 207 * Start the HZ tick on the current CPU. 208 * Only cpu_idle may call this function. 209 */ 210 static void start_hz_timer(void) 211 { 212 BUG_ON(!in_interrupt()); 213 214 if (!cpu_isset(smp_processor_id(), nohz_cpu_mask)) 215 return; 216 account_ticks(get_clock()); 217 set_clock_comparator(S390_lowcore.jiffy_timer + CPU_DEVIATION); 218 cpu_clear(smp_processor_id(), nohz_cpu_mask); 219 } 220 221 static int nohz_idle_notify(struct notifier_block *self, 222 unsigned long action, void *hcpu) 223 { 224 switch (action) { 225 case S390_CPU_IDLE: 226 stop_hz_timer(); 227 break; 228 case S390_CPU_NOT_IDLE: 229 start_hz_timer(); 230 break; 231 } 232 return NOTIFY_OK; 233 } 234 235 static struct notifier_block nohz_idle_nb = { 236 .notifier_call = nohz_idle_notify, 237 }; 238 239 static void __init nohz_init(void) 240 { 241 if (register_idle_notifier(&nohz_idle_nb)) 242 panic("Couldn't register idle notifier"); 243 } 244 245 #endif 246 247 /* 248 * Set up per cpu jiffy timer and set the clock comparator. 249 */ 250 static void setup_jiffy_timer(void) 251 { 252 /* Set up clock comparator to next jiffy. */ 253 S390_lowcore.jiffy_timer = 254 jiffies_timer_cc + (jiffies_64 + 1) * CLK_TICKS_PER_JIFFY; 255 set_clock_comparator(S390_lowcore.jiffy_timer + CPU_DEVIATION); 256 } 257 258 /* 259 * Set up lowcore and control register of the current cpu to 260 * enable TOD clock and clock comparator interrupts. 261 */ 262 void init_cpu_timer(void) 263 { 264 setup_jiffy_timer(); 265 266 /* Enable clock comparator timer interrupt. */ 267 __ctl_set_bit(0,11); 268 269 /* Always allow ETR external interrupts, even without an ETR. */ 270 __ctl_set_bit(0, 4); 271 } 272 273 static void clock_comparator_interrupt(__u16 code) 274 { 275 /* set clock comparator for next tick */ 276 set_clock_comparator(S390_lowcore.jiffy_timer + CPU_DEVIATION); 277 } 278 279 static void etr_reset(void); 280 static void etr_ext_handler(__u16); 281 282 /* 283 * Get the TOD clock running. 284 */ 285 static u64 __init reset_tod_clock(void) 286 { 287 u64 time; 288 289 etr_reset(); 290 if (store_clock(&time) == 0) 291 return time; 292 /* TOD clock not running. Set the clock to Unix Epoch. */ 293 if (set_clock(TOD_UNIX_EPOCH) != 0 || store_clock(&time) != 0) 294 panic("TOD clock not operational."); 295 296 return TOD_UNIX_EPOCH; 297 } 298 299 static cycle_t read_tod_clock(void) 300 { 301 return get_clock(); 302 } 303 304 static struct clocksource clocksource_tod = { 305 .name = "tod", 306 .rating = 400, 307 .read = read_tod_clock, 308 .mask = -1ULL, 309 .mult = 1000, 310 .shift = 12, 311 .flags = CLOCK_SOURCE_IS_CONTINUOUS, 312 }; 313 314 315 /* 316 * Initialize the TOD clock and the CPU timer of 317 * the boot cpu. 318 */ 319 void __init time_init(void) 320 { 321 init_timer_cc = reset_tod_clock(); 322 xtime_cc = init_timer_cc + CLK_TICKS_PER_JIFFY; 323 jiffies_timer_cc = init_timer_cc - jiffies_64 * CLK_TICKS_PER_JIFFY; 324 325 /* set xtime */ 326 tod_to_timeval(init_timer_cc - TOD_UNIX_EPOCH, &xtime); 327 set_normalized_timespec(&wall_to_monotonic, 328 -xtime.tv_sec, -xtime.tv_nsec); 329 330 /* request the clock comparator external interrupt */ 331 if (register_early_external_interrupt(0x1004, 332 clock_comparator_interrupt, 333 &ext_int_info_cc) != 0) 334 panic("Couldn't request external interrupt 0x1004"); 335 336 if (clocksource_register(&clocksource_tod) != 0) 337 panic("Could not register TOD clock source"); 338 339 /* request the etr external interrupt */ 340 if (register_early_external_interrupt(0x1406, etr_ext_handler, 341 &ext_int_etr_cc) != 0) 342 panic("Couldn't request external interrupt 0x1406"); 343 344 /* Enable TOD clock interrupts on the boot cpu. */ 345 init_cpu_timer(); 346 347 #ifdef CONFIG_NO_IDLE_HZ 348 nohz_init(); 349 #endif 350 351 #ifdef CONFIG_VIRT_TIMER 352 vtime_init(); 353 #endif 354 } 355 356 /* 357 * External Time Reference (ETR) code. 358 */ 359 static int etr_port0_online; 360 static int etr_port1_online; 361 362 static int __init early_parse_etr(char *p) 363 { 364 if (strncmp(p, "off", 3) == 0) 365 etr_port0_online = etr_port1_online = 0; 366 else if (strncmp(p, "port0", 5) == 0) 367 etr_port0_online = 1; 368 else if (strncmp(p, "port1", 5) == 0) 369 etr_port1_online = 1; 370 else if (strncmp(p, "on", 2) == 0) 371 etr_port0_online = etr_port1_online = 1; 372 return 0; 373 } 374 early_param("etr", early_parse_etr); 375 376 enum etr_event { 377 ETR_EVENT_PORT0_CHANGE, 378 ETR_EVENT_PORT1_CHANGE, 379 ETR_EVENT_PORT_ALERT, 380 ETR_EVENT_SYNC_CHECK, 381 ETR_EVENT_SWITCH_LOCAL, 382 ETR_EVENT_UPDATE, 383 }; 384 385 enum etr_flags { 386 ETR_FLAG_ENOSYS, 387 ETR_FLAG_EACCES, 388 ETR_FLAG_STEAI, 389 }; 390 391 /* 392 * Valid bit combinations of the eacr register are (x = don't care): 393 * e0 e1 dp p0 p1 ea es sl 394 * 0 0 x 0 0 0 0 0 initial, disabled state 395 * 0 0 x 0 1 1 0 0 port 1 online 396 * 0 0 x 1 0 1 0 0 port 0 online 397 * 0 0 x 1 1 1 0 0 both ports online 398 * 0 1 x 0 1 1 0 0 port 1 online and usable, ETR or PPS mode 399 * 0 1 x 0 1 1 0 1 port 1 online, usable and ETR mode 400 * 0 1 x 0 1 1 1 0 port 1 online, usable, PPS mode, in-sync 401 * 0 1 x 0 1 1 1 1 port 1 online, usable, ETR mode, in-sync 402 * 0 1 x 1 1 1 0 0 both ports online, port 1 usable 403 * 0 1 x 1 1 1 1 0 both ports online, port 1 usable, PPS mode, in-sync 404 * 0 1 x 1 1 1 1 1 both ports online, port 1 usable, ETR mode, in-sync 405 * 1 0 x 1 0 1 0 0 port 0 online and usable, ETR or PPS mode 406 * 1 0 x 1 0 1 0 1 port 0 online, usable and ETR mode 407 * 1 0 x 1 0 1 1 0 port 0 online, usable, PPS mode, in-sync 408 * 1 0 x 1 0 1 1 1 port 0 online, usable, ETR mode, in-sync 409 * 1 0 x 1 1 1 0 0 both ports online, port 0 usable 410 * 1 0 x 1 1 1 1 0 both ports online, port 0 usable, PPS mode, in-sync 411 * 1 0 x 1 1 1 1 1 both ports online, port 0 usable, ETR mode, in-sync 412 * 1 1 x 1 1 1 1 0 both ports online & usable, ETR, in-sync 413 * 1 1 x 1 1 1 1 1 both ports online & usable, ETR, in-sync 414 */ 415 static struct etr_eacr etr_eacr; 416 static u64 etr_tolec; /* time of last eacr update */ 417 static unsigned long etr_flags; 418 static struct etr_aib etr_port0; 419 static int etr_port0_uptodate; 420 static struct etr_aib etr_port1; 421 static int etr_port1_uptodate; 422 static unsigned long etr_events; 423 static struct timer_list etr_timer; 424 static DEFINE_PER_CPU(atomic_t, etr_sync_word); 425 426 static void etr_timeout(unsigned long dummy); 427 static void etr_work_fn(struct work_struct *work); 428 static DECLARE_WORK(etr_work, etr_work_fn); 429 430 /* 431 * The etr get_clock function. It will write the current clock value 432 * to the clock pointer and return 0 if the clock is in sync with the 433 * external time source. If the clock mode is local it will return 434 * -ENOSYS and -EAGAIN if the clock is not in sync with the external 435 * reference. This function is what ETR is all about.. 436 */ 437 int get_sync_clock(unsigned long long *clock) 438 { 439 atomic_t *sw_ptr; 440 unsigned int sw0, sw1; 441 442 sw_ptr = &get_cpu_var(etr_sync_word); 443 sw0 = atomic_read(sw_ptr); 444 *clock = get_clock(); 445 sw1 = atomic_read(sw_ptr); 446 put_cpu_var(etr_sync_sync); 447 if (sw0 == sw1 && (sw0 & 0x80000000U)) 448 /* Success: time is in sync. */ 449 return 0; 450 if (test_bit(ETR_FLAG_ENOSYS, &etr_flags)) 451 return -ENOSYS; 452 if (test_bit(ETR_FLAG_EACCES, &etr_flags)) 453 return -EACCES; 454 return -EAGAIN; 455 } 456 EXPORT_SYMBOL(get_sync_clock); 457 458 /* 459 * Make get_sync_clock return -EAGAIN. 460 */ 461 static void etr_disable_sync_clock(void *dummy) 462 { 463 atomic_t *sw_ptr = &__get_cpu_var(etr_sync_word); 464 /* 465 * Clear the in-sync bit 2^31. All get_sync_clock calls will 466 * fail until the sync bit is turned back on. In addition 467 * increase the "sequence" counter to avoid the race of an 468 * etr event and the complete recovery against get_sync_clock. 469 */ 470 atomic_clear_mask(0x80000000, sw_ptr); 471 atomic_inc(sw_ptr); 472 } 473 474 /* 475 * Make get_sync_clock return 0 again. 476 * Needs to be called from a context disabled for preemption. 477 */ 478 static void etr_enable_sync_clock(void) 479 { 480 atomic_t *sw_ptr = &__get_cpu_var(etr_sync_word); 481 atomic_set_mask(0x80000000, sw_ptr); 482 } 483 484 /* 485 * Reset ETR attachment. 486 */ 487 static void etr_reset(void) 488 { 489 etr_eacr = (struct etr_eacr) { 490 .e0 = 0, .e1 = 0, ._pad0 = 4, .dp = 0, 491 .p0 = 0, .p1 = 0, ._pad1 = 0, .ea = 0, 492 .es = 0, .sl = 0 }; 493 if (etr_setr(&etr_eacr) == 0) 494 etr_tolec = get_clock(); 495 else { 496 set_bit(ETR_FLAG_ENOSYS, &etr_flags); 497 if (etr_port0_online || etr_port1_online) { 498 printk(KERN_WARNING "Running on non ETR capable " 499 "machine, only local mode available.\n"); 500 etr_port0_online = etr_port1_online = 0; 501 } 502 } 503 } 504 505 static int __init etr_init(void) 506 { 507 struct etr_aib aib; 508 509 if (test_bit(ETR_FLAG_ENOSYS, &etr_flags)) 510 return 0; 511 /* Check if this machine has the steai instruction. */ 512 if (etr_steai(&aib, ETR_STEAI_STEPPING_PORT) == 0) 513 set_bit(ETR_FLAG_STEAI, &etr_flags); 514 setup_timer(&etr_timer, etr_timeout, 0UL); 515 if (!etr_port0_online && !etr_port1_online) 516 set_bit(ETR_FLAG_EACCES, &etr_flags); 517 if (etr_port0_online) { 518 set_bit(ETR_EVENT_PORT0_CHANGE, &etr_events); 519 schedule_work(&etr_work); 520 } 521 if (etr_port1_online) { 522 set_bit(ETR_EVENT_PORT1_CHANGE, &etr_events); 523 schedule_work(&etr_work); 524 } 525 return 0; 526 } 527 528 arch_initcall(etr_init); 529 530 /* 531 * Two sorts of ETR machine checks. The architecture reads: 532 * "When a machine-check niterruption occurs and if a switch-to-local or 533 * ETR-sync-check interrupt request is pending but disabled, this pending 534 * disabled interruption request is indicated and is cleared". 535 * Which means that we can get etr_switch_to_local events from the machine 536 * check handler although the interruption condition is disabled. Lovely.. 537 */ 538 539 /* 540 * Switch to local machine check. This is called when the last usable 541 * ETR port goes inactive. After switch to local the clock is not in sync. 542 */ 543 void etr_switch_to_local(void) 544 { 545 if (!etr_eacr.sl) 546 return; 547 etr_disable_sync_clock(NULL); 548 set_bit(ETR_EVENT_SWITCH_LOCAL, &etr_events); 549 schedule_work(&etr_work); 550 } 551 552 /* 553 * ETR sync check machine check. This is called when the ETR OTE and the 554 * local clock OTE are farther apart than the ETR sync check tolerance. 555 * After a ETR sync check the clock is not in sync. The machine check 556 * is broadcasted to all cpus at the same time. 557 */ 558 void etr_sync_check(void) 559 { 560 if (!etr_eacr.es) 561 return; 562 etr_disable_sync_clock(NULL); 563 set_bit(ETR_EVENT_SYNC_CHECK, &etr_events); 564 schedule_work(&etr_work); 565 } 566 567 /* 568 * ETR external interrupt. There are two causes: 569 * 1) port state change, check the usability of the port 570 * 2) port alert, one of the ETR-data-validity bits (v1-v2 bits of the 571 * sldr-status word) or ETR-data word 1 (edf1) or ETR-data word 3 (edf3) 572 * or ETR-data word 4 (edf4) has changed. 573 */ 574 static void etr_ext_handler(__u16 code) 575 { 576 struct etr_interruption_parameter *intparm = 577 (struct etr_interruption_parameter *) &S390_lowcore.ext_params; 578 579 if (intparm->pc0) 580 /* ETR port 0 state change. */ 581 set_bit(ETR_EVENT_PORT0_CHANGE, &etr_events); 582 if (intparm->pc1) 583 /* ETR port 1 state change. */ 584 set_bit(ETR_EVENT_PORT1_CHANGE, &etr_events); 585 if (intparm->eai) 586 /* 587 * ETR port alert on either port 0, 1 or both. 588 * Both ports are not up-to-date now. 589 */ 590 set_bit(ETR_EVENT_PORT_ALERT, &etr_events); 591 schedule_work(&etr_work); 592 } 593 594 static void etr_timeout(unsigned long dummy) 595 { 596 set_bit(ETR_EVENT_UPDATE, &etr_events); 597 schedule_work(&etr_work); 598 } 599 600 /* 601 * Check if the etr mode is pss. 602 */ 603 static inline int etr_mode_is_pps(struct etr_eacr eacr) 604 { 605 return eacr.es && !eacr.sl; 606 } 607 608 /* 609 * Check if the etr mode is etr. 610 */ 611 static inline int etr_mode_is_etr(struct etr_eacr eacr) 612 { 613 return eacr.es && eacr.sl; 614 } 615 616 /* 617 * Check if the port can be used for TOD synchronization. 618 * For PPS mode the port has to receive OTEs. For ETR mode 619 * the port has to receive OTEs, the ETR stepping bit has to 620 * be zero and the validity bits for data frame 1, 2, and 3 621 * have to be 1. 622 */ 623 static int etr_port_valid(struct etr_aib *aib, int port) 624 { 625 unsigned int psc; 626 627 /* Check that this port is receiving OTEs. */ 628 if (aib->tsp == 0) 629 return 0; 630 631 psc = port ? aib->esw.psc1 : aib->esw.psc0; 632 if (psc == etr_lpsc_pps_mode) 633 return 1; 634 if (psc == etr_lpsc_operational_step) 635 return !aib->esw.y && aib->slsw.v1 && 636 aib->slsw.v2 && aib->slsw.v3; 637 return 0; 638 } 639 640 /* 641 * Check if two ports are on the same network. 642 */ 643 static int etr_compare_network(struct etr_aib *aib1, struct etr_aib *aib2) 644 { 645 // FIXME: any other fields we have to compare? 646 return aib1->edf1.net_id == aib2->edf1.net_id; 647 } 648 649 /* 650 * Wrapper for etr_stei that converts physical port states 651 * to logical port states to be consistent with the output 652 * of stetr (see etr_psc vs. etr_lpsc). 653 */ 654 static void etr_steai_cv(struct etr_aib *aib, unsigned int func) 655 { 656 BUG_ON(etr_steai(aib, func) != 0); 657 /* Convert port state to logical port state. */ 658 if (aib->esw.psc0 == 1) 659 aib->esw.psc0 = 2; 660 else if (aib->esw.psc0 == 0 && aib->esw.p == 0) 661 aib->esw.psc0 = 1; 662 if (aib->esw.psc1 == 1) 663 aib->esw.psc1 = 2; 664 else if (aib->esw.psc1 == 0 && aib->esw.p == 1) 665 aib->esw.psc1 = 1; 666 } 667 668 /* 669 * Check if the aib a2 is still connected to the same attachment as 670 * aib a1, the etv values differ by one and a2 is valid. 671 */ 672 static int etr_aib_follows(struct etr_aib *a1, struct etr_aib *a2, int p) 673 { 674 int state_a1, state_a2; 675 676 /* Paranoia check: e0/e1 should better be the same. */ 677 if (a1->esw.eacr.e0 != a2->esw.eacr.e0 || 678 a1->esw.eacr.e1 != a2->esw.eacr.e1) 679 return 0; 680 681 /* Still connected to the same etr ? */ 682 state_a1 = p ? a1->esw.psc1 : a1->esw.psc0; 683 state_a2 = p ? a2->esw.psc1 : a2->esw.psc0; 684 if (state_a1 == etr_lpsc_operational_step) { 685 if (state_a2 != etr_lpsc_operational_step || 686 a1->edf1.net_id != a2->edf1.net_id || 687 a1->edf1.etr_id != a2->edf1.etr_id || 688 a1->edf1.etr_pn != a2->edf1.etr_pn) 689 return 0; 690 } else if (state_a2 != etr_lpsc_pps_mode) 691 return 0; 692 693 /* The ETV value of a2 needs to be ETV of a1 + 1. */ 694 if (a1->edf2.etv + 1 != a2->edf2.etv) 695 return 0; 696 697 if (!etr_port_valid(a2, p)) 698 return 0; 699 700 return 1; 701 } 702 703 /* 704 * The time is "clock". xtime is what we think the time is. 705 * Adjust the value by a multiple of jiffies and add the delta to ntp. 706 * "delay" is an approximation how long the synchronization took. If 707 * the time correction is positive, then "delay" is subtracted from 708 * the time difference and only the remaining part is passed to ntp. 709 */ 710 static void etr_adjust_time(unsigned long long clock, unsigned long long delay) 711 { 712 unsigned long long delta, ticks; 713 struct timex adjust; 714 715 /* 716 * We don't have to take the xtime lock because the cpu 717 * executing etr_adjust_time is running disabled in 718 * tasklet context and all other cpus are looping in 719 * etr_sync_cpu_start. 720 */ 721 if (clock > xtime_cc) { 722 /* It is later than we thought. */ 723 delta = ticks = clock - xtime_cc; 724 delta = ticks = (delta < delay) ? 0 : delta - delay; 725 delta -= do_div(ticks, CLK_TICKS_PER_JIFFY); 726 init_timer_cc = init_timer_cc + delta; 727 jiffies_timer_cc = jiffies_timer_cc + delta; 728 xtime_cc = xtime_cc + delta; 729 adjust.offset = ticks * (1000000 / HZ); 730 } else { 731 /* It is earlier than we thought. */ 732 delta = ticks = xtime_cc - clock; 733 delta -= do_div(ticks, CLK_TICKS_PER_JIFFY); 734 init_timer_cc = init_timer_cc - delta; 735 jiffies_timer_cc = jiffies_timer_cc - delta; 736 xtime_cc = xtime_cc - delta; 737 adjust.offset = -ticks * (1000000 / HZ); 738 } 739 if (adjust.offset != 0) { 740 printk(KERN_NOTICE "etr: time adjusted by %li micro-seconds\n", 741 adjust.offset); 742 adjust.modes = ADJ_OFFSET_SINGLESHOT; 743 do_adjtimex(&adjust); 744 } 745 } 746 747 #ifdef CONFIG_SMP 748 static void etr_sync_cpu_start(void *dummy) 749 { 750 int *in_sync = dummy; 751 752 etr_enable_sync_clock(); 753 /* 754 * This looks like a busy wait loop but it isn't. etr_sync_cpus 755 * is called on all other cpus while the TOD clocks is stopped. 756 * __udelay will stop the cpu on an enabled wait psw until the 757 * TOD is running again. 758 */ 759 while (*in_sync == 0) { 760 __udelay(1); 761 /* 762 * A different cpu changes *in_sync. Therefore use 763 * barrier() to force memory access. 764 */ 765 barrier(); 766 } 767 if (*in_sync != 1) 768 /* Didn't work. Clear per-cpu in sync bit again. */ 769 etr_disable_sync_clock(NULL); 770 /* 771 * This round of TOD syncing is done. Set the clock comparator 772 * to the next tick and let the processor continue. 773 */ 774 setup_jiffy_timer(); 775 } 776 777 static void etr_sync_cpu_end(void *dummy) 778 { 779 } 780 #endif /* CONFIG_SMP */ 781 782 /* 783 * Sync the TOD clock using the port refered to by aibp. This port 784 * has to be enabled and the other port has to be disabled. The 785 * last eacr update has to be more than 1.6 seconds in the past. 786 */ 787 static int etr_sync_clock(struct etr_aib *aib, int port) 788 { 789 struct etr_aib *sync_port; 790 unsigned long long clock, delay; 791 int in_sync, follows; 792 int rc; 793 794 /* Check if the current aib is adjacent to the sync port aib. */ 795 sync_port = (port == 0) ? &etr_port0 : &etr_port1; 796 follows = etr_aib_follows(sync_port, aib, port); 797 memcpy(sync_port, aib, sizeof(*aib)); 798 if (!follows) 799 return -EAGAIN; 800 801 /* 802 * Catch all other cpus and make them wait until we have 803 * successfully synced the clock. smp_call_function will 804 * return after all other cpus are in etr_sync_cpu_start. 805 */ 806 in_sync = 0; 807 preempt_disable(); 808 smp_call_function(etr_sync_cpu_start,&in_sync,0,0); 809 local_irq_disable(); 810 etr_enable_sync_clock(); 811 812 /* Set clock to next OTE. */ 813 __ctl_set_bit(14, 21); 814 __ctl_set_bit(0, 29); 815 clock = ((unsigned long long) (aib->edf2.etv + 1)) << 32; 816 if (set_clock(clock) == 0) { 817 __udelay(1); /* Wait for the clock to start. */ 818 __ctl_clear_bit(0, 29); 819 __ctl_clear_bit(14, 21); 820 etr_stetr(aib); 821 /* Adjust Linux timing variables. */ 822 delay = (unsigned long long) 823 (aib->edf2.etv - sync_port->edf2.etv) << 32; 824 etr_adjust_time(clock, delay); 825 setup_jiffy_timer(); 826 /* Verify that the clock is properly set. */ 827 if (!etr_aib_follows(sync_port, aib, port)) { 828 /* Didn't work. */ 829 etr_disable_sync_clock(NULL); 830 in_sync = -EAGAIN; 831 rc = -EAGAIN; 832 } else { 833 in_sync = 1; 834 rc = 0; 835 } 836 } else { 837 /* Could not set the clock ?!? */ 838 __ctl_clear_bit(0, 29); 839 __ctl_clear_bit(14, 21); 840 etr_disable_sync_clock(NULL); 841 in_sync = -EAGAIN; 842 rc = -EAGAIN; 843 } 844 local_irq_enable(); 845 smp_call_function(etr_sync_cpu_end,NULL,0,0); 846 preempt_enable(); 847 return rc; 848 } 849 850 /* 851 * Handle the immediate effects of the different events. 852 * The port change event is used for online/offline changes. 853 */ 854 static struct etr_eacr etr_handle_events(struct etr_eacr eacr) 855 { 856 if (test_and_clear_bit(ETR_EVENT_SYNC_CHECK, &etr_events)) 857 eacr.es = 0; 858 if (test_and_clear_bit(ETR_EVENT_SWITCH_LOCAL, &etr_events)) 859 eacr.es = eacr.sl = 0; 860 if (test_and_clear_bit(ETR_EVENT_PORT_ALERT, &etr_events)) 861 etr_port0_uptodate = etr_port1_uptodate = 0; 862 863 if (test_and_clear_bit(ETR_EVENT_PORT0_CHANGE, &etr_events)) { 864 if (eacr.e0) 865 /* 866 * Port change of an enabled port. We have to 867 * assume that this can have caused an stepping 868 * port switch. 869 */ 870 etr_tolec = get_clock(); 871 eacr.p0 = etr_port0_online; 872 if (!eacr.p0) 873 eacr.e0 = 0; 874 etr_port0_uptodate = 0; 875 } 876 if (test_and_clear_bit(ETR_EVENT_PORT1_CHANGE, &etr_events)) { 877 if (eacr.e1) 878 /* 879 * Port change of an enabled port. We have to 880 * assume that this can have caused an stepping 881 * port switch. 882 */ 883 etr_tolec = get_clock(); 884 eacr.p1 = etr_port1_online; 885 if (!eacr.p1) 886 eacr.e1 = 0; 887 etr_port1_uptodate = 0; 888 } 889 clear_bit(ETR_EVENT_UPDATE, &etr_events); 890 return eacr; 891 } 892 893 /* 894 * Set up a timer that expires after the etr_tolec + 1.6 seconds if 895 * one of the ports needs an update. 896 */ 897 static void etr_set_tolec_timeout(unsigned long long now) 898 { 899 unsigned long micros; 900 901 if ((!etr_eacr.p0 || etr_port0_uptodate) && 902 (!etr_eacr.p1 || etr_port1_uptodate)) 903 return; 904 micros = (now > etr_tolec) ? ((now - etr_tolec) >> 12) : 0; 905 micros = (micros > 1600000) ? 0 : 1600000 - micros; 906 mod_timer(&etr_timer, jiffies + (micros * HZ) / 1000000 + 1); 907 } 908 909 /* 910 * Set up a time that expires after 1/2 second. 911 */ 912 static void etr_set_sync_timeout(void) 913 { 914 mod_timer(&etr_timer, jiffies + HZ/2); 915 } 916 917 /* 918 * Update the aib information for one or both ports. 919 */ 920 static struct etr_eacr etr_handle_update(struct etr_aib *aib, 921 struct etr_eacr eacr) 922 { 923 /* With both ports disabled the aib information is useless. */ 924 if (!eacr.e0 && !eacr.e1) 925 return eacr; 926 927 /* Update port0 or port1 with aib stored in etr_work_fn. */ 928 if (aib->esw.q == 0) { 929 /* Information for port 0 stored. */ 930 if (eacr.p0 && !etr_port0_uptodate) { 931 etr_port0 = *aib; 932 if (etr_port0_online) 933 etr_port0_uptodate = 1; 934 } 935 } else { 936 /* Information for port 1 stored. */ 937 if (eacr.p1 && !etr_port1_uptodate) { 938 etr_port1 = *aib; 939 if (etr_port0_online) 940 etr_port1_uptodate = 1; 941 } 942 } 943 944 /* 945 * Do not try to get the alternate port aib if the clock 946 * is not in sync yet. 947 */ 948 if (!eacr.es) 949 return eacr; 950 951 /* 952 * If steai is available we can get the information about 953 * the other port immediately. If only stetr is available the 954 * data-port bit toggle has to be used. 955 */ 956 if (test_bit(ETR_FLAG_STEAI, &etr_flags)) { 957 if (eacr.p0 && !etr_port0_uptodate) { 958 etr_steai_cv(&etr_port0, ETR_STEAI_PORT_0); 959 etr_port0_uptodate = 1; 960 } 961 if (eacr.p1 && !etr_port1_uptodate) { 962 etr_steai_cv(&etr_port1, ETR_STEAI_PORT_1); 963 etr_port1_uptodate = 1; 964 } 965 } else { 966 /* 967 * One port was updated above, if the other 968 * port is not uptodate toggle dp bit. 969 */ 970 if ((eacr.p0 && !etr_port0_uptodate) || 971 (eacr.p1 && !etr_port1_uptodate)) 972 eacr.dp ^= 1; 973 else 974 eacr.dp = 0; 975 } 976 return eacr; 977 } 978 979 /* 980 * Write new etr control register if it differs from the current one. 981 * Return 1 if etr_tolec has been updated as well. 982 */ 983 static void etr_update_eacr(struct etr_eacr eacr) 984 { 985 int dp_changed; 986 987 if (memcmp(&etr_eacr, &eacr, sizeof(eacr)) == 0) 988 /* No change, return. */ 989 return; 990 /* 991 * The disable of an active port of the change of the data port 992 * bit can/will cause a change in the data port. 993 */ 994 dp_changed = etr_eacr.e0 > eacr.e0 || etr_eacr.e1 > eacr.e1 || 995 (etr_eacr.dp ^ eacr.dp) != 0; 996 etr_eacr = eacr; 997 etr_setr(&etr_eacr); 998 if (dp_changed) 999 etr_tolec = get_clock(); 1000 } 1001 1002 /* 1003 * ETR tasklet. In this function you'll find the main logic. In 1004 * particular this is the only function that calls etr_update_eacr(), 1005 * it "controls" the etr control register. 1006 */ 1007 static void etr_work_fn(struct work_struct *work) 1008 { 1009 unsigned long long now; 1010 struct etr_eacr eacr; 1011 struct etr_aib aib; 1012 int sync_port; 1013 1014 /* Create working copy of etr_eacr. */ 1015 eacr = etr_eacr; 1016 1017 /* Check for the different events and their immediate effects. */ 1018 eacr = etr_handle_events(eacr); 1019 1020 /* Check if ETR is supposed to be active. */ 1021 eacr.ea = eacr.p0 || eacr.p1; 1022 if (!eacr.ea) { 1023 /* Both ports offline. Reset everything. */ 1024 eacr.dp = eacr.es = eacr.sl = 0; 1025 on_each_cpu(etr_disable_sync_clock, NULL, 0, 1); 1026 del_timer_sync(&etr_timer); 1027 etr_update_eacr(eacr); 1028 set_bit(ETR_FLAG_EACCES, &etr_flags); 1029 return; 1030 } 1031 1032 /* Store aib to get the current ETR status word. */ 1033 BUG_ON(etr_stetr(&aib) != 0); 1034 etr_port0.esw = etr_port1.esw = aib.esw; /* Copy status word. */ 1035 now = get_clock(); 1036 1037 /* 1038 * Update the port information if the last stepping port change 1039 * or data port change is older than 1.6 seconds. 1040 */ 1041 if (now >= etr_tolec + (1600000 << 12)) 1042 eacr = etr_handle_update(&aib, eacr); 1043 1044 /* 1045 * Select ports to enable. The prefered synchronization mode is PPS. 1046 * If a port can be enabled depends on a number of things: 1047 * 1) The port needs to be online and uptodate. A port is not 1048 * disabled just because it is not uptodate, but it is only 1049 * enabled if it is uptodate. 1050 * 2) The port needs to have the same mode (pps / etr). 1051 * 3) The port needs to be usable -> etr_port_valid() == 1 1052 * 4) To enable the second port the clock needs to be in sync. 1053 * 5) If both ports are useable and are ETR ports, the network id 1054 * has to be the same. 1055 * The eacr.sl bit is used to indicate etr mode vs. pps mode. 1056 */ 1057 if (eacr.p0 && aib.esw.psc0 == etr_lpsc_pps_mode) { 1058 eacr.sl = 0; 1059 eacr.e0 = 1; 1060 if (!etr_mode_is_pps(etr_eacr)) 1061 eacr.es = 0; 1062 if (!eacr.es || !eacr.p1 || aib.esw.psc1 != etr_lpsc_pps_mode) 1063 eacr.e1 = 0; 1064 // FIXME: uptodate checks ? 1065 else if (etr_port0_uptodate && etr_port1_uptodate) 1066 eacr.e1 = 1; 1067 sync_port = (etr_port0_uptodate && 1068 etr_port_valid(&etr_port0, 0)) ? 0 : -1; 1069 clear_bit(ETR_FLAG_EACCES, &etr_flags); 1070 } else if (eacr.p1 && aib.esw.psc1 == etr_lpsc_pps_mode) { 1071 eacr.sl = 0; 1072 eacr.e0 = 0; 1073 eacr.e1 = 1; 1074 if (!etr_mode_is_pps(etr_eacr)) 1075 eacr.es = 0; 1076 sync_port = (etr_port1_uptodate && 1077 etr_port_valid(&etr_port1, 1)) ? 1 : -1; 1078 clear_bit(ETR_FLAG_EACCES, &etr_flags); 1079 } else if (eacr.p0 && aib.esw.psc0 == etr_lpsc_operational_step) { 1080 eacr.sl = 1; 1081 eacr.e0 = 1; 1082 if (!etr_mode_is_etr(etr_eacr)) 1083 eacr.es = 0; 1084 if (!eacr.es || !eacr.p1 || 1085 aib.esw.psc1 != etr_lpsc_operational_alt) 1086 eacr.e1 = 0; 1087 else if (etr_port0_uptodate && etr_port1_uptodate && 1088 etr_compare_network(&etr_port0, &etr_port1)) 1089 eacr.e1 = 1; 1090 sync_port = (etr_port0_uptodate && 1091 etr_port_valid(&etr_port0, 0)) ? 0 : -1; 1092 clear_bit(ETR_FLAG_EACCES, &etr_flags); 1093 } else if (eacr.p1 && aib.esw.psc1 == etr_lpsc_operational_step) { 1094 eacr.sl = 1; 1095 eacr.e0 = 0; 1096 eacr.e1 = 1; 1097 if (!etr_mode_is_etr(etr_eacr)) 1098 eacr.es = 0; 1099 sync_port = (etr_port1_uptodate && 1100 etr_port_valid(&etr_port1, 1)) ? 1 : -1; 1101 clear_bit(ETR_FLAG_EACCES, &etr_flags); 1102 } else { 1103 /* Both ports not usable. */ 1104 eacr.es = eacr.sl = 0; 1105 sync_port = -1; 1106 set_bit(ETR_FLAG_EACCES, &etr_flags); 1107 } 1108 1109 /* 1110 * If the clock is in sync just update the eacr and return. 1111 * If there is no valid sync port wait for a port update. 1112 */ 1113 if (eacr.es || sync_port < 0) { 1114 etr_update_eacr(eacr); 1115 etr_set_tolec_timeout(now); 1116 return; 1117 } 1118 1119 /* 1120 * Prepare control register for clock syncing 1121 * (reset data port bit, set sync check control. 1122 */ 1123 eacr.dp = 0; 1124 eacr.es = 1; 1125 1126 /* 1127 * Update eacr and try to synchronize the clock. If the update 1128 * of eacr caused a stepping port switch (or if we have to 1129 * assume that a stepping port switch has occured) or the 1130 * clock syncing failed, reset the sync check control bit 1131 * and set up a timer to try again after 0.5 seconds 1132 */ 1133 etr_update_eacr(eacr); 1134 if (now < etr_tolec + (1600000 << 12) || 1135 etr_sync_clock(&aib, sync_port) != 0) { 1136 /* Sync failed. Try again in 1/2 second. */ 1137 eacr.es = 0; 1138 etr_update_eacr(eacr); 1139 etr_set_sync_timeout(); 1140 } else 1141 etr_set_tolec_timeout(now); 1142 } 1143 1144 /* 1145 * Sysfs interface functions 1146 */ 1147 static struct sysdev_class etr_sysclass = { 1148 .name = "etr", 1149 }; 1150 1151 static struct sys_device etr_port0_dev = { 1152 .id = 0, 1153 .cls = &etr_sysclass, 1154 }; 1155 1156 static struct sys_device etr_port1_dev = { 1157 .id = 1, 1158 .cls = &etr_sysclass, 1159 }; 1160 1161 /* 1162 * ETR class attributes 1163 */ 1164 static ssize_t etr_stepping_port_show(struct sysdev_class *class, char *buf) 1165 { 1166 return sprintf(buf, "%i\n", etr_port0.esw.p); 1167 } 1168 1169 static SYSDEV_CLASS_ATTR(stepping_port, 0400, etr_stepping_port_show, NULL); 1170 1171 static ssize_t etr_stepping_mode_show(struct sysdev_class *class, char *buf) 1172 { 1173 char *mode_str; 1174 1175 if (etr_mode_is_pps(etr_eacr)) 1176 mode_str = "pps"; 1177 else if (etr_mode_is_etr(etr_eacr)) 1178 mode_str = "etr"; 1179 else 1180 mode_str = "local"; 1181 return sprintf(buf, "%s\n", mode_str); 1182 } 1183 1184 static SYSDEV_CLASS_ATTR(stepping_mode, 0400, etr_stepping_mode_show, NULL); 1185 1186 /* 1187 * ETR port attributes 1188 */ 1189 static inline struct etr_aib *etr_aib_from_dev(struct sys_device *dev) 1190 { 1191 if (dev == &etr_port0_dev) 1192 return etr_port0_online ? &etr_port0 : NULL; 1193 else 1194 return etr_port1_online ? &etr_port1 : NULL; 1195 } 1196 1197 static ssize_t etr_online_show(struct sys_device *dev, char *buf) 1198 { 1199 unsigned int online; 1200 1201 online = (dev == &etr_port0_dev) ? etr_port0_online : etr_port1_online; 1202 return sprintf(buf, "%i\n", online); 1203 } 1204 1205 static ssize_t etr_online_store(struct sys_device *dev, 1206 const char *buf, size_t count) 1207 { 1208 unsigned int value; 1209 1210 value = simple_strtoul(buf, NULL, 0); 1211 if (value != 0 && value != 1) 1212 return -EINVAL; 1213 if (test_bit(ETR_FLAG_ENOSYS, &etr_flags)) 1214 return -ENOSYS; 1215 if (dev == &etr_port0_dev) { 1216 if (etr_port0_online == value) 1217 return count; /* Nothing to do. */ 1218 etr_port0_online = value; 1219 set_bit(ETR_EVENT_PORT0_CHANGE, &etr_events); 1220 schedule_work(&etr_work); 1221 } else { 1222 if (etr_port1_online == value) 1223 return count; /* Nothing to do. */ 1224 etr_port1_online = value; 1225 set_bit(ETR_EVENT_PORT1_CHANGE, &etr_events); 1226 schedule_work(&etr_work); 1227 } 1228 return count; 1229 } 1230 1231 static SYSDEV_ATTR(online, 0600, etr_online_show, etr_online_store); 1232 1233 static ssize_t etr_stepping_control_show(struct sys_device *dev, char *buf) 1234 { 1235 return sprintf(buf, "%i\n", (dev == &etr_port0_dev) ? 1236 etr_eacr.e0 : etr_eacr.e1); 1237 } 1238 1239 static SYSDEV_ATTR(stepping_control, 0400, etr_stepping_control_show, NULL); 1240 1241 static ssize_t etr_mode_code_show(struct sys_device *dev, char *buf) 1242 { 1243 if (!etr_port0_online && !etr_port1_online) 1244 /* Status word is not uptodate if both ports are offline. */ 1245 return -ENODATA; 1246 return sprintf(buf, "%i\n", (dev == &etr_port0_dev) ? 1247 etr_port0.esw.psc0 : etr_port0.esw.psc1); 1248 } 1249 1250 static SYSDEV_ATTR(state_code, 0400, etr_mode_code_show, NULL); 1251 1252 static ssize_t etr_untuned_show(struct sys_device *dev, char *buf) 1253 { 1254 struct etr_aib *aib = etr_aib_from_dev(dev); 1255 1256 if (!aib || !aib->slsw.v1) 1257 return -ENODATA; 1258 return sprintf(buf, "%i\n", aib->edf1.u); 1259 } 1260 1261 static SYSDEV_ATTR(untuned, 0400, etr_untuned_show, NULL); 1262 1263 static ssize_t etr_network_id_show(struct sys_device *dev, char *buf) 1264 { 1265 struct etr_aib *aib = etr_aib_from_dev(dev); 1266 1267 if (!aib || !aib->slsw.v1) 1268 return -ENODATA; 1269 return sprintf(buf, "%i\n", aib->edf1.net_id); 1270 } 1271 1272 static SYSDEV_ATTR(network, 0400, etr_network_id_show, NULL); 1273 1274 static ssize_t etr_id_show(struct sys_device *dev, char *buf) 1275 { 1276 struct etr_aib *aib = etr_aib_from_dev(dev); 1277 1278 if (!aib || !aib->slsw.v1) 1279 return -ENODATA; 1280 return sprintf(buf, "%i\n", aib->edf1.etr_id); 1281 } 1282 1283 static SYSDEV_ATTR(id, 0400, etr_id_show, NULL); 1284 1285 static ssize_t etr_port_number_show(struct sys_device *dev, char *buf) 1286 { 1287 struct etr_aib *aib = etr_aib_from_dev(dev); 1288 1289 if (!aib || !aib->slsw.v1) 1290 return -ENODATA; 1291 return sprintf(buf, "%i\n", aib->edf1.etr_pn); 1292 } 1293 1294 static SYSDEV_ATTR(port, 0400, etr_port_number_show, NULL); 1295 1296 static ssize_t etr_coupled_show(struct sys_device *dev, char *buf) 1297 { 1298 struct etr_aib *aib = etr_aib_from_dev(dev); 1299 1300 if (!aib || !aib->slsw.v3) 1301 return -ENODATA; 1302 return sprintf(buf, "%i\n", aib->edf3.c); 1303 } 1304 1305 static SYSDEV_ATTR(coupled, 0400, etr_coupled_show, NULL); 1306 1307 static ssize_t etr_local_time_show(struct sys_device *dev, char *buf) 1308 { 1309 struct etr_aib *aib = etr_aib_from_dev(dev); 1310 1311 if (!aib || !aib->slsw.v3) 1312 return -ENODATA; 1313 return sprintf(buf, "%i\n", aib->edf3.blto); 1314 } 1315 1316 static SYSDEV_ATTR(local_time, 0400, etr_local_time_show, NULL); 1317 1318 static ssize_t etr_utc_offset_show(struct sys_device *dev, char *buf) 1319 { 1320 struct etr_aib *aib = etr_aib_from_dev(dev); 1321 1322 if (!aib || !aib->slsw.v3) 1323 return -ENODATA; 1324 return sprintf(buf, "%i\n", aib->edf3.buo); 1325 } 1326 1327 static SYSDEV_ATTR(utc_offset, 0400, etr_utc_offset_show, NULL); 1328 1329 static struct sysdev_attribute *etr_port_attributes[] = { 1330 &attr_online, 1331 &attr_stepping_control, 1332 &attr_state_code, 1333 &attr_untuned, 1334 &attr_network, 1335 &attr_id, 1336 &attr_port, 1337 &attr_coupled, 1338 &attr_local_time, 1339 &attr_utc_offset, 1340 NULL 1341 }; 1342 1343 static int __init etr_register_port(struct sys_device *dev) 1344 { 1345 struct sysdev_attribute **attr; 1346 int rc; 1347 1348 rc = sysdev_register(dev); 1349 if (rc) 1350 goto out; 1351 for (attr = etr_port_attributes; *attr; attr++) { 1352 rc = sysdev_create_file(dev, *attr); 1353 if (rc) 1354 goto out_unreg; 1355 } 1356 return 0; 1357 out_unreg: 1358 for (; attr >= etr_port_attributes; attr--) 1359 sysdev_remove_file(dev, *attr); 1360 sysdev_unregister(dev); 1361 out: 1362 return rc; 1363 } 1364 1365 static void __init etr_unregister_port(struct sys_device *dev) 1366 { 1367 struct sysdev_attribute **attr; 1368 1369 for (attr = etr_port_attributes; *attr; attr++) 1370 sysdev_remove_file(dev, *attr); 1371 sysdev_unregister(dev); 1372 } 1373 1374 static int __init etr_init_sysfs(void) 1375 { 1376 int rc; 1377 1378 rc = sysdev_class_register(&etr_sysclass); 1379 if (rc) 1380 goto out; 1381 rc = sysdev_class_create_file(&etr_sysclass, &attr_stepping_port); 1382 if (rc) 1383 goto out_unreg_class; 1384 rc = sysdev_class_create_file(&etr_sysclass, &attr_stepping_mode); 1385 if (rc) 1386 goto out_remove_stepping_port; 1387 rc = etr_register_port(&etr_port0_dev); 1388 if (rc) 1389 goto out_remove_stepping_mode; 1390 rc = etr_register_port(&etr_port1_dev); 1391 if (rc) 1392 goto out_remove_port0; 1393 return 0; 1394 1395 out_remove_port0: 1396 etr_unregister_port(&etr_port0_dev); 1397 out_remove_stepping_mode: 1398 sysdev_class_remove_file(&etr_sysclass, &attr_stepping_mode); 1399 out_remove_stepping_port: 1400 sysdev_class_remove_file(&etr_sysclass, &attr_stepping_port); 1401 out_unreg_class: 1402 sysdev_class_unregister(&etr_sysclass); 1403 out: 1404 return rc; 1405 } 1406 1407 device_initcall(etr_init_sysfs); 1408