1 /* 2 * arch/s390/kernel/time.c 3 * Time of day based timer functions. 4 * 5 * S390 version 6 * Copyright (C) 1999 IBM Deutschland Entwicklung GmbH, IBM Corporation 7 * Author(s): Hartmut Penner (hp@de.ibm.com), 8 * Martin Schwidefsky (schwidefsky@de.ibm.com), 9 * Denis Joseph Barrow (djbarrow@de.ibm.com,barrow_dj@yahoo.com) 10 * 11 * Derived from "arch/i386/kernel/time.c" 12 * Copyright (C) 1991, 1992, 1995 Linus Torvalds 13 */ 14 15 #include <linux/errno.h> 16 #include <linux/module.h> 17 #include <linux/sched.h> 18 #include <linux/kernel.h> 19 #include <linux/param.h> 20 #include <linux/string.h> 21 #include <linux/mm.h> 22 #include <linux/interrupt.h> 23 #include <linux/time.h> 24 #include <linux/sysdev.h> 25 #include <linux/delay.h> 26 #include <linux/init.h> 27 #include <linux/smp.h> 28 #include <linux/types.h> 29 #include <linux/profile.h> 30 #include <linux/timex.h> 31 #include <linux/notifier.h> 32 #include <linux/clocksource.h> 33 34 #include <asm/uaccess.h> 35 #include <asm/delay.h> 36 #include <asm/s390_ext.h> 37 #include <asm/div64.h> 38 #include <asm/irq.h> 39 #include <asm/irq_regs.h> 40 #include <asm/timer.h> 41 #include <asm/etr.h> 42 43 /* change this if you have some constant time drift */ 44 #define USECS_PER_JIFFY ((unsigned long) 1000000/HZ) 45 #define CLK_TICKS_PER_JIFFY ((unsigned long) USECS_PER_JIFFY << 12) 46 47 /* The value of the TOD clock for 1.1.1970. */ 48 #define TOD_UNIX_EPOCH 0x7d91048bca000000ULL 49 50 /* 51 * Create a small time difference between the timer interrupts 52 * on the different cpus to avoid lock contention. 53 */ 54 #define CPU_DEVIATION (smp_processor_id() << 12) 55 56 #define TICK_SIZE tick 57 58 static ext_int_info_t ext_int_info_cc; 59 static ext_int_info_t ext_int_etr_cc; 60 static u64 init_timer_cc; 61 static u64 jiffies_timer_cc; 62 static u64 xtime_cc; 63 64 /* 65 * Scheduler clock - returns current time in nanosec units. 66 */ 67 unsigned long long sched_clock(void) 68 { 69 return ((get_clock() - jiffies_timer_cc) * 125) >> 9; 70 } 71 72 /* 73 * Monotonic_clock - returns # of nanoseconds passed since time_init() 74 */ 75 unsigned long long monotonic_clock(void) 76 { 77 return sched_clock(); 78 } 79 EXPORT_SYMBOL(monotonic_clock); 80 81 void tod_to_timeval(__u64 todval, struct timespec *xtime) 82 { 83 unsigned long long sec; 84 85 sec = todval >> 12; 86 do_div(sec, 1000000); 87 xtime->tv_sec = sec; 88 todval -= (sec * 1000000) << 12; 89 xtime->tv_nsec = ((todval * 1000) >> 12); 90 } 91 92 #ifdef CONFIG_PROFILING 93 #define s390_do_profile() profile_tick(CPU_PROFILING) 94 #else 95 #define s390_do_profile() do { ; } while(0) 96 #endif /* CONFIG_PROFILING */ 97 98 /* 99 * Advance the per cpu tick counter up to the time given with the 100 * "time" argument. The per cpu update consists of accounting 101 * the virtual cpu time, calling update_process_times and calling 102 * the profiling hook. If xtime is before time it is advanced as well. 103 */ 104 void account_ticks(u64 time) 105 { 106 __u32 ticks; 107 __u64 tmp; 108 109 /* Calculate how many ticks have passed. */ 110 if (time < S390_lowcore.jiffy_timer) 111 return; 112 tmp = time - S390_lowcore.jiffy_timer; 113 if (tmp >= 2*CLK_TICKS_PER_JIFFY) { /* more than two ticks ? */ 114 ticks = __div(tmp, CLK_TICKS_PER_JIFFY) + 1; 115 S390_lowcore.jiffy_timer += 116 CLK_TICKS_PER_JIFFY * (__u64) ticks; 117 } else if (tmp >= CLK_TICKS_PER_JIFFY) { 118 ticks = 2; 119 S390_lowcore.jiffy_timer += 2*CLK_TICKS_PER_JIFFY; 120 } else { 121 ticks = 1; 122 S390_lowcore.jiffy_timer += CLK_TICKS_PER_JIFFY; 123 } 124 125 #ifdef CONFIG_SMP 126 /* 127 * Do not rely on the boot cpu to do the calls to do_timer. 128 * Spread it over all cpus instead. 129 */ 130 write_seqlock(&xtime_lock); 131 if (S390_lowcore.jiffy_timer > xtime_cc) { 132 __u32 xticks; 133 tmp = S390_lowcore.jiffy_timer - xtime_cc; 134 if (tmp >= 2*CLK_TICKS_PER_JIFFY) { 135 xticks = __div(tmp, CLK_TICKS_PER_JIFFY); 136 xtime_cc += (__u64) xticks * CLK_TICKS_PER_JIFFY; 137 } else { 138 xticks = 1; 139 xtime_cc += CLK_TICKS_PER_JIFFY; 140 } 141 do_timer(xticks); 142 } 143 write_sequnlock(&xtime_lock); 144 #else 145 do_timer(ticks); 146 #endif 147 148 while (ticks--) 149 update_process_times(user_mode(get_irq_regs())); 150 151 s390_do_profile(); 152 } 153 154 #ifdef CONFIG_NO_IDLE_HZ 155 156 #ifdef CONFIG_NO_IDLE_HZ_INIT 157 int sysctl_hz_timer = 0; 158 #else 159 int sysctl_hz_timer = 1; 160 #endif 161 162 /* 163 * Stop the HZ tick on the current CPU. 164 * Only cpu_idle may call this function. 165 */ 166 static void stop_hz_timer(void) 167 { 168 unsigned long flags; 169 unsigned long seq, next; 170 __u64 timer, todval; 171 int cpu = smp_processor_id(); 172 173 if (sysctl_hz_timer != 0) 174 return; 175 176 cpu_set(cpu, nohz_cpu_mask); 177 178 /* 179 * Leave the clock comparator set up for the next timer 180 * tick if either rcu or a softirq is pending. 181 */ 182 if (rcu_needs_cpu(cpu) || local_softirq_pending()) { 183 cpu_clear(cpu, nohz_cpu_mask); 184 return; 185 } 186 187 /* 188 * This cpu is going really idle. Set up the clock comparator 189 * for the next event. 190 */ 191 next = next_timer_interrupt(); 192 do { 193 seq = read_seqbegin_irqsave(&xtime_lock, flags); 194 timer = ((__u64) next) - ((__u64) jiffies) + jiffies_64; 195 } while (read_seqretry_irqrestore(&xtime_lock, seq, flags)); 196 todval = -1ULL; 197 /* Be careful about overflows. */ 198 if (timer < (-1ULL / CLK_TICKS_PER_JIFFY)) { 199 timer = jiffies_timer_cc + timer * CLK_TICKS_PER_JIFFY; 200 if (timer >= jiffies_timer_cc) 201 todval = timer; 202 } 203 set_clock_comparator(todval); 204 } 205 206 /* 207 * Start the HZ tick on the current CPU. 208 * Only cpu_idle may call this function. 209 */ 210 static void start_hz_timer(void) 211 { 212 if (!cpu_isset(smp_processor_id(), nohz_cpu_mask)) 213 return; 214 account_ticks(get_clock()); 215 set_clock_comparator(S390_lowcore.jiffy_timer + CPU_DEVIATION); 216 cpu_clear(smp_processor_id(), nohz_cpu_mask); 217 } 218 219 static int nohz_idle_notify(struct notifier_block *self, 220 unsigned long action, void *hcpu) 221 { 222 switch (action) { 223 case S390_CPU_IDLE: 224 stop_hz_timer(); 225 break; 226 case S390_CPU_NOT_IDLE: 227 start_hz_timer(); 228 break; 229 } 230 return NOTIFY_OK; 231 } 232 233 static struct notifier_block nohz_idle_nb = { 234 .notifier_call = nohz_idle_notify, 235 }; 236 237 static void __init nohz_init(void) 238 { 239 if (register_idle_notifier(&nohz_idle_nb)) 240 panic("Couldn't register idle notifier"); 241 } 242 243 #endif 244 245 /* 246 * Set up per cpu jiffy timer and set the clock comparator. 247 */ 248 static void setup_jiffy_timer(void) 249 { 250 /* Set up clock comparator to next jiffy. */ 251 S390_lowcore.jiffy_timer = 252 jiffies_timer_cc + (jiffies_64 + 1) * CLK_TICKS_PER_JIFFY; 253 set_clock_comparator(S390_lowcore.jiffy_timer + CPU_DEVIATION); 254 } 255 256 /* 257 * Set up lowcore and control register of the current cpu to 258 * enable TOD clock and clock comparator interrupts. 259 */ 260 void init_cpu_timer(void) 261 { 262 setup_jiffy_timer(); 263 264 /* Enable clock comparator timer interrupt. */ 265 __ctl_set_bit(0,11); 266 267 /* Always allow ETR external interrupts, even without an ETR. */ 268 __ctl_set_bit(0, 4); 269 } 270 271 static void clock_comparator_interrupt(__u16 code) 272 { 273 /* set clock comparator for next tick */ 274 set_clock_comparator(S390_lowcore.jiffy_timer + CPU_DEVIATION); 275 } 276 277 static void etr_reset(void); 278 static void etr_ext_handler(__u16); 279 280 /* 281 * Get the TOD clock running. 282 */ 283 static u64 __init reset_tod_clock(void) 284 { 285 u64 time; 286 287 etr_reset(); 288 if (store_clock(&time) == 0) 289 return time; 290 /* TOD clock not running. Set the clock to Unix Epoch. */ 291 if (set_clock(TOD_UNIX_EPOCH) != 0 || store_clock(&time) != 0) 292 panic("TOD clock not operational."); 293 294 return TOD_UNIX_EPOCH; 295 } 296 297 static cycle_t read_tod_clock(void) 298 { 299 return get_clock(); 300 } 301 302 static struct clocksource clocksource_tod = { 303 .name = "tod", 304 .rating = 400, 305 .read = read_tod_clock, 306 .mask = -1ULL, 307 .mult = 1000, 308 .shift = 12, 309 .flags = CLOCK_SOURCE_IS_CONTINUOUS, 310 }; 311 312 313 /* 314 * Initialize the TOD clock and the CPU timer of 315 * the boot cpu. 316 */ 317 void __init time_init(void) 318 { 319 init_timer_cc = reset_tod_clock(); 320 xtime_cc = init_timer_cc + CLK_TICKS_PER_JIFFY; 321 jiffies_timer_cc = init_timer_cc - jiffies_64 * CLK_TICKS_PER_JIFFY; 322 323 /* set xtime */ 324 tod_to_timeval(init_timer_cc - TOD_UNIX_EPOCH, &xtime); 325 set_normalized_timespec(&wall_to_monotonic, 326 -xtime.tv_sec, -xtime.tv_nsec); 327 328 /* request the clock comparator external interrupt */ 329 if (register_early_external_interrupt(0x1004, 330 clock_comparator_interrupt, 331 &ext_int_info_cc) != 0) 332 panic("Couldn't request external interrupt 0x1004"); 333 334 if (clocksource_register(&clocksource_tod) != 0) 335 panic("Could not register TOD clock source"); 336 337 /* request the etr external interrupt */ 338 if (register_early_external_interrupt(0x1406, etr_ext_handler, 339 &ext_int_etr_cc) != 0) 340 panic("Couldn't request external interrupt 0x1406"); 341 342 /* Enable TOD clock interrupts on the boot cpu. */ 343 init_cpu_timer(); 344 345 #ifdef CONFIG_NO_IDLE_HZ 346 nohz_init(); 347 #endif 348 349 #ifdef CONFIG_VIRT_TIMER 350 vtime_init(); 351 #endif 352 } 353 354 /* 355 * External Time Reference (ETR) code. 356 */ 357 static int etr_port0_online; 358 static int etr_port1_online; 359 360 static int __init early_parse_etr(char *p) 361 { 362 if (strncmp(p, "off", 3) == 0) 363 etr_port0_online = etr_port1_online = 0; 364 else if (strncmp(p, "port0", 5) == 0) 365 etr_port0_online = 1; 366 else if (strncmp(p, "port1", 5) == 0) 367 etr_port1_online = 1; 368 else if (strncmp(p, "on", 2) == 0) 369 etr_port0_online = etr_port1_online = 1; 370 return 0; 371 } 372 early_param("etr", early_parse_etr); 373 374 enum etr_event { 375 ETR_EVENT_PORT0_CHANGE, 376 ETR_EVENT_PORT1_CHANGE, 377 ETR_EVENT_PORT_ALERT, 378 ETR_EVENT_SYNC_CHECK, 379 ETR_EVENT_SWITCH_LOCAL, 380 ETR_EVENT_UPDATE, 381 }; 382 383 enum etr_flags { 384 ETR_FLAG_ENOSYS, 385 ETR_FLAG_EACCES, 386 ETR_FLAG_STEAI, 387 }; 388 389 /* 390 * Valid bit combinations of the eacr register are (x = don't care): 391 * e0 e1 dp p0 p1 ea es sl 392 * 0 0 x 0 0 0 0 0 initial, disabled state 393 * 0 0 x 0 1 1 0 0 port 1 online 394 * 0 0 x 1 0 1 0 0 port 0 online 395 * 0 0 x 1 1 1 0 0 both ports online 396 * 0 1 x 0 1 1 0 0 port 1 online and usable, ETR or PPS mode 397 * 0 1 x 0 1 1 0 1 port 1 online, usable and ETR mode 398 * 0 1 x 0 1 1 1 0 port 1 online, usable, PPS mode, in-sync 399 * 0 1 x 0 1 1 1 1 port 1 online, usable, ETR mode, in-sync 400 * 0 1 x 1 1 1 0 0 both ports online, port 1 usable 401 * 0 1 x 1 1 1 1 0 both ports online, port 1 usable, PPS mode, in-sync 402 * 0 1 x 1 1 1 1 1 both ports online, port 1 usable, ETR mode, in-sync 403 * 1 0 x 1 0 1 0 0 port 0 online and usable, ETR or PPS mode 404 * 1 0 x 1 0 1 0 1 port 0 online, usable and ETR mode 405 * 1 0 x 1 0 1 1 0 port 0 online, usable, PPS mode, in-sync 406 * 1 0 x 1 0 1 1 1 port 0 online, usable, ETR mode, in-sync 407 * 1 0 x 1 1 1 0 0 both ports online, port 0 usable 408 * 1 0 x 1 1 1 1 0 both ports online, port 0 usable, PPS mode, in-sync 409 * 1 0 x 1 1 1 1 1 both ports online, port 0 usable, ETR mode, in-sync 410 * 1 1 x 1 1 1 1 0 both ports online & usable, ETR, in-sync 411 * 1 1 x 1 1 1 1 1 both ports online & usable, ETR, in-sync 412 */ 413 static struct etr_eacr etr_eacr; 414 static u64 etr_tolec; /* time of last eacr update */ 415 static unsigned long etr_flags; 416 static struct etr_aib etr_port0; 417 static int etr_port0_uptodate; 418 static struct etr_aib etr_port1; 419 static int etr_port1_uptodate; 420 static unsigned long etr_events; 421 static struct timer_list etr_timer; 422 static DEFINE_PER_CPU(atomic_t, etr_sync_word); 423 424 static void etr_timeout(unsigned long dummy); 425 static void etr_work_fn(struct work_struct *work); 426 static DECLARE_WORK(etr_work, etr_work_fn); 427 428 /* 429 * The etr get_clock function. It will write the current clock value 430 * to the clock pointer and return 0 if the clock is in sync with the 431 * external time source. If the clock mode is local it will return 432 * -ENOSYS and -EAGAIN if the clock is not in sync with the external 433 * reference. This function is what ETR is all about.. 434 */ 435 int get_sync_clock(unsigned long long *clock) 436 { 437 atomic_t *sw_ptr; 438 unsigned int sw0, sw1; 439 440 sw_ptr = &get_cpu_var(etr_sync_word); 441 sw0 = atomic_read(sw_ptr); 442 *clock = get_clock(); 443 sw1 = atomic_read(sw_ptr); 444 put_cpu_var(etr_sync_sync); 445 if (sw0 == sw1 && (sw0 & 0x80000000U)) 446 /* Success: time is in sync. */ 447 return 0; 448 if (test_bit(ETR_FLAG_ENOSYS, &etr_flags)) 449 return -ENOSYS; 450 if (test_bit(ETR_FLAG_EACCES, &etr_flags)) 451 return -EACCES; 452 return -EAGAIN; 453 } 454 EXPORT_SYMBOL(get_sync_clock); 455 456 /* 457 * Make get_sync_clock return -EAGAIN. 458 */ 459 static void etr_disable_sync_clock(void *dummy) 460 { 461 atomic_t *sw_ptr = &__get_cpu_var(etr_sync_word); 462 /* 463 * Clear the in-sync bit 2^31. All get_sync_clock calls will 464 * fail until the sync bit is turned back on. In addition 465 * increase the "sequence" counter to avoid the race of an 466 * etr event and the complete recovery against get_sync_clock. 467 */ 468 atomic_clear_mask(0x80000000, sw_ptr); 469 atomic_inc(sw_ptr); 470 } 471 472 /* 473 * Make get_sync_clock return 0 again. 474 * Needs to be called from a context disabled for preemption. 475 */ 476 static void etr_enable_sync_clock(void) 477 { 478 atomic_t *sw_ptr = &__get_cpu_var(etr_sync_word); 479 atomic_set_mask(0x80000000, sw_ptr); 480 } 481 482 /* 483 * Reset ETR attachment. 484 */ 485 static void etr_reset(void) 486 { 487 etr_eacr = (struct etr_eacr) { 488 .e0 = 0, .e1 = 0, ._pad0 = 4, .dp = 0, 489 .p0 = 0, .p1 = 0, ._pad1 = 0, .ea = 0, 490 .es = 0, .sl = 0 }; 491 if (etr_setr(&etr_eacr) == 0) 492 etr_tolec = get_clock(); 493 else { 494 set_bit(ETR_FLAG_ENOSYS, &etr_flags); 495 if (etr_port0_online || etr_port1_online) { 496 printk(KERN_WARNING "Running on non ETR capable " 497 "machine, only local mode available.\n"); 498 etr_port0_online = etr_port1_online = 0; 499 } 500 } 501 } 502 503 static int __init etr_init(void) 504 { 505 struct etr_aib aib; 506 507 if (test_bit(ETR_FLAG_ENOSYS, &etr_flags)) 508 return 0; 509 /* Check if this machine has the steai instruction. */ 510 if (etr_steai(&aib, ETR_STEAI_STEPPING_PORT) == 0) 511 set_bit(ETR_FLAG_STEAI, &etr_flags); 512 setup_timer(&etr_timer, etr_timeout, 0UL); 513 if (!etr_port0_online && !etr_port1_online) 514 set_bit(ETR_FLAG_EACCES, &etr_flags); 515 if (etr_port0_online) { 516 set_bit(ETR_EVENT_PORT0_CHANGE, &etr_events); 517 schedule_work(&etr_work); 518 } 519 if (etr_port1_online) { 520 set_bit(ETR_EVENT_PORT1_CHANGE, &etr_events); 521 schedule_work(&etr_work); 522 } 523 return 0; 524 } 525 526 arch_initcall(etr_init); 527 528 /* 529 * Two sorts of ETR machine checks. The architecture reads: 530 * "When a machine-check niterruption occurs and if a switch-to-local or 531 * ETR-sync-check interrupt request is pending but disabled, this pending 532 * disabled interruption request is indicated and is cleared". 533 * Which means that we can get etr_switch_to_local events from the machine 534 * check handler although the interruption condition is disabled. Lovely.. 535 */ 536 537 /* 538 * Switch to local machine check. This is called when the last usable 539 * ETR port goes inactive. After switch to local the clock is not in sync. 540 */ 541 void etr_switch_to_local(void) 542 { 543 if (!etr_eacr.sl) 544 return; 545 etr_disable_sync_clock(NULL); 546 set_bit(ETR_EVENT_SWITCH_LOCAL, &etr_events); 547 schedule_work(&etr_work); 548 } 549 550 /* 551 * ETR sync check machine check. This is called when the ETR OTE and the 552 * local clock OTE are farther apart than the ETR sync check tolerance. 553 * After a ETR sync check the clock is not in sync. The machine check 554 * is broadcasted to all cpus at the same time. 555 */ 556 void etr_sync_check(void) 557 { 558 if (!etr_eacr.es) 559 return; 560 etr_disable_sync_clock(NULL); 561 set_bit(ETR_EVENT_SYNC_CHECK, &etr_events); 562 schedule_work(&etr_work); 563 } 564 565 /* 566 * ETR external interrupt. There are two causes: 567 * 1) port state change, check the usability of the port 568 * 2) port alert, one of the ETR-data-validity bits (v1-v2 bits of the 569 * sldr-status word) or ETR-data word 1 (edf1) or ETR-data word 3 (edf3) 570 * or ETR-data word 4 (edf4) has changed. 571 */ 572 static void etr_ext_handler(__u16 code) 573 { 574 struct etr_interruption_parameter *intparm = 575 (struct etr_interruption_parameter *) &S390_lowcore.ext_params; 576 577 if (intparm->pc0) 578 /* ETR port 0 state change. */ 579 set_bit(ETR_EVENT_PORT0_CHANGE, &etr_events); 580 if (intparm->pc1) 581 /* ETR port 1 state change. */ 582 set_bit(ETR_EVENT_PORT1_CHANGE, &etr_events); 583 if (intparm->eai) 584 /* 585 * ETR port alert on either port 0, 1 or both. 586 * Both ports are not up-to-date now. 587 */ 588 set_bit(ETR_EVENT_PORT_ALERT, &etr_events); 589 schedule_work(&etr_work); 590 } 591 592 static void etr_timeout(unsigned long dummy) 593 { 594 set_bit(ETR_EVENT_UPDATE, &etr_events); 595 schedule_work(&etr_work); 596 } 597 598 /* 599 * Check if the etr mode is pss. 600 */ 601 static inline int etr_mode_is_pps(struct etr_eacr eacr) 602 { 603 return eacr.es && !eacr.sl; 604 } 605 606 /* 607 * Check if the etr mode is etr. 608 */ 609 static inline int etr_mode_is_etr(struct etr_eacr eacr) 610 { 611 return eacr.es && eacr.sl; 612 } 613 614 /* 615 * Check if the port can be used for TOD synchronization. 616 * For PPS mode the port has to receive OTEs. For ETR mode 617 * the port has to receive OTEs, the ETR stepping bit has to 618 * be zero and the validity bits for data frame 1, 2, and 3 619 * have to be 1. 620 */ 621 static int etr_port_valid(struct etr_aib *aib, int port) 622 { 623 unsigned int psc; 624 625 /* Check that this port is receiving OTEs. */ 626 if (aib->tsp == 0) 627 return 0; 628 629 psc = port ? aib->esw.psc1 : aib->esw.psc0; 630 if (psc == etr_lpsc_pps_mode) 631 return 1; 632 if (psc == etr_lpsc_operational_step) 633 return !aib->esw.y && aib->slsw.v1 && 634 aib->slsw.v2 && aib->slsw.v3; 635 return 0; 636 } 637 638 /* 639 * Check if two ports are on the same network. 640 */ 641 static int etr_compare_network(struct etr_aib *aib1, struct etr_aib *aib2) 642 { 643 // FIXME: any other fields we have to compare? 644 return aib1->edf1.net_id == aib2->edf1.net_id; 645 } 646 647 /* 648 * Wrapper for etr_stei that converts physical port states 649 * to logical port states to be consistent with the output 650 * of stetr (see etr_psc vs. etr_lpsc). 651 */ 652 static void etr_steai_cv(struct etr_aib *aib, unsigned int func) 653 { 654 BUG_ON(etr_steai(aib, func) != 0); 655 /* Convert port state to logical port state. */ 656 if (aib->esw.psc0 == 1) 657 aib->esw.psc0 = 2; 658 else if (aib->esw.psc0 == 0 && aib->esw.p == 0) 659 aib->esw.psc0 = 1; 660 if (aib->esw.psc1 == 1) 661 aib->esw.psc1 = 2; 662 else if (aib->esw.psc1 == 0 && aib->esw.p == 1) 663 aib->esw.psc1 = 1; 664 } 665 666 /* 667 * Check if the aib a2 is still connected to the same attachment as 668 * aib a1, the etv values differ by one and a2 is valid. 669 */ 670 static int etr_aib_follows(struct etr_aib *a1, struct etr_aib *a2, int p) 671 { 672 int state_a1, state_a2; 673 674 /* Paranoia check: e0/e1 should better be the same. */ 675 if (a1->esw.eacr.e0 != a2->esw.eacr.e0 || 676 a1->esw.eacr.e1 != a2->esw.eacr.e1) 677 return 0; 678 679 /* Still connected to the same etr ? */ 680 state_a1 = p ? a1->esw.psc1 : a1->esw.psc0; 681 state_a2 = p ? a2->esw.psc1 : a2->esw.psc0; 682 if (state_a1 == etr_lpsc_operational_step) { 683 if (state_a2 != etr_lpsc_operational_step || 684 a1->edf1.net_id != a2->edf1.net_id || 685 a1->edf1.etr_id != a2->edf1.etr_id || 686 a1->edf1.etr_pn != a2->edf1.etr_pn) 687 return 0; 688 } else if (state_a2 != etr_lpsc_pps_mode) 689 return 0; 690 691 /* The ETV value of a2 needs to be ETV of a1 + 1. */ 692 if (a1->edf2.etv + 1 != a2->edf2.etv) 693 return 0; 694 695 if (!etr_port_valid(a2, p)) 696 return 0; 697 698 return 1; 699 } 700 701 /* 702 * The time is "clock". xtime is what we think the time is. 703 * Adjust the value by a multiple of jiffies and add the delta to ntp. 704 * "delay" is an approximation how long the synchronization took. If 705 * the time correction is positive, then "delay" is subtracted from 706 * the time difference and only the remaining part is passed to ntp. 707 */ 708 static void etr_adjust_time(unsigned long long clock, unsigned long long delay) 709 { 710 unsigned long long delta, ticks; 711 struct timex adjust; 712 713 /* 714 * We don't have to take the xtime lock because the cpu 715 * executing etr_adjust_time is running disabled in 716 * tasklet context and all other cpus are looping in 717 * etr_sync_cpu_start. 718 */ 719 if (clock > xtime_cc) { 720 /* It is later than we thought. */ 721 delta = ticks = clock - xtime_cc; 722 delta = ticks = (delta < delay) ? 0 : delta - delay; 723 delta -= do_div(ticks, CLK_TICKS_PER_JIFFY); 724 init_timer_cc = init_timer_cc + delta; 725 jiffies_timer_cc = jiffies_timer_cc + delta; 726 xtime_cc = xtime_cc + delta; 727 adjust.offset = ticks * (1000000 / HZ); 728 } else { 729 /* It is earlier than we thought. */ 730 delta = ticks = xtime_cc - clock; 731 delta -= do_div(ticks, CLK_TICKS_PER_JIFFY); 732 init_timer_cc = init_timer_cc - delta; 733 jiffies_timer_cc = jiffies_timer_cc - delta; 734 xtime_cc = xtime_cc - delta; 735 adjust.offset = -ticks * (1000000 / HZ); 736 } 737 if (adjust.offset != 0) { 738 printk(KERN_NOTICE "etr: time adjusted by %li micro-seconds\n", 739 adjust.offset); 740 adjust.modes = ADJ_OFFSET_SINGLESHOT; 741 do_adjtimex(&adjust); 742 } 743 } 744 745 static void etr_sync_cpu_start(void *dummy) 746 { 747 int *in_sync = dummy; 748 749 etr_enable_sync_clock(); 750 /* 751 * This looks like a busy wait loop but it isn't. etr_sync_cpus 752 * is called on all other cpus while the TOD clocks is stopped. 753 * __udelay will stop the cpu on an enabled wait psw until the 754 * TOD is running again. 755 */ 756 while (*in_sync == 0) { 757 __udelay(1); 758 /* 759 * A different cpu changes *in_sync. Therefore use 760 * barrier() to force memory access. 761 */ 762 barrier(); 763 } 764 if (*in_sync != 1) 765 /* Didn't work. Clear per-cpu in sync bit again. */ 766 etr_disable_sync_clock(NULL); 767 /* 768 * This round of TOD syncing is done. Set the clock comparator 769 * to the next tick and let the processor continue. 770 */ 771 setup_jiffy_timer(); 772 } 773 774 static void etr_sync_cpu_end(void *dummy) 775 { 776 } 777 778 /* 779 * Sync the TOD clock using the port refered to by aibp. This port 780 * has to be enabled and the other port has to be disabled. The 781 * last eacr update has to be more than 1.6 seconds in the past. 782 */ 783 static int etr_sync_clock(struct etr_aib *aib, int port) 784 { 785 struct etr_aib *sync_port; 786 unsigned long long clock, delay; 787 int in_sync, follows; 788 int rc; 789 790 /* Check if the current aib is adjacent to the sync port aib. */ 791 sync_port = (port == 0) ? &etr_port0 : &etr_port1; 792 follows = etr_aib_follows(sync_port, aib, port); 793 memcpy(sync_port, aib, sizeof(*aib)); 794 if (!follows) 795 return -EAGAIN; 796 797 /* 798 * Catch all other cpus and make them wait until we have 799 * successfully synced the clock. smp_call_function will 800 * return after all other cpus are in etr_sync_cpu_start. 801 */ 802 in_sync = 0; 803 preempt_disable(); 804 smp_call_function(etr_sync_cpu_start,&in_sync,0,0); 805 local_irq_disable(); 806 etr_enable_sync_clock(); 807 808 /* Set clock to next OTE. */ 809 __ctl_set_bit(14, 21); 810 __ctl_set_bit(0, 29); 811 clock = ((unsigned long long) (aib->edf2.etv + 1)) << 32; 812 if (set_clock(clock) == 0) { 813 __udelay(1); /* Wait for the clock to start. */ 814 __ctl_clear_bit(0, 29); 815 __ctl_clear_bit(14, 21); 816 etr_stetr(aib); 817 /* Adjust Linux timing variables. */ 818 delay = (unsigned long long) 819 (aib->edf2.etv - sync_port->edf2.etv) << 32; 820 etr_adjust_time(clock, delay); 821 setup_jiffy_timer(); 822 /* Verify that the clock is properly set. */ 823 if (!etr_aib_follows(sync_port, aib, port)) { 824 /* Didn't work. */ 825 etr_disable_sync_clock(NULL); 826 in_sync = -EAGAIN; 827 rc = -EAGAIN; 828 } else { 829 in_sync = 1; 830 rc = 0; 831 } 832 } else { 833 /* Could not set the clock ?!? */ 834 __ctl_clear_bit(0, 29); 835 __ctl_clear_bit(14, 21); 836 etr_disable_sync_clock(NULL); 837 in_sync = -EAGAIN; 838 rc = -EAGAIN; 839 } 840 local_irq_enable(); 841 smp_call_function(etr_sync_cpu_end,NULL,0,0); 842 preempt_enable(); 843 return rc; 844 } 845 846 /* 847 * Handle the immediate effects of the different events. 848 * The port change event is used for online/offline changes. 849 */ 850 static struct etr_eacr etr_handle_events(struct etr_eacr eacr) 851 { 852 if (test_and_clear_bit(ETR_EVENT_SYNC_CHECK, &etr_events)) 853 eacr.es = 0; 854 if (test_and_clear_bit(ETR_EVENT_SWITCH_LOCAL, &etr_events)) 855 eacr.es = eacr.sl = 0; 856 if (test_and_clear_bit(ETR_EVENT_PORT_ALERT, &etr_events)) 857 etr_port0_uptodate = etr_port1_uptodate = 0; 858 859 if (test_and_clear_bit(ETR_EVENT_PORT0_CHANGE, &etr_events)) { 860 if (eacr.e0) 861 /* 862 * Port change of an enabled port. We have to 863 * assume that this can have caused an stepping 864 * port switch. 865 */ 866 etr_tolec = get_clock(); 867 eacr.p0 = etr_port0_online; 868 if (!eacr.p0) 869 eacr.e0 = 0; 870 etr_port0_uptodate = 0; 871 } 872 if (test_and_clear_bit(ETR_EVENT_PORT1_CHANGE, &etr_events)) { 873 if (eacr.e1) 874 /* 875 * Port change of an enabled port. We have to 876 * assume that this can have caused an stepping 877 * port switch. 878 */ 879 etr_tolec = get_clock(); 880 eacr.p1 = etr_port1_online; 881 if (!eacr.p1) 882 eacr.e1 = 0; 883 etr_port1_uptodate = 0; 884 } 885 clear_bit(ETR_EVENT_UPDATE, &etr_events); 886 return eacr; 887 } 888 889 /* 890 * Set up a timer that expires after the etr_tolec + 1.6 seconds if 891 * one of the ports needs an update. 892 */ 893 static void etr_set_tolec_timeout(unsigned long long now) 894 { 895 unsigned long micros; 896 897 if ((!etr_eacr.p0 || etr_port0_uptodate) && 898 (!etr_eacr.p1 || etr_port1_uptodate)) 899 return; 900 micros = (now > etr_tolec) ? ((now - etr_tolec) >> 12) : 0; 901 micros = (micros > 1600000) ? 0 : 1600000 - micros; 902 mod_timer(&etr_timer, jiffies + (micros * HZ) / 1000000 + 1); 903 } 904 905 /* 906 * Set up a time that expires after 1/2 second. 907 */ 908 static void etr_set_sync_timeout(void) 909 { 910 mod_timer(&etr_timer, jiffies + HZ/2); 911 } 912 913 /* 914 * Update the aib information for one or both ports. 915 */ 916 static struct etr_eacr etr_handle_update(struct etr_aib *aib, 917 struct etr_eacr eacr) 918 { 919 /* With both ports disabled the aib information is useless. */ 920 if (!eacr.e0 && !eacr.e1) 921 return eacr; 922 923 /* Update port0 or port1 with aib stored in etr_work_fn. */ 924 if (aib->esw.q == 0) { 925 /* Information for port 0 stored. */ 926 if (eacr.p0 && !etr_port0_uptodate) { 927 etr_port0 = *aib; 928 if (etr_port0_online) 929 etr_port0_uptodate = 1; 930 } 931 } else { 932 /* Information for port 1 stored. */ 933 if (eacr.p1 && !etr_port1_uptodate) { 934 etr_port1 = *aib; 935 if (etr_port0_online) 936 etr_port1_uptodate = 1; 937 } 938 } 939 940 /* 941 * Do not try to get the alternate port aib if the clock 942 * is not in sync yet. 943 */ 944 if (!eacr.es) 945 return eacr; 946 947 /* 948 * If steai is available we can get the information about 949 * the other port immediately. If only stetr is available the 950 * data-port bit toggle has to be used. 951 */ 952 if (test_bit(ETR_FLAG_STEAI, &etr_flags)) { 953 if (eacr.p0 && !etr_port0_uptodate) { 954 etr_steai_cv(&etr_port0, ETR_STEAI_PORT_0); 955 etr_port0_uptodate = 1; 956 } 957 if (eacr.p1 && !etr_port1_uptodate) { 958 etr_steai_cv(&etr_port1, ETR_STEAI_PORT_1); 959 etr_port1_uptodate = 1; 960 } 961 } else { 962 /* 963 * One port was updated above, if the other 964 * port is not uptodate toggle dp bit. 965 */ 966 if ((eacr.p0 && !etr_port0_uptodate) || 967 (eacr.p1 && !etr_port1_uptodate)) 968 eacr.dp ^= 1; 969 else 970 eacr.dp = 0; 971 } 972 return eacr; 973 } 974 975 /* 976 * Write new etr control register if it differs from the current one. 977 * Return 1 if etr_tolec has been updated as well. 978 */ 979 static void etr_update_eacr(struct etr_eacr eacr) 980 { 981 int dp_changed; 982 983 if (memcmp(&etr_eacr, &eacr, sizeof(eacr)) == 0) 984 /* No change, return. */ 985 return; 986 /* 987 * The disable of an active port of the change of the data port 988 * bit can/will cause a change in the data port. 989 */ 990 dp_changed = etr_eacr.e0 > eacr.e0 || etr_eacr.e1 > eacr.e1 || 991 (etr_eacr.dp ^ eacr.dp) != 0; 992 etr_eacr = eacr; 993 etr_setr(&etr_eacr); 994 if (dp_changed) 995 etr_tolec = get_clock(); 996 } 997 998 /* 999 * ETR tasklet. In this function you'll find the main logic. In 1000 * particular this is the only function that calls etr_update_eacr(), 1001 * it "controls" the etr control register. 1002 */ 1003 static void etr_work_fn(struct work_struct *work) 1004 { 1005 unsigned long long now; 1006 struct etr_eacr eacr; 1007 struct etr_aib aib; 1008 int sync_port; 1009 1010 /* Create working copy of etr_eacr. */ 1011 eacr = etr_eacr; 1012 1013 /* Check for the different events and their immediate effects. */ 1014 eacr = etr_handle_events(eacr); 1015 1016 /* Check if ETR is supposed to be active. */ 1017 eacr.ea = eacr.p0 || eacr.p1; 1018 if (!eacr.ea) { 1019 /* Both ports offline. Reset everything. */ 1020 eacr.dp = eacr.es = eacr.sl = 0; 1021 on_each_cpu(etr_disable_sync_clock, NULL, 0, 1); 1022 del_timer_sync(&etr_timer); 1023 etr_update_eacr(eacr); 1024 set_bit(ETR_FLAG_EACCES, &etr_flags); 1025 return; 1026 } 1027 1028 /* Store aib to get the current ETR status word. */ 1029 BUG_ON(etr_stetr(&aib) != 0); 1030 etr_port0.esw = etr_port1.esw = aib.esw; /* Copy status word. */ 1031 now = get_clock(); 1032 1033 /* 1034 * Update the port information if the last stepping port change 1035 * or data port change is older than 1.6 seconds. 1036 */ 1037 if (now >= etr_tolec + (1600000 << 12)) 1038 eacr = etr_handle_update(&aib, eacr); 1039 1040 /* 1041 * Select ports to enable. The prefered synchronization mode is PPS. 1042 * If a port can be enabled depends on a number of things: 1043 * 1) The port needs to be online and uptodate. A port is not 1044 * disabled just because it is not uptodate, but it is only 1045 * enabled if it is uptodate. 1046 * 2) The port needs to have the same mode (pps / etr). 1047 * 3) The port needs to be usable -> etr_port_valid() == 1 1048 * 4) To enable the second port the clock needs to be in sync. 1049 * 5) If both ports are useable and are ETR ports, the network id 1050 * has to be the same. 1051 * The eacr.sl bit is used to indicate etr mode vs. pps mode. 1052 */ 1053 if (eacr.p0 && aib.esw.psc0 == etr_lpsc_pps_mode) { 1054 eacr.sl = 0; 1055 eacr.e0 = 1; 1056 if (!etr_mode_is_pps(etr_eacr)) 1057 eacr.es = 0; 1058 if (!eacr.es || !eacr.p1 || aib.esw.psc1 != etr_lpsc_pps_mode) 1059 eacr.e1 = 0; 1060 // FIXME: uptodate checks ? 1061 else if (etr_port0_uptodate && etr_port1_uptodate) 1062 eacr.e1 = 1; 1063 sync_port = (etr_port0_uptodate && 1064 etr_port_valid(&etr_port0, 0)) ? 0 : -1; 1065 clear_bit(ETR_FLAG_EACCES, &etr_flags); 1066 } else if (eacr.p1 && aib.esw.psc1 == etr_lpsc_pps_mode) { 1067 eacr.sl = 0; 1068 eacr.e0 = 0; 1069 eacr.e1 = 1; 1070 if (!etr_mode_is_pps(etr_eacr)) 1071 eacr.es = 0; 1072 sync_port = (etr_port1_uptodate && 1073 etr_port_valid(&etr_port1, 1)) ? 1 : -1; 1074 clear_bit(ETR_FLAG_EACCES, &etr_flags); 1075 } else if (eacr.p0 && aib.esw.psc0 == etr_lpsc_operational_step) { 1076 eacr.sl = 1; 1077 eacr.e0 = 1; 1078 if (!etr_mode_is_etr(etr_eacr)) 1079 eacr.es = 0; 1080 if (!eacr.es || !eacr.p1 || 1081 aib.esw.psc1 != etr_lpsc_operational_alt) 1082 eacr.e1 = 0; 1083 else if (etr_port0_uptodate && etr_port1_uptodate && 1084 etr_compare_network(&etr_port0, &etr_port1)) 1085 eacr.e1 = 1; 1086 sync_port = (etr_port0_uptodate && 1087 etr_port_valid(&etr_port0, 0)) ? 0 : -1; 1088 clear_bit(ETR_FLAG_EACCES, &etr_flags); 1089 } else if (eacr.p1 && aib.esw.psc1 == etr_lpsc_operational_step) { 1090 eacr.sl = 1; 1091 eacr.e0 = 0; 1092 eacr.e1 = 1; 1093 if (!etr_mode_is_etr(etr_eacr)) 1094 eacr.es = 0; 1095 sync_port = (etr_port1_uptodate && 1096 etr_port_valid(&etr_port1, 1)) ? 1 : -1; 1097 clear_bit(ETR_FLAG_EACCES, &etr_flags); 1098 } else { 1099 /* Both ports not usable. */ 1100 eacr.es = eacr.sl = 0; 1101 sync_port = -1; 1102 set_bit(ETR_FLAG_EACCES, &etr_flags); 1103 } 1104 1105 /* 1106 * If the clock is in sync just update the eacr and return. 1107 * If there is no valid sync port wait for a port update. 1108 */ 1109 if (eacr.es || sync_port < 0) { 1110 etr_update_eacr(eacr); 1111 etr_set_tolec_timeout(now); 1112 return; 1113 } 1114 1115 /* 1116 * Prepare control register for clock syncing 1117 * (reset data port bit, set sync check control. 1118 */ 1119 eacr.dp = 0; 1120 eacr.es = 1; 1121 1122 /* 1123 * Update eacr and try to synchronize the clock. If the update 1124 * of eacr caused a stepping port switch (or if we have to 1125 * assume that a stepping port switch has occured) or the 1126 * clock syncing failed, reset the sync check control bit 1127 * and set up a timer to try again after 0.5 seconds 1128 */ 1129 etr_update_eacr(eacr); 1130 if (now < etr_tolec + (1600000 << 12) || 1131 etr_sync_clock(&aib, sync_port) != 0) { 1132 /* Sync failed. Try again in 1/2 second. */ 1133 eacr.es = 0; 1134 etr_update_eacr(eacr); 1135 etr_set_sync_timeout(); 1136 } else 1137 etr_set_tolec_timeout(now); 1138 } 1139 1140 /* 1141 * Sysfs interface functions 1142 */ 1143 static struct sysdev_class etr_sysclass = { 1144 .name = "etr", 1145 }; 1146 1147 static struct sys_device etr_port0_dev = { 1148 .id = 0, 1149 .cls = &etr_sysclass, 1150 }; 1151 1152 static struct sys_device etr_port1_dev = { 1153 .id = 1, 1154 .cls = &etr_sysclass, 1155 }; 1156 1157 /* 1158 * ETR class attributes 1159 */ 1160 static ssize_t etr_stepping_port_show(struct sysdev_class *class, char *buf) 1161 { 1162 return sprintf(buf, "%i\n", etr_port0.esw.p); 1163 } 1164 1165 static SYSDEV_CLASS_ATTR(stepping_port, 0400, etr_stepping_port_show, NULL); 1166 1167 static ssize_t etr_stepping_mode_show(struct sysdev_class *class, char *buf) 1168 { 1169 char *mode_str; 1170 1171 if (etr_mode_is_pps(etr_eacr)) 1172 mode_str = "pps"; 1173 else if (etr_mode_is_etr(etr_eacr)) 1174 mode_str = "etr"; 1175 else 1176 mode_str = "local"; 1177 return sprintf(buf, "%s\n", mode_str); 1178 } 1179 1180 static SYSDEV_CLASS_ATTR(stepping_mode, 0400, etr_stepping_mode_show, NULL); 1181 1182 /* 1183 * ETR port attributes 1184 */ 1185 static inline struct etr_aib *etr_aib_from_dev(struct sys_device *dev) 1186 { 1187 if (dev == &etr_port0_dev) 1188 return etr_port0_online ? &etr_port0 : NULL; 1189 else 1190 return etr_port1_online ? &etr_port1 : NULL; 1191 } 1192 1193 static ssize_t etr_online_show(struct sys_device *dev, char *buf) 1194 { 1195 unsigned int online; 1196 1197 online = (dev == &etr_port0_dev) ? etr_port0_online : etr_port1_online; 1198 return sprintf(buf, "%i\n", online); 1199 } 1200 1201 static ssize_t etr_online_store(struct sys_device *dev, 1202 const char *buf, size_t count) 1203 { 1204 unsigned int value; 1205 1206 value = simple_strtoul(buf, NULL, 0); 1207 if (value != 0 && value != 1) 1208 return -EINVAL; 1209 if (test_bit(ETR_FLAG_ENOSYS, &etr_flags)) 1210 return -ENOSYS; 1211 if (dev == &etr_port0_dev) { 1212 if (etr_port0_online == value) 1213 return count; /* Nothing to do. */ 1214 etr_port0_online = value; 1215 set_bit(ETR_EVENT_PORT0_CHANGE, &etr_events); 1216 schedule_work(&etr_work); 1217 } else { 1218 if (etr_port1_online == value) 1219 return count; /* Nothing to do. */ 1220 etr_port1_online = value; 1221 set_bit(ETR_EVENT_PORT1_CHANGE, &etr_events); 1222 schedule_work(&etr_work); 1223 } 1224 return count; 1225 } 1226 1227 static SYSDEV_ATTR(online, 0600, etr_online_show, etr_online_store); 1228 1229 static ssize_t etr_stepping_control_show(struct sys_device *dev, char *buf) 1230 { 1231 return sprintf(buf, "%i\n", (dev == &etr_port0_dev) ? 1232 etr_eacr.e0 : etr_eacr.e1); 1233 } 1234 1235 static SYSDEV_ATTR(stepping_control, 0400, etr_stepping_control_show, NULL); 1236 1237 static ssize_t etr_mode_code_show(struct sys_device *dev, char *buf) 1238 { 1239 if (!etr_port0_online && !etr_port1_online) 1240 /* Status word is not uptodate if both ports are offline. */ 1241 return -ENODATA; 1242 return sprintf(buf, "%i\n", (dev == &etr_port0_dev) ? 1243 etr_port0.esw.psc0 : etr_port0.esw.psc1); 1244 } 1245 1246 static SYSDEV_ATTR(state_code, 0400, etr_mode_code_show, NULL); 1247 1248 static ssize_t etr_untuned_show(struct sys_device *dev, char *buf) 1249 { 1250 struct etr_aib *aib = etr_aib_from_dev(dev); 1251 1252 if (!aib || !aib->slsw.v1) 1253 return -ENODATA; 1254 return sprintf(buf, "%i\n", aib->edf1.u); 1255 } 1256 1257 static SYSDEV_ATTR(untuned, 0400, etr_untuned_show, NULL); 1258 1259 static ssize_t etr_network_id_show(struct sys_device *dev, char *buf) 1260 { 1261 struct etr_aib *aib = etr_aib_from_dev(dev); 1262 1263 if (!aib || !aib->slsw.v1) 1264 return -ENODATA; 1265 return sprintf(buf, "%i\n", aib->edf1.net_id); 1266 } 1267 1268 static SYSDEV_ATTR(network, 0400, etr_network_id_show, NULL); 1269 1270 static ssize_t etr_id_show(struct sys_device *dev, char *buf) 1271 { 1272 struct etr_aib *aib = etr_aib_from_dev(dev); 1273 1274 if (!aib || !aib->slsw.v1) 1275 return -ENODATA; 1276 return sprintf(buf, "%i\n", aib->edf1.etr_id); 1277 } 1278 1279 static SYSDEV_ATTR(id, 0400, etr_id_show, NULL); 1280 1281 static ssize_t etr_port_number_show(struct sys_device *dev, char *buf) 1282 { 1283 struct etr_aib *aib = etr_aib_from_dev(dev); 1284 1285 if (!aib || !aib->slsw.v1) 1286 return -ENODATA; 1287 return sprintf(buf, "%i\n", aib->edf1.etr_pn); 1288 } 1289 1290 static SYSDEV_ATTR(port, 0400, etr_port_number_show, NULL); 1291 1292 static ssize_t etr_coupled_show(struct sys_device *dev, char *buf) 1293 { 1294 struct etr_aib *aib = etr_aib_from_dev(dev); 1295 1296 if (!aib || !aib->slsw.v3) 1297 return -ENODATA; 1298 return sprintf(buf, "%i\n", aib->edf3.c); 1299 } 1300 1301 static SYSDEV_ATTR(coupled, 0400, etr_coupled_show, NULL); 1302 1303 static ssize_t etr_local_time_show(struct sys_device *dev, char *buf) 1304 { 1305 struct etr_aib *aib = etr_aib_from_dev(dev); 1306 1307 if (!aib || !aib->slsw.v3) 1308 return -ENODATA; 1309 return sprintf(buf, "%i\n", aib->edf3.blto); 1310 } 1311 1312 static SYSDEV_ATTR(local_time, 0400, etr_local_time_show, NULL); 1313 1314 static ssize_t etr_utc_offset_show(struct sys_device *dev, char *buf) 1315 { 1316 struct etr_aib *aib = etr_aib_from_dev(dev); 1317 1318 if (!aib || !aib->slsw.v3) 1319 return -ENODATA; 1320 return sprintf(buf, "%i\n", aib->edf3.buo); 1321 } 1322 1323 static SYSDEV_ATTR(utc_offset, 0400, etr_utc_offset_show, NULL); 1324 1325 static struct sysdev_attribute *etr_port_attributes[] = { 1326 &attr_online, 1327 &attr_stepping_control, 1328 &attr_state_code, 1329 &attr_untuned, 1330 &attr_network, 1331 &attr_id, 1332 &attr_port, 1333 &attr_coupled, 1334 &attr_local_time, 1335 &attr_utc_offset, 1336 NULL 1337 }; 1338 1339 static int __init etr_register_port(struct sys_device *dev) 1340 { 1341 struct sysdev_attribute **attr; 1342 int rc; 1343 1344 rc = sysdev_register(dev); 1345 if (rc) 1346 goto out; 1347 for (attr = etr_port_attributes; *attr; attr++) { 1348 rc = sysdev_create_file(dev, *attr); 1349 if (rc) 1350 goto out_unreg; 1351 } 1352 return 0; 1353 out_unreg: 1354 for (; attr >= etr_port_attributes; attr--) 1355 sysdev_remove_file(dev, *attr); 1356 sysdev_unregister(dev); 1357 out: 1358 return rc; 1359 } 1360 1361 static void __init etr_unregister_port(struct sys_device *dev) 1362 { 1363 struct sysdev_attribute **attr; 1364 1365 for (attr = etr_port_attributes; *attr; attr++) 1366 sysdev_remove_file(dev, *attr); 1367 sysdev_unregister(dev); 1368 } 1369 1370 static int __init etr_init_sysfs(void) 1371 { 1372 int rc; 1373 1374 rc = sysdev_class_register(&etr_sysclass); 1375 if (rc) 1376 goto out; 1377 rc = sysdev_class_create_file(&etr_sysclass, &attr_stepping_port); 1378 if (rc) 1379 goto out_unreg_class; 1380 rc = sysdev_class_create_file(&etr_sysclass, &attr_stepping_mode); 1381 if (rc) 1382 goto out_remove_stepping_port; 1383 rc = etr_register_port(&etr_port0_dev); 1384 if (rc) 1385 goto out_remove_stepping_mode; 1386 rc = etr_register_port(&etr_port1_dev); 1387 if (rc) 1388 goto out_remove_port0; 1389 return 0; 1390 1391 out_remove_port0: 1392 etr_unregister_port(&etr_port0_dev); 1393 out_remove_stepping_mode: 1394 sysdev_class_remove_file(&etr_sysclass, &attr_stepping_mode); 1395 out_remove_stepping_port: 1396 sysdev_class_remove_file(&etr_sysclass, &attr_stepping_port); 1397 out_unreg_class: 1398 sysdev_class_unregister(&etr_sysclass); 1399 out: 1400 return rc; 1401 } 1402 1403 device_initcall(etr_init_sysfs); 1404